BEJ30203 MICROPROCESSOR

AND MICROCONTROLLER

Chapter 3 – Microprocessor and

Microcontroller Programming
The ARM ISA

Dr. Chessda Uttraphan, PhD

Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia
 Development Flow

Data Representation

Instruction Set

Chapter Outline
Chapter 3 – Microprocessor and Writing Assembly and C Program
Microcontroller Programming
ARM Development flow

© C. Uttraphan
Data Representation

Representation of Numbers and Characters

• Integers are often represented in byte (8-bit), halfword (16-bit), and word (32-
bit) quantities.
• Unsigned representations make the assumption that every bit signifies a
positive contribution to the value of the number.
• Signed representations make the assumption that the most significant bit is
used to create positive and negative values, and they come in three flavors:
sign-magnitude, one’s complement and two’s complement.

© C. Uttraphan
Instruction Set

▪ Moving data within the processor

▪ Memory accesses
▪ Arithmetic operations
▪ Logic operations
▪ Shift and rotate operations
▪ Program flow control

© C. Uttraphan
Instruction set – Moving data within the processor

Moving data from a register to another register

Data size = 32-bit

MOV <Rd>,<Rm> R0 0 x 12345678

R1 0 x 00000000
Destination register R2 0 x 00000000
Source register
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R2, R0

© C. Uttraphan
Instruction set – Moving data within the processor

Moving data from a register to another register

Data size = 32-bit

MOV <Rd>,<Rm> R0 0 x 12345678

R1 0 x 00000000
Destination register R2 0 x 12345678
Source register
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R2, R0

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate value into a register

32-bit Operation

MOV <Rd>,<#value> R0 0 x 00000000

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R0, #0x9

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate value into a register

32-bit Operation

MOV <Rd>,<#value> R0 0 x 00000009

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R0, #0x9

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate value into a register

32-bit Operation

MOV <Rd>,<#value> R0 0 x 00000009

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R0, #-9

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate value into a register

32-bit Operation

MOV <Rd>,<#value> R0 0 x FFFFFFF7

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOV R0, #-9

© C. Uttraphan
Instruction set – Moving data within the processor

Move wide (write a 16-bit immediate value to register)

The top 16-bit will be cleared to 0x0000

MOVW <Rd>,<#value> R0 0 x 00000000

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
(16-bit) R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOVW R0, #0x1234

© C. Uttraphan
Instruction set – Moving data within the processor

Move wide (write a 16-bit immediate value to register)

The top 16-bit will be cleared to 0x0000

MOVW <Rd>,<#value> R0 0 x 00001234

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
(16-bit) R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOVW R0, #0x1234

© C. Uttraphan
Instruction set – Moving data within the processor

Move top (write an immediate value to the top half word of

destination reg). The lower 16-bit is unchanged

MOVT <Rd>,<#value>
R0 0 x 00001234
R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
(16-bit) R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOVT R0, #0xABCD

© C. Uttraphan
Instruction set – Moving data within the processor

Move top (write an immediate value to the top half word of

destination reg). The lower 16-bit is unchanged

MOVT <Rd>,<#value>
R0 0 x ABCD1234
R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
(16-bit) R3 0 x 00000000
Example: ·
R15 0 x 00000000
MOVT R0, #0xABCD

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate complement value into a register

(Move Not) - Data size = 32-bit

MVN <Rd>,<#value> R0 0 x 00000000

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MVN R0, #1

© C. Uttraphan
Instruction set – Moving data within the processor

Moving immediate complement value into a register

(Move Not) - Data size = 32-bit

MVN <Rd>,<#value> R0 0 x FFFFFFFE

R1 0 x 00000000
Destination register R2 0 x 00000000
Immediate value
R3 0 x 00000000
Example: ·
R15 0 x 00000000
MVN R0, #1

© C. Uttraphan
Instruction set – Memory Accesses

• The ARM processors use the load and store instruction (Load and
Store architecture) to access memory instead of using the move
instructions as in CISC processors. This means data manipulations
must be done in the registers.
• For example, to add the data in two (or more) memory locations,
the data must be loaded into the register, perform the addition
process and store back into the memory.
• In this section, we will also examine the addressing modes that
can be used in order to access the memory.

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from a register into a memory location and reading data from
memory location to a register
• ARM processors use indirect addressing mode to store the data from the
register to the memory (or load from memory to register) where the address
of the memory location that we want to store/load the data must first be
loaded into the register. This register will act as a pointer to the target memory
location.
• The instruction format:

STR/LDR <Rd>, [<Rm>]

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 into a memory location
0x20000000 Source operand

STR R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 32-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 into a memory location
0x20000000 Source operand

STR R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 78
R0 0 x 20000000 20000001 0 x 56
20000002 0 x 34
R1 0 x 12345678 20000003 0 x 12
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 32-bit
Effective address
© C. Uttraphan
Instruction set – Memory Accesses (Cont..)

STR R1, [R0]

1FFFFFFF 0 x 00 The data is stored
20000000 0 x 78 starting from memory
R0 0 x 20000000 20000001 0 x 56 location 2000000 to
20000003 as each
R1 0 x 12345678 20000002 0 x 34 memory location is 8-
20000003 0 x 12 bit (byte) in size
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
• Observe that the least significant byte (0x78) of the data is stored at the least
significant address in the memory. This storing mode is called Little Endian Mode. By
default, ARM processors use the Little Endian modes.
• Some ARM processors support both little and big endian modes (Can change using
special instruction).
• However, the supported memory type also depends on the design of the rest of the
microprocessor system (bus connections, memory controllers, peripherals, and so on).
© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 (haft word) into a memory
location 0x20000000
Source operand

STRH R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 16-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 (haft word) into a memory
location 0x20000000
Source operand

STRH R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 78
R0 0 x 20000000 20000001 0 x 56
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 16-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 (byte) into a memory location
0x20000000
Source operand

STRB R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 8-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data from register R1 (byte) into a memory location
0x20000000
Source operand

STRB R1, [R0]

destination operand 1FFFFFFF 0 x 00
20000000 0 x 78
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00
Data size = 8-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading data from memory location 0x20000000 into register R2
destination operand

LDR R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x 00000000 20000004 0 x FF
20000005 0 x 34
Data size = 32-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading data from memory location 0x20000000 into register R2
destination operand

LDR R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x DDCCBBAA 20000004 0 x FF
20000005 0 x 34
Data size = 32-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading half word data from memory location 0x20000000 into
register R2
destination operand

LDRH R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x 00000000 20000004 0 x FF
20000005 0 x 34
Data size = 16-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading half word data from memory location 0x20000000 into
register R2
destination operand

LDRH R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x 0000BBAA 20000004 0 x FF
20000005 0 x 34
Data size = 16-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading one byte data from memory location 0x20000000 into
register R2
destination operand

LDRB R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x 00000000 20000004 0 x FF
20000005 0 x 34
Data size = 8-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading one byte data from memory location 0x20000000 into
register R2
destination operand

LDRB R2, [R0]

source operand 1FFFFFFF 0 x 12
20000000 0 x AA
R0 0 x 20000000 20000001 0 x BB
20000002 0 x CC
R1 0 x 12345678 20000003 0 x DD
R2 0 x 000000AA 20000004 0 x FF
20000005 0 x 34
Data size = 8-bit

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading/storing data using offset addressing mode

• The instruction format:

STR/LDR <Rd>, [<Rm>, <offset>]

• The offset can be an immediate value or a value in a
register.
• The size of the offset must be between -255 to 4095
• The base address (in Rm) combined with the offset value
to form an effective address (ea)

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using offset addressing mode

STRB R1, [R0, #2]

1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

The effective address = 0x20000000 + 2 = 0x20000002

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using offset addressing mode

STRB R1, [R0, #2]

1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 78
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

The effective address = 0x20000000 + 2 = 0x20000002

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading/storing data using post-indexed addressing mode

• The instruction format:

STR/LDR <Rd>, [<Rm>] <offset>

• The offset must an immediate value.
• The size of the offset must be between -255 to 255
• The base address (Rm) forms the effective address (ea).
• The base address is updated with the new value (offset
value) after the instruction is executed.

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using post-indexed addressing mode

STRB R1, [R0], #2

1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

The effective address = 0x20000000

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using post-indexed addressing mode

STRB R1, [R0], #2

1FFFFFFF 0 x 00
R0 is updated
20000000 0 x 78
R0 0 x 20000002 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

The effective address = 0x20000000

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Reading/storing data using pre-indexed addressing mode

• The instruction format:

STR/LDR <Rd>, [<Rm>, <offset>]!

• The offset must an immediate value.
• The size of the offset must be between -255 to 255
• The base address is updated with the new value (offset
value) before the instruction is executed.
• The base address (in Rm) combined with the offset value
to form an effective address (ea).
© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using pre-indexed addressing mode

STRB R1, [R0, #2 ]!

1FFFFFFF 0 x 00
20000000 0 x 00
R0 0 x 20000000 20000001 0 x 00
20000002 0 x 00
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

© C. Uttraphan
Instruction set – Memory Accesses (Cont..)
Storing data using pre-indexed addressing mode

STRB R1, [R0, #2 ]!

1FFFFFFF 0 x 00
R0 is updated
20000000 0 x 00
R0 0 x 20000002 20000001 0 x 00
20000002 0 x 78
R1 0 x 12345678 20000003 0 x 00
R2 0 x 00000000 20000004 0 x 00
20000005 0 x 00

The effective address = 0x20000000 + 2 = 0x20000002

© C. Uttraphan
Instruction set – Logic and Arithmetic

• Arithmetic operations are probably one of the most common types of

instructions we will use, especially if the software being written involves
manipulating large amounts of data, such as an incoming audio signal.
• Graphics algorithms, speech processing algorithms, digital controllers, and audio
processing all involve a great deal of arithmetic work, so it’s important to
understand the types of data that we have and how to perform the operation
needed in the shortest amount of time and/or space.
• Recall from Chapter 2 that the Program Status Register holds the current state of
the machine: the flags, the mode, the interrupt bits, and the Thumb bit for the
processor core.
• There are four bits, N, Z, C, and V, in the uppermost nibble that help determine
whether or not an instruction will be conditionally executed. There are several
things that will set or clear the flags:
© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

• Instructions that are specifically used for setting and clearing flags, such TST or
CMP.
• Instructions that are told to set the flags by appending an “S” to the mnemonic.
For example, MOVS would perform a MOV operation and set the flags afterward,
since the S bit is set in the instruction. We can do this with all of the ALU
instructions, so we control whether or not to update the flags.
• A direct write to the Program Status Register, where you explicitly set or clear
flags

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

The ADD instruction: ADD two 32-bit numbers

Format 1: ADDS <Rd>, <Op2>

• Op2 can be a register or an 8-bit immediate value

Format 2: ADDS <Rd>, <Rm>, <Op2>

• Op2 can be a register or an 8-bit immediate value

The ADD instruction (without suffix “S”) does not update the
flags!

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

Add data from a register to another register

Data size = 32-bit

ADDS R0, R1

R0 0 x 00000004 R0 0 x 00000006
R1 0 x 00000002 R1 0 x 00000002
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

Add immediate value to a register

Data size = 32-bit

ADDS R0, #0x100

R0 0 x 00000004 R0 0 x 00000104
R1 0 x 00000002 R1 0 x 00000002
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

Examine the flags condition after the ADD instruction

Let the content of R0 = 0x7FFFFFFF and R1 = 0x00000001

After the microprocessor executing the instruction
ADDS R2, R0, R1
The content of R0, R1, R2 and flags NZCV will be
R0 = 0x7FFFFFFF N = 1, indicates result is negative
R1 = 0x00000001 Z = 0, the result is not zero
R2 = 0x80000000 C = 0, there is no carry produce
V = 1, The result is out of 32-bit range
signed number
© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

The SUB instruction: Subtract a 32-bit number from a 32 bit

number in destination register

Format 1: SUBS <Rd>, <Op2>

• Op2 can be a register or an 8-bit immediate value

Format 2: SUBS <Rd>, <Rm>, <Op2>

• Op2 can be a register or an 8-bit immediate value

The SUB instruction (without suffix “S”) does not update the
flags!

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)

Subtract data from a register to another register

Data size = 32-bit

SUBS R0, R1

R0 0 x 00000004 R0 0 x 00000002
R1 0 x 00000002 R1 0 x 00000002
before after

Condition flags: N = 0, Z = 0, C = 1, V = 0

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Multiplication
(1) MUL <Rd>, <Rn>, <Rm> - Multiply, 32-bit result
- Can be 2 or 3 operands

(2) SMULL <RdLo>, <RdHi>, <Rn>, <Rm>

- Signed multiply, 64-bit result
- Use 2 registers to form 64-bit
space for storing the result
(RdHi and RdLo)

(3) UMULL <RdLo>, <RdHi>, <Rn>, <Rm>

- Unsigned multiply, 64-bit result
**No condition flag is affected
© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Multiplication

SMULL R0, R1, R2, R3

R0 0 x 00000000 R0 0 x FFFFFF00
R1 0 x 00000000 R1 0 x 0000007F
R2 0 x 7FFFFFFF R2 0 x 7FFFFFFF
R3 0 x 00000100 R3 0 x 00000100
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Division
(1) SDIV <Rd>, <Rn>, <Rm> - performs a signed integer
division of the value in Rn by
the value in Rm

(2) UDIV <Rd>, <Rn>, <Rm> - performs an unsigned integer

division of the value in Rn by
the value in Rm

**No condition flag is affected

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Division

SDIV R0, R1

R0 0 x FFFFFFF6 R0 0 x FFFFFFFB
R1 0 x 00000002 R1 0 x 00000002
R2 0 x 00000000 R2 0 x 00000000
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Division

UDIV R0, R1

R0 0 x 0000000A R0 0 x 00000005
R1 0 x 00000002 R1 0 x 00000002
R2 0 x 00000000 R2 0 x 00000000
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Logic Instructions (AND, OR, XOR)
(1) AND <Rd>, <Rm>, Op2
(2) ORR <Rd>, <Rm>, Op2
(3) EOR <Rd>, <Rm>, Op2
(4) BIC <Rd>, <Rm>, Op2
(5) ORN <Rd>, <Rm>, Op2

• The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR,
and OR operations on the values in Rm and Op2 (Can be a register or an
immediate value).
• The BIC instruction performs an AND operation on the bits in Rm with
the complements of the corresponding bits in the value of Op2.
• The ORN instruction performs an OR operation on the bits in Rm with
the complements of the corresponding bits in the value of Op2.
© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Logic operations

AND R0, R1, R2

R0 0 x 00000000 R0 0 x 00001200
R1 0 x 00001234 R1 0 x 00001234
R2 0 x 0000FF00 R2 0 x 0000FF00
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Instruction for Logic operations

BIC R0, R1, R2

R0 0 x 00000000 R0 0 x 00000034
R1 0 x 00001234 R1 0 x 00001234
R2 0 x 0000FF00 R2 0 x 0000FF00
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Shift and Rotate instructions
(1) ASR <Rd>, <Rm>, Op2 - Arithmetic shift right
(2) LSL <Rd>, <Rm>, Op2 - Logical shift left
(3) LSR <Rd>, <Rm>, Op2 - Logical shift right
(4) ROR <Rd>, <Rm>, Op2 - Rotate right
(5) RRX <Rd>, <Rm> - Rotate right with extend

Rm is the register holding the value to be shifted, Op2 is the shift

length (can be an immediate value or a value in the register)

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Shift and Rotate instructions

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Shift and Rotate instructions

LSL R0, R1, #4

R0 0 x 00000000 R0 0 x 000000F0
R1 0 x 0000000F R1 0 x 0000000F
R2 0 x 00000000 R2 0 x 00000000
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Instruction set – Logic and Arithmetic (Cont..)
Shift and Rotate instructions

ASR R0, R1, R2

R0 0 x 00000000 R0 0 x FF050000
R1 0 x F050000F R1 0 x F050000F
R2 0 x 00000004 R2 0 x 00000004
R3 0 x 00000000 R3 0 x 00000000
before after

© C. Uttraphan
Program flow control

Decisions and Conditional Branches

• Most conditional branches in ARM processors use flags in the APSR to determine whether a
branch should be carried out. In the APSR, there are five flag bits; four of them are used for
branch decisions (N, Z, V and C).
• There is another flag, called the Q flag. It is for saturation math operations and is not used for
conditional branches.
• With combinations of the four flags (N, Z, C, and V ), 15 branch conditions are defined. Using
these conditions, branch instructions can be written as, for example,

BEQ label ;Branch to address 'label' if Z flag is set

© C. Uttraphan
Program flow control

Review

© C. Uttraphan
Program flow control

© C. Uttraphan
Writing Assembly Program

Assembly directive
• Assembly directives are instructions to the assembler for creating areas of code, aligning data, marking
the end of your code, and so forth. These are unlike processor instructions, which tell the processor to
add two numbers or jump somewhere in your code, since they never turn into actual machine
instructions.

Directive Uses
AREA Defines a block of code or data
EQU Equates a symbol to a numeric constant
ENTRY Declares an entry point to the program
DCB, DCW, DCD Allocates memory and specifies initial runtime contents
ALIGN Aligns data or code to a particular memory boundary
END Designates the end of a source file
EXPORT declares a symbol that can be used by the linker to resolve
symbol references in separate object and library files.

© C. Uttraphan
Writing Assembly Program
Assembly program example

Label Operands Comments

Mnemonics
© C. Uttraphan
Writing Assembly Program

Allocates memory and specifies initial runtime contents

00000100 0 x 10
00000101 0 x 11
MyData DCB 0x10, 0x11, 0x12, 0x13 00000102 0 x 12
00000103 0 x 13
00000104 0 x 00

00000100 0 x 48
MyData DCB “HELLO” 00000101 0 x 45
00000102 0 x 4C
00000103 0 x 4C
00000104 0 x 4F

© C. Uttraphan
Writing Assembly Program

Allocates memory and specifies initial runtime contents

00000100 0 x 11
00000101 0 x 10
MyData DCW 0x1011, 0x1213 00000102 0 x 13
00000103 0 x 12
00000104 0 x 00

00000100 0 x 13
MyData DCD 0x10111213 00000101 0 x 12
00000102 0 x 11
00000103 0 x 10
00000104 0 x 00

© C. Uttraphan
Writing Assembly Program
Load the memory address of the data into a register

LDR R0,=MyData 00000100 0 x 10

.
.
00000101 0 x 11
MyData DCB 0x10, 0x11, 0x12, 0x13 00000102 0 x 12
00000103 0 x 13
R0 0 x 00000100 00000104 0 x 00

Load data from memory (predefined) into a register

00000100 0 x 10
LDRB R0,MyData
. 00000101 0 x 11
. 00000102 0 x 12
MyData DCB 0x10, 0x11, 0x12, 0x13 00000103 0 x 13
00000104 0 x 00
R0 0 x 00000010
© C. Uttraphan
C codes and Assembly codes
If-then-else statement
if (A > B) Assume: A in R0, B in R1 and C in R2
C = 1;
else CMP R0,R1
C = -1; BGT next1
MOV R2,#-1
C codes
B next2
next1 MOV R2,#1
next2 ....
yes
A>B? C=1 Assembly codes
no

C = -1

© C. Uttraphan
C codes and Assembly codes
For-loop statement
for (i=1;i<10;i++) R2 holds the memory address
A[i] = 0xF0;
MOV R0,#1
C codes
MOV R1,#0xF0
loop STRB R1,[R2],#1
i=1 ADDS R0,#1
CMP R0,#10
A[i] = 0xF0 BLT loop

Assembly codes post-indexed

i = i+1
A[1] 0x101 0x000000F0 R1

yes R2 0x00000101 A[2] 0x102

A[3] 0x103
i < 10?

no A[9] 0x109
© C. Uttraphan
C codes and Assembly codes
While statement
int A = 10
MOV R0,#10
while(A != 0)
loop SUBS R0,#1
A = A - 1;
BNE loop
C codes
Assembly codes

no
A=0? A=A-1

yes

© C. Uttraphan
Example 1

• Since any real code will have something more than just arithmetic and
control instructions, the whole notion of looping through code needs to be
addressed. We need the ability to execute a section of code multiple times,
so we’re going to start off the discussion of loops by looking at a real
problem.
• Suppose that we want to move a block of data from memory address
location 0x20000000 – 0x2000001F to a memory address location
0x20000020 – 0x2000003F

© C. Uttraphan
Example 1

20000000 0 x 12 20000020 0 x 12
20000001 0 x 13 20000021 0 x 13
20000002 0 x 14 20000022 0 x 14
20000003 0 x 15 20000023 0 x 15

2000001D 0 x A1 2000003D 0 x A1
2000001E 0 x A2 2000003E 0 x A2
2000001F 0 x A3 2000003F 0 x A3

© C. Uttraphan
Example 1

1 word 2 word 3 word 4 word 5 word 6 word 7 word 8 word

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
0x20000000
0x20000020
0x20000040
0x20000060
0x20000080

© C. Uttraphan
Example 1
Flowchart
A
start
Move data word
Mem[R1] <- R2 from R2 to mem
R0 <- 0x20000000 pointer1

pointer2 R1 <- R1 + 4 Update the pointer

R1 <- 0x20000020

Increment the
Counter, to R3 <- R3 + 1 counter
R3 <- 0 count up to 8 words

Move data word no Last location

from mem to R2 R2 <- Mem[R0] R3 = 8 ? reached?

yes
Update the pointer to
R0 <- R0 + 4 point to the next word
end
A
© C. Uttraphan
Example 1

Assembly codes

MOVW R0,#0x0000 ;Set R0 as pointer for 0x20000000

MOVT R0,#0x2000
MOVW R1,#0x0020 ;Set R0 as pointer for 0x20000020
MOVT R1,#0x2000
MOV R3,#0 ;R3 is a Counter, Initialize to 0

L1 LDR R2,[R0],#4 ;Load 4 byte (32-bit) data from

;memory to R2
STR R2,[R1],#4 ;Store to new memory location
ADDS R3,#1 ;Update the Counter
CMP R3,#8 ;is the Counter = 8?
BNE L1 ;if not, repeat

© C. Uttraphan
Example 2
Suppose that we had a register
start
containing a binary value that needed to
be normalized. In other words, we need
to have the leading 1 in the most no
significant bit. MSB = 1? Shift left

yes

end
Assembly codes

MOVW R0,#0x1234 ;The number to be normalized in R0

MOVS R1,R0 ;Move to R1 to update N flag
BMI done ;if set, done
L1 LSLS R1,#1 ;if not, logical shift left
BMI done ;if flag N = 1, done
B L1 ;if not, repeat
done ....

© C. Uttraphan
Stack and Subroutine

Stack
• Stacks are conceptually Last In-First Out (LIFO) queues that can be used to describe systems
from the architectural level down to the hardware level.

• When referring to hardware, generally these are areas in memory that have a variable length
and a fixed starting address.

• Data is written, or pushed, onto the top of the stack, and also read, or popped, from the top
of the stack, where the processor adjusts the stack pointer before or after each operation.

• ARM processors have a stack pointer, register R13, which holds the address of either the next
empty entry or the last filled entry in the queue.

© C. Uttraphan
Stack and Subroutine
Stack

Hardware stack concept in memory

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack

STK_AD EQU 0x20000100 ;Define stack address

LDR SP,=STK_AD ;Load stack address to stack
;pointer
LDR R0,=0x12345678 ;Load 32-bit value to R0
LDR R1,=0x1A2A3A4A ;Load 32-bit value to R1
PUSH {R0} ;Push R0 to top of the stack (TOS)
PUSH {R1} ;Push R1 to TOS
POP {R2} ;Pop value from TOS to R2
POP {R2} ;Pop value from TOS to R2

Student are required to run the code in Keil MDK and observe the
value in registers and stack!!!

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack
Initial values in registers and stack

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 00000000
R2 0 x 00000000 200000FC 0 x 00000000
20000100 0 x 00000000
R13 (SP) 0 x 20000100

Stack’s base address

EQU 0x20000100
LDR SP,=STK_AD
LDR R0,=0x12345678
LDR R1,=0x1A2A3A4A

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 00000000
R2 0 x 00000000 TOS 200000FC 0 x 78563412
20000100 0 x 00000000
R13 (SP) 0 x 200000FC

PUSH {R0}

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A TOS 200000F8 0 x 4A3A2A1A
R2 0 x 00000000 200000FC 0 x 78563412
20000100 0 x 00000000
R13 (SP) 0 x 200000F8

PUSH {R1}

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 4A3A2A1A
R2 0 x 1A2A3A4A TOS 200000FC 0 x 78563412
20000100 0 x 00000000
R13 (SP) 0 x 200000FC

POP {R2}

© C. Uttraphan
Stack and Subroutine
Example of push and pop data to/from stack

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 4A3A2A1A
R2 0 x 12345678 200000FC 0 x 78563412
20000100 0 x 00000000
R13 (SP) 0 x 20000100

Stack’s base address

POP {R2}

© C. Uttraphan
Stack and Subroutine
Subroutine
• Most large programs consist of many smaller blocks of code, or subroutines, where
functions can be called at will, such as a print routine or a complicated arithmetic function
like a logarithm.

• A large task can be described more easily this way. Subroutines also allow programmers to
write and test small blocks of code first, building on the knowledge that they’ve been
proven to work.

• Subroutine is called with the BL (branch and link) instruction. This instruction transfers the
branch target (the starting address of the subroutine) into the Program Counter and also
transfers the return address into the Link Register, R14, so that the subroutine can return
back to the calling program.

• Subroutines can also call other subroutines, but caution must be taken to ensure
information is not lost in the process.
© C. Uttraphan
Stack and Subroutine
Subroutine Example

__main LDR R0,=0x12345678 ;Load value in R0

LDR R1,=0xA1A2A3A4 ;Load value in R1
BL Routine1 ;Call Routine1
LSL R0,#10 ;Data processing1
LSR R1,#10
ADDS R2,R0,R1
stop B stop ;Loop forever (required in
;hardware programming)
;This is subroutine
Routine1
PUSH {R0,R1} ;Save the values of R0 and R1
MOV R0,#0x20 ;Data processing 2
SUBS R1,R0,#0x05
POP {R0,R1} ;Restore the values of R0 and R1
BX LR ;Return from subroutine

© C. Uttraphan
Stack and Subroutine
How the microprocessor executes the subroutine
Initial values in registers and stack just before execute the BL Routine1 instruction

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 00000000
R2 0 x 00000000 200000FC 0 x 00000000
20000100 0 x 00000000
R13 (SP) 0 x 00000100
R14 (LR) 0 x 00000000
Stack’s base address
R15 (PC) 0 x 00000408

PC points to the address of BL instruction

© C. Uttraphan
Stack and Subroutine
How the microprocessor executes the subroutine
After executing the BL Routine1 instruction

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 00000000
R2 0 x 00000000 200000FC 0 x 00000000
20000100 0 x 00000000
R13 (SP) 0 x 00000100
R14 (LR) 0 x 0000040D
Stack’s base address
R15 (PC) 0 x 00000418

PC points to Routine1 address

LR is loaded with the return address + 1
© C. Uttraphan
Stack and Subroutine
How the microprocessor executes the subroutine

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A TOS 200000F8 0 x 78563412
R2 0 x 00000000 200000FC 0 x 4A3A2A1A
20000100 0 x 00000000
R13 (SP) 0 x 200000F8
R14 (LR) 0 x 0000040D
PUSH {R0,R1}
R15 (PC) 0 x 0000041A

© C. Uttraphan
Stack and Subroutine
How the microprocessor executes the subroutine

R0 0 x 00000020 200000F4 0 x 00000000

R1 0 x 0000001B TOS 200000F8 0 x 78563412
R2 0 x 00000000 200000FC 0 x 4A3A2A1A
20000100 0 x 00000000
R13 (SP) 0 x 200000F8
R14 (LR) 0 x 00000405
MOV R0,#0x20
R15 (PC) 0 x 00000420 SUBS R1,R0,#0x05

© C. Uttraphan
Stack and Subroutine
How the microprocessor executes the subroutine

R0 0 x 12345678 200000F4 0 x 00000000

R1 0 x 1A2A3A4A 200000F8 0 x 78563412
R2 0 x 00000000 200000FC 0 x 4A3A2A1A
20000100 0 x 00000000
R13 (SP) 0 x 20000100
R14 (LR) 0 x 0000040D
POP {R0,R1}
R15 (PC) 0 x 0000040C BX LR

PC = LR – 1

© C. Uttraphan
Stack and Subroutine

Nested Subroutine (Call subroutine from a subroutine)

• In the previous example, there is only one subroutine, hence, only one return address is
needed to be kept track.

• However, if we need to call another subroutine from a subroutine, there will be two return
addresses that need to be saved. Therefore, BX instruction cannot be used in this case.

• In nested subroutine, the stack is used to store the value of LR as shown in the next
example.

© C. Uttraphan
Stack and Subroutine
__main LDR SP,=0x20000100 ;Stack address
LDR R0,=0x12345678 ;Load value in R0
LDR R1,=0xA1A2A3A4 ;Load value in R1
BL Routine1 ;Call Routine1
MOV R0,#0x10 ;Data processing1
MOV R1,#0x10
ADDS R2,R0,R1
stop B stop ;Loop forever (required in
;hardware programming)
Routine1
PUSH {LR} ;Save the values of LR
MOV R0,#0x20 ;Data processing 2
SUBS R1,R0,#0x05
BL Routine2 ;Call Routine2
POP {PC} ;Restore the values of return
;address to PC
Routine2
MOV R0,#0x30 ;Data processing 3
SUBS R0,R0,#0x05
BX LR ;Restore the values of R0, R1, and
;return to main loop
© C. Uttraphan
Exercise

1. Write a sequence of instruction to clear bit no 7-0 of register R0.

2. Write a sequence of instruction to set bit no 7-0 of register R0.
3. Without using the MUL instruction, give instructions that multiply register
R4 by 135.
4. Suppose register R0 contains the value 0xBBFF0000. Give the instruction
and register value for R1 that would insert the value 0x7777 into the lower
half of register R0, so that the final value is 0xBBFF7777.
5. Write a program that converts a binary value between 0 and 15 into its
ASCII representation.
6. Write a program that takes character data “a” through “z” and returns the
character in uppercase.
7. Write a program that will reverse the word “HELLO” to “OLLEH” in
memory location 0x20000010

© C. Uttraphan