A Translation Method of Ladder Diagram on PLC

with Application to a Manufacturing Process

Hyung Seok Kimy, Dong Sung Kimy, Naehyuck Changz, Wook Hyun Kwony
y School of Electrical Eng., Seoul National University, Seoul, Korea
z Computer Eng., Seoul National University, Seoul, Korea

Abstract is important as a measure of its performance. Thus,

increase of instructions puts a burden to performance
This paper1 proposes a translation method for PLCs of the PLC.
(Programmable logic controllers) used in most au- To improve speed of the PLC, architectures of a
tomation systems. It describes detailed steps of the new processor have been suggested. They developed
method that converts from a ladder diagram directly specic processors for PLC to raise its performance,
to a native code. A general-purpose DSP (Digital sig- using parallel processing methods 5{7] or application-
nal processor) based PLC with the method is imple- specic IC (ASIC) design methods 8{10]. For exam-
mented. A benchmark test in an automotive manu- ple, researches on reduced instruction set computer
facturing process shows that the proposed translation (RISC) put typical instructions of the PLC into a
method fairly speeds up execution in comparison with PLC-specic processor 5,6]. This method seems e
-
existing interpretation methods. cient to increase the execution speed. But it is di
cult
to add new instructions to the processor and to de-
1 Introduction velop it within a short time. Koo et al. 5] insist that
the PLC based on a general-purpose processor has less
Programmable logic controller (PLC) was origi-
nally developed to replace electro-magnetic relay cir-
cuit. It is widely used for implementing systems based
on logic, sequencing, timing, counting and arithmetic
1, 2]. PLCs are the backbone of most automation
projects of the process control and instrumentation
sector. Automation of production lines and manufac-
turing processes will lead to the development of the
manless factory where there is no longer any signif-
icant requirement for production workers or opera-
tors. Such levels of automation will not be achievable
without development of control systems, particularly
PLCs 11].
As automation systems progress, works that the
PLC carries out become more complex. To treat them
e
ciently, it has retained more than a hundred kinds
of instructions. Of the instructions, the proportion of
special instructions such as PID and oating-point op-
erations has been increased with the extension of its
adaptable range. These instructions need much time
to execute. The execution time of the PLC program
ciency of this translation method.
1 This work is supported in part by the POSCON, Ltd.,
Korea
1
performance than one based on a specic-purpose pro-
cessor.
But the general-purpose processor has some prac-
tical advantages. It has the price/performance curve
that grows at a very fast rate. It also can be manu-
factured at lower cost in a shorter time through the
improvement related to the software. The translator
of PLC languages occupies a main part of the software.
The translator should convert the LD to another code
close to the machine language. But it is not easy to
translate the graphical LD into the native code of a
processor because of a semantic gap between them.
Existing translation methods have not considered it
seriously. They convert an LD program to interme-
diate codes that consists of code matching with each
node of the PLC. On their operation, they fetch inter-
mediate codes from the memory and then call a rou-
tine of corresponding program block. They usually
require a long time even on high-performance RISC
processors because they need many branches. Accord-
ingly, a method is needed to overcome slow speed and
low e
To improve the performance of the PLC on the
general-purpose processor, it is essential to translate
the graphical LD to the native code properly. short
This paper proposes the proper translation method of a X0 : 0

LD and describes implementation of it and application token

X1 : 1
X2 : 0
to an automotive manufacturing process.
...
...
. analyzer .

The paper is organized as following. Section 2 in-

.
... b .
.
.

troduces existing LD translation approach in the PLC. LD e

Y0 : 0
Y1 : 1
Section 3 proposes our translation method of LD. It
application
Y2 : 1
prorgram ¨è
also describes implementation of a PLC system for
mnemonic .
operation .

test. Section 4 evaluates translation methods with routine

c

application to an automobile manufacturing process.

d

Finally, the conclusion with future works is drawn in

application system
I/O table
program program

Section 5.
memory
memory memory

a. fetch application program by the command

2 Common Approach
b. call the execution routine that is associated with
each command
c. translate operands and read data in I/O table

Figure 1 shows a common structure of a PLC. The memory

d. execute proper operation
microprocessor moves state of a plant to an I/O table e. go to a, then repeat a-e
memory through input devices, executes application
program stored in the application program memory,
and controls the plant by transmitting calculated out- Figure 2: Block diagram of the LD interpreter
put values through the output devices. Figure 2 de-
the processor fetches intermediate codes of application
program stored in memory and alternates them with
programmable logic controller

programming
application
input input an execution routine prepared already. Accordingly,
a method is needed to overcome slow speed and low
program
panel circuit device
memory

e
ciency of this processing scheme.
I/O
micro
table
processor
memory
system
output output
program

3 Translation Method of LD
circuit device
memory

power supplier

3.1 Architecture
Figure 1: A general structure of PLC Figure 3 represents main ow of the proposed trans-
lation method of PLC by the block diagram. The rst
scribes operation to execute the application program.
After the PLC starts to control a plant, its memo- ladder diagram
ries repeat operation of gure 2. As a kind of con- application
LD/mnemonic
converter
troller, PLC itself includes little user interface gener- program

ally. Instead, a programming unit similar to a calcula- macro

tor or a computer keyboard is connected to the CPU compiler

unit of the PLC through the communication port.

The programmer draws LD directly with the program- assembler
ming unit to make application programs. Then, PLC
translates this program into intermediate codes asso-
ciated with each element of LD, and loads them into PLC processor download
application program memory. Its translator fetches
intermediate codes and calls routine of correspond-
ing execution codes. As shown in the gure 2, `call' Figure 3: Block diagram of the proposed method
and `return' instructions appear frequently in existing
method. They usually require a long time even on input is LD application program and the last output
high-performance RISC processors. Execution time is executable binary code specic to the PLC proces-
of the application program seems to be long because sor. First, in the LD/mnemonics converter, an LD

2
application program is converted to the program that ;M_LDID 0ffffh,0ffffh,R11
LDHI 0ffffh,R11
;; LD X3
;M_LDIA 08000h,03h,R0
;; ORB
LDI R10,R0

consists of LD mnemonics. This process is shown in OR

;; LD X1
0ffffh,R11 LDPK
LDI
08000h
@03h,R0
LSH 1,R10
;M_LDID 08000h,0h,R1

gure 4. The (a) of gure 4 is an example of simple ;M_LDIA 08000h,01h,R0

LDPK 08000h
AND
LSH
R11,R0
-1,R10
LDHI
OR
08000h,R1
0h,R1

LD block. The (b) describes a tree for representing LDI

AND
LSH
@01h,R0
R11,R0
-1,R10 LD003:
OR
BR
R0,R10
LD003
AND
OR
;; ANDB
R1,R0
R0,R10

OR R0,R10 ;; AND X4 LDI R10,R0

BR LD001 ;M_LDIA 08000h,04h,R0 LSH 1,R10
1 2 LD001: LDPK 08000h ;M_LDID 07fffh,0ffffh,R1
A B ;; LD X2 LDI @04h,R0 LDHI 07fffh,R1
;M_LDIA 08000h,02h,R0 AND R11,R0 OR 0ffffh,R1
LDPK 08000h ;M_LDID 07fffh,0ffffh,R1 OR R1,R0
3 4 LDI @02h,R0 LDHI 07fffh,R1 AND R0,R10
AND R11,R0 OR 0ffffh,R1
C
LSH -1,R10 OR R1,R0
OR R0,R10 AND R0,R10
BR LD002 BR AND001
LD002: AND001:
(a)

A LOAD 1
Figure 5: assembly code
ANDBLK
LOAD 2
B

labels such as `LD001' and `AND001' in symbol ta-

LOAD 3
1 ORBLK
C

ble, then the second pass refers to the table and con-
C AND 4
2 AND B

verts assmbly code to binary code. The PLC has a

ORBLK

number of branches because it decides, by logic oper-

ANDBLK A
3 4

ation, whether it executes a rung or not. It requires

1 or 0

(b)

a large memory. The PLC-specic assembler that re-

(c)

Figure 4: LD/mnemonic conversion duces both the size of the memory and the translation
time is shown in gure 6. PLC mnemonics have in-
Boolean equation (1). It makes translation of graph- dependent relation with each other except ones with
ical LD block into text format easy. A, B and C in ow control or global variable. Using this, at step
(b) pull the latest data from the stack, then carry out 1, addresses of labels commonly used with another
AND or OR logical operation with them. mnemonic are stored in a symbol table. After pro-
cessing labels and global variables, the assembly code
output(on=of f ) = 1 ^ 2 _ 3 ^ 4]] (1) block that matches with each mnemonic passes the
assembler in the order of 2,3,4,5... steps. Whenever
`_' and `^' represent `and' and `or' logical opera- a block nishes conversion, all data from the symbol
tions respectively. The (c) is a mnemonic program as table are erased except global data. Then, memory
an output of the LD/mnemonic converter. `LOAD' reduction and less translation time are achieved. As a
pushes the value of operand(the point of PLC) to
stack. `ANDBLOCK' and `ORBLOCK' operate _
and ^ logical operation respectively with the latest
;; LD X1
;M_LDIA 08000h,01h,R0
LDPK 08000h
LDI @01h,R0

blocks calculated by `AND' or `OR'. A stack is needed

2 AND
LSH
R11,R0
-1,R10
3
OR R0,R10

for these logical operations, a general purpose regis-

BR LD001
LD001:

ter that globally not be overwritten for other purpose

;; LD X2
;M_LDIA 08000h,02h,R0
LDPK 08000h
LDI @02h,R0

can be used. Through these steps, LD is changed to

1 4 AND
LSH
R11,R0
-1,R10
5 symbol table
OR R0,R10

uniform text format similar to general assembly code.

BR LD002
LD002: LD001:
;; LD X3 LD002:

Thus, its lexical analysis becomes easy.

;M_LDIA 08000h,03h,R0
LDPK 08000h
LDI @03h,R0 LD003:
6 7
The macro compiler translates each mnemonic to
AND R11,R0

..
AND001:
LSH -1,R10
OR R0,R10

assembly code block specic to the main processor.

BR LD003
LD003:

The point operands such as `X0' and `Y20' is replaced .. .. .. .

by matching addresses, constant operands matching . . .
constants. At this process, the macrocompiler noti-
es programmer of programming errors of the source Figure 6: pass of the assembler
code and optimizes code for length and execution time
of machine code. Figure 5 shows resultant assembly
code in TMS320C40 DSP. The assembler generates ex- nal result of the LD translator, the executable binary
ecutable binary code with the assembly code. In the code produced by the assembler is transmitted to the
two-pass assembler, the rst pass stores addresses of PLC and resides in its application program memory.

3
3.2 Implementation of PLC mnemonics. For both methods, the graph of mean
We have built a large-scale PLC based on digital sig- value of measured execution time of various kinds of
nal processor (DSP) TMS320C40. It supports about LD mnemonics is shown in gure 7. The mnemon-
200 mnemonics including logical operations, arith-
metic operations, trigonometric functions, PID etc. It
also has 10,000 points including I/O points and tempo-
ral registers. Serial communication port has been set
to connect the PLC to the loader, IBM-PC. Internal
cache is disabled in order to measure constant execu-
tion time. The wait state of the I/O table memory
and the application program memory is set to 50ns,
25ns respectively. Both translation methods are im-
plemented for their performance evaluation.
4 Performance Evaluation
cient when LD mnemon-
4.1 Execution Time of Mnemonics
Translation time and execution time can be consid-
ered as main factors for performance evaluation. First,
the translation time of the existing method is much
ics are classied according to their purpose and form,
based on the grouping of a PLC manufacturers 12,13].
Common arithmetic mnemonic generally has three
operands which consist of two sources and one des-
tination. Mnemonics with three operands occupies
most of common PLC mnemonics. They provide the
largest reduction of the execution times because they
pass operand routine three times at least and fetch the
intermediate code in memory more frequently. On the
contrary, ow control mnemonics are in the least re-
duction since ow control mnemonics have an operand
as label and have brief machine code. Accordingly,
the proposed structure is e
ics have more operands and longer code.
4.2 Application
Y020 Y021 Y022 Y023

shorter than that of the proposed method. To get M0

executable binary code using the proposed method, SHUT

UP
SHUT
ADV
SHUT
DOWN
SHUT
RET
SHUT
UP

the LD application program must pass through pro-

M0 M1 Y021

cedure of several steps such as LD-mnemonics con-

Y020

HOME SHUT SHUT

START

verter, macro compiler and assembler. Besides, le

POS ADV UP
Y020

input/output is taken at every step. But, usually,

once an application program of PLC has been xed,
SHUT
UP

without modication of the program it is used for a

Y020 X000 Y022

Y021

long time, about several years. Stopping PLC opera- SHUT

UP
SHUT
UP LS
SHUT
DOWN
SHUT
ADV

tion for update of the application program can cause Y021

a great loss to the users. Since the user does not nd a

di
culty in time due to infrequent translation, trans-
SHUT
ADV
Y020 X001 Y023

lation time is not related to the performance of PLC. Y020

Therefore, it is concluded that the element for eval- SHUT

ADV
SHUT
ADV LS
SHUT
RET
SHUT
DOWN

uating the LD translator is not translation time but Y022

execution time of the application program. SHUT

DOWN
Y022 X0002 X0003

Y023
SHUT
(T 0 ) basic SHUT
DOWN
SHUT SHUT
DOWN RET LS RET
LS
(T 1 ) tranfer Y023

(T 2 ) timer,counter
SHUT
(T 3 ) compare RET

(T 4 ) common arithmetic
(T 5 )
special arithmetic Figure 8: LD for automotive process
(T 6 ) flow control

0 2 4 6 8 Figure 8 is an example of the LD program for auto-

matic control of an shuttle process used in an automo-
tive manufacturing process. The operation sequence
proposed existing

of the process is Home Position!Shuttle Up!Shuttle

Figure 7: execution time of LD mnemonics Advance!Shuttle Down !Shuttle Return!Home Po-
sition. LD programming can be done for various pu-
We measured the execution time of the LD poses and is not unigue. The arithmetic operations

4
such as add, mul and sin can be assigned as outputs
in LD. They also can be represented as a form of fuc- 6

tion block (FB). These non-logical operations are di-

vided into common arithmetics (add,sub,mul etc) and
5
N exe =1200

special arithmetics (sin,cos,PID etc). To analyze re- execution 4

the size of
program
time

special (P 2 ) (msec)
3
arithmetic (P 5 ) timer,counter
1.0% 1.5% flow control
common
arithmetic (P 6 ) 2
2.2%
(P 4 ) 6.0% N exe =300

(P 3 ) comparison 1 N exe =1200

9.3%
transfer
(P 1 ) 12.0% 20% 40% 60% 80% 100%
basic
ratio of basic mnemonic in application program
68.9%

existing structure

proposed structure

Figure 9: frequency of mnemonics in the process

Figure 10: Execution time of a program in each
duction of execution time of an application program, a method
ratio of mnemonics included in the program should be
known. Figure 9 is a result of practical examining ap-
plication programs on the automotive manufacturing At the proposed method, memory requirement is
process. We analyzed the execution time of an appli-
cation program, changing total number of mnemonics M = 9:790Nexe (Bytes) (4)
and percentage of basic mnemonics respectively. The
following equation is calculation of execution time of Unless Nexe is exceedingly large in the process, M does
an application program is T0T6 mean execution time not require absurdly much memory compared with
of each class of the mnemonics, as the result of this M.0

experiment. Nexe is total number of LD mnemonics

in the program.
Texe = T0  Pbasic  Nexe (2)
6

X 
Pi
+ Ti   (1 ; Pbasic )  Nexe
i=1 (1 ; 0:689)
The percentage of basic mnemonic, Pbasic , is assumed
to be changed according to the application program.
But P1 P6 are constants and ratio between them is
assumed to be constant. Figure 10 represents a rela-
tion between ratio of basic LD mnemonics and execu-
tion time of application program. It also shows change
of the execution time when increasing Nexe , the num-
ber of mnemonics, in a program by three hundreds.
It also can be noted that dierence between the total
execution times is decreased if the program uses basic
mnemonics frequently.
Memory requirement of each method is calculated
and the result is represented in (3),(4). NPLC is the
number of mnemonics that the PLC serves. On the
existing method, memory requirement is
M = 2:114Nexe + 18:973NPLC + 183 (Bytes) (3)
0
5 Conclusion
We have described a method to translate LD into
the native code of the processor. The improvement
of the execution time has been considered in order to
acquire the high-speed PLC. In the proposed method,
an executable code is generated without converting
the LD application program to the intermediate code.
It includes three steps of the LD/mnemonic converter,
the macro compiler and the assembler. We have built
a high-speed DSP-based PLC system with the trans-
lation method. The execution time of each mnemonic
has been measured on the PLC.
When the proposed translation method is applied
to an automotive manufacturing process, the execu-
tion time of the application programs used by the
process has been analyzed. The proposed translation
method results in better performance. The memory
requirement of it can be much more as a tradeo of
speed. But the proposed translation method does not
require nonrealistic memory size unless the application
program of the process is very long.

5
 As the role of the PLC is larger in various elds, fur- 12] POSFA PLC Programming manual, POSCON,
ther studies on e
cient translation method will be re- 1995
quired. They can be investigated with execution time 13] MCPU Programming manual, LG industrial elec-
and memory requirement. The translation method of tronics, 1996
other programming languages of the PLC may be valu-
able as well.

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