Q1)What is a Combinational PLD ? Describe its classification.

Definition: A combinational PLD is an integrated circuit with programmable gates. It comprises of an

AND array and an OR array in order to provide an AND-OR implementation on of logic functions in the
sum of products form. Three fundamental types PLD a) The PROM (Programmable Read Only Memory)
has a fixed AND array (constructed as a decoder) and programmable connections for the output OR
array. The PROM implements Boolean functions in sum-of-minterms form. b) PAL (Programmable Array
Logic) device has a programmable AND array and fixed connections for the OR array. c)PLA
(Programmable Logic Array) has programmable connections for both AND and OR arrays. So, it is the
most flexible type of PLD.
What are the advantages of PLDS over fixed function ICs (1)Short design cycle.(2) Low development
cost.(3) Reduction in board space requirements.(4) Reduction in power requirements. (5) Design
security.(6) Compact circuitry.(7)Higher switching speed.(8)Higher densities.(9)Lower quantity
production cost.(10) Design security
Q2)What is a ROM/ PROM? or Define ROM. Write short note on PROM as PLD.
1)The input lines to the AND array are hard-wired and the output lines to the OR array are
programmable.2)Each AND gate generates one of the possible AND products minterm .
Block diagram of PROM =(1)Read-only memory (ROM) is a basic memory unit of any computer
system.(2)ROM is a non-volatile memory, where the stored data cannot be erased even when the
power is turned off.(3)PROM consists of fixed AND array and programmable OR array. The block
diagram has n inputs and m output Features of PROM(1)PROMS are used in digital electronic devices
to store permanent data, usually low level programs such as firmware and microcode. Characteristics
of PROM(1)In PROM, bipolar transistors are used.(2)PRO M is not reusable.(3) PROM is in expensive
(4)Writing to PROM is irreversible, which means its memory is permanent.5)The storage endurance
of PROM is high
Q3)Explain in detail the architecture of PLA.
PLA consists of two level AND-OR circuits on a single chip. The number of AND and OR gates and their
inputs are fixed for a given PLA chip.The AND gates provide the product terms, and the OR gates logically
sum these products and generate a SOP expression. Block Diagram A)Input Buffer (1) The buffer
circuits at the input limit the loading of the sources that drive the inputs.(2) It produces inverted as well
as non-inverted inputs at the output as shown in Fig.B)AND Matrix(1) An AND matrix is used to form
product terms. Fig OR matrix OR gate consists of parallel connected transistors with a common emitter
load.The outputs of the OR-matrix are obtained atS0 through S n-1 The output S0 = P0 + P1 +.....+P n-1
. fig Invert/Non-Invert MatrixThis is a programmable buffer that can be set for inverting or Non-
inverting operation corresponding to active-low or active-high outputs
Q4)Features of PLA PLA is a kind of programmable logic device.It is used to implement combinational
logic circuits. PLA has a set of programmable AND gate-planes. AND gates are linked to programmable
OR gate planes.The dimension of PLA :N*P*M .P<2 and the value of P is set by the PLA manufacture.
. Advantages Low development cost,Less space requirement, Less power requirement,Less design time
High switching speed, High design security
Q5)Explain CPLD

Definition-A complex programmable logic device (CPLD) is a logic device with completely
programmable AND/OR arrays and macrocells Features of CPLD1) AND/OR arrays are reprogrammable
and responsible for performing various logic functions.2)Macrocells can be regarded as functional
blocks responsible for performing sequential or combinatorial logic 3) The common features of CPLDS
and FPGAS are that they both have large number of gates and flexible provisions for logic.4)Common
features between CPLDS and PALS include non-volatile configuration memory. Applications of
CPLD1)CPLDS can be used as boot loaders for FPGA and other programmable systems.2) CPLDs are
often used as address decoders and custom state machines in digital systems.3)Due to their small size
and low power consumptions, CPLDS are ideal for use in portable and handheld digital devices.4)CPLDS
are also used in safety-critical control applications. Advantages Easy to design.CPLD gives simple way
to implement a design.CPLDs require low cost.Low development cost. Space requirement is less.Less
power requirement.Easy to troubleshoot.Less design time. High switching speed.
Q5)Explain FPGA
(i)Aerospace and Defense: Radiation-tolerant FPGAS along with intellectual property for image
processing, waveform generation, and partial reconfiguration for SDRS.(ii) ASIC prototyping: ASIC
prototyping with FDGAS enables fast and accurate. SoC. system modeling and verification of embedded
software.(iii) Broardcast and pro AV: Adapt to changing requirement faster and increasing
product life cycles with Broadcast Targeted Design platforms and solutions for high-end professional
broad-cast systems.(iv) onsumer Electronics: Cost effective solutions - enabling next generation, full-
featured consumer applications, such as converged handsets, digital flat panel displays, information
appliances, networking,(v)Data center low-latency : Designed for high-bandwidth, servers, networking,
and storage applications to bring higher value into cloud deployments.

Q6)What is logic family? 1)Digital Integrated circuits are produced using several different circuit
configurations and production technologies. Each such approach is called a specific logic family.2)A logic
family is a collection of different integrated circuit chips that have similar input, output, and internal
circuit characteristics, but they perform different logic gate functions such as AND, OR, NOT
Classification of logic family (logic families) 1.unipolar POMS, NMOS ,CMOS 2.bipolar a)non saturated
shottky TTL and Emitter Coupled logic b)saturated RTL, DTL, TTL
Q7)Write a short note on Characteristics of logic families. fig

some important parameters related to logic families.(1) Threshold voltage(2) Propagation delay
(speed of operation)(3)Power dissipation(4)Power delay product(5)Voltage and current parameters
(6)Fan in(7)Fan out(8)Noise margin(9)Operating temperature
Define propagation delay(Speed of operation)
Definition: Propagation delay is the time taken by the output to change its state after input changes.
It is denoted by Tp.2) Less the propagation delay, higher is the speed of operation.
Power dissipation and mention its standard value for TTL logic family.
Definition: It represents the power delivered to the gate from the power supply.2)Every gate will
require a supply voltage (Vcc) to operate the internal circuit of the gate. When the gate is powered, it
draws a current (Ic) from the supply. Refer Fig.The power dissipation of the gate is calculated from the
voltage and current as ( Pd =power dissipation =Vcc * Ic )
Fan-in ->Definition: It is defined as the maximum number of inputs that the logic gate is
designed to handle. fan In= Number of input pins fig
Fan out ->Definition: It is defined as the maximum number of logic gates that can be driven by a output
of a single logic gate without falling outside the specified output voltage limits.Fan out in LOW and HIGH
states are obtained as (fanoutL = fanout in LOW state= IOL/ IIL =16 mA/1.6mA =10) (fanoutL=fanout in
HIGH state=Loh/ IIH=400 mA/40mA=10) fanout=min(fanoutL,fanoutH)=10
Noise Margin->The maximum value of noise that can be tolerated in a system without creating an
error is called as noise margin. For logic 0 = NML=VIL (max) - VOL (max) = 0.8 - 0.4 = 0.4V For logic 1
= NMH=VOH (min) - VIH (min) = 2.4 - 2 = 0.4V NM = min(NML, NMH) = 0.4V
Q8)Difference between TTL and CMOS logic circuit
1) Stands for: It stands for transistor transistor logic.It stands for complementary metal oxide
semiconductor.2) Consists of : It uses bipolar junction transistors, It uses NMOS and PMOS transistors.
3) Power supply: Vcc=5V ± 10%, for4000 series 3 V<=Vdd<= 18 V For HC family V For HC family
2V<=Vdd<6V 4)Noise margin :Small typically 0.4 V , Large, typically 0.3 V 5) Fan out: Less typically 10,
Large, typically 40 6)Power dissipation: fixed 10mW, Depends on VDD and frequency PD(static)=2.5
nW for VDD=5V PD=1 mW/gate at f=1 MHZ VDD=10V 7) Propagation delay: small(10nS),large(70nS)
8) Figure of merit:100pJ,0.7pJ 9) Basic gate: NAND,(NAND NOR) 10) Packaging density: Less ,Very
high as the size of CMOS is very small. 11) Cost: Less expansive but not as economical as CMOS, More
expansive than TTL but are less costly at a system level 12)design: more complex design with BJT and
resistors ,similar design with NMOS and POMS transistor 13)Interconnction: Cannot drive CMOS
directly requires a Can directly drive TTL pull up resistor ,can directly derive TTL
Explain TTL open collector
Diagram then (1) This type of gate is obtained by removing the components, resistor R3 transistor Q3
and diode D from the totem pole stage shown in the dashed box (2) The collector of Q4 is left open,
therefore the name. open collector gate (3)Thus the resistor R pulls the voltage at Y to high level. hence
it is called as pull-up resistor. When Q4 is ON (saturated), the output terminal Y gets connected to
ground through low collector emitter resistance of Q4, resulting in low output voltage.

ADVANTAGE -> (1) Wired AND operation is possible with this type of gates. (2) Open collector outputs
allow the device to drive another type of device at different Vcc (high voltage loads), or
loads other than 5 V.(3) They can be used to drive high current loads (relays or
indicator lamps) as shown in fig
Disadvantages -> (1) The problem with open collector gate is the large time constant. We know that in
totem pole (Fig. 1.6.1(a)). when the output is high, the transistor Q3 is ON which behaves like a emitter
follower stage providing low output impedance. This results in small RC time constant.(2) But when Q3
is removed and R is connected externally, the external resistance R decides the time constant, which is
usually larger than totem pole TTL. So, naturally speed of open collector TTL is slower than the standard
TTL.(3) The speed of open collector TTL can be slightly increased by decreasing the value of R. But it
increases the current, resulting in more power dissipation. This is why this TTL is avoided when the
speed is the criteria

Wire logic AND get TTL

DIAGRAM then consider two normal TTL gates whose outputs are A and B. We want the AND operation
of these two, that is Y = A.B (2) But in case of open collector gates, if the outputs A and B are wired
together at point P, it acts like AND operation (3) Let A=0V logic 0 and B = 5 V logic 1. when they are not
connected output A remains at 0 V i.e. grounded through the output stage of gate 1 and
B remains at + 5V (4) When we connect A and B, the output B is forcefully connected to ground through
output A, resulting in voltage at common point P equal to OV, giving Y = 0 then next diagram
Tri-state Inverter TTL -> 1) The standard totem pole TTL circuit is a bistable circuit, it has two stable
states, namely HIGH state (logic 1) and LOW state (logic 0) (2) But tri-state TTL circuit, can operate in 3
states,(i) HIGH state(ii)LOW state(iii) High impedance state (3) In the standard TTL circuit, the states of
transistors Q3 and Q4 decides the output of the circuit For Y=1 =>Q3 ON ,Q4 OFF | Y=0 => Q3 OFF,Q4
ON So here, either Q3 is ON or Q4 is ON, both are not OFF at the same time. (4) But in tri-state TTL,
there is one state where both Q3 and Q4 are OFF. This state is called as high impedance state (High Z)
then Fig
Q)Draw and explain operation of two input CMOS inverter.
Explain with neat diagram working of CMOS inverter. OR Implement CMOS inverter.
(1) CMOS stands for complementary MOS, it uses both PMOS and NMOS transistors. (2) CMOS
inverter circuit uses both PMOS (Q1) and NMOS (Q2) transistors connected in series as shown in fig
(3) The input terminal of the inverter (A) is connected to both the gate terminals (G) ofQ1 and Q2.(4)
The output of the inverter (Y) is connected to both the drain (D) terminals of Q1andQ2.(5) The supply
voltage Vdd is connected to the source (S) terminal of PMOS (Q₁) transistor, while the source (S)
terminal of NMOS (Q2) is connected to the ground terminal(6) The input A can be a logic low (0) or a
logic high (1). For some input when one transistor is ON then the other will be OFF. Operation (1) Q1
(PMOS) → ON when input LOW | Q₂ (NMOS)→ON when input HIGH case (i)A=0 fig 1) when low input
is applied then Q1 is on and Q₂ is off. so Q1 behaves like the switch is closed and Q2 behaves like the
switch is open as shown in fig. (2) the supply voltage vdd is connected to the output (y)resulting in
high output (logic 1). A=0 Y=1 case (ii) A=1 fig (1) When high input is applied, then Q1 is OFF and Q2 will be
ON. The transistor Q1 behaves like the switch is open and Q2 Behave like the switch is closed as shown in Fig
(2)The ground is now connected with output (Y) resulting in LOW output (logic 0). A=1 Y=0 (3)the input
combinations and the corresponding out put are TRUTH TABLE Input A [0 1] | Q1[ON OFF] Q2[OFF ON] output
Y[1 0]

Draw and explain the working of 2-input CMOS NAND gate

fig(1)CMOS stands for complementary MOS, it uses both PMOS and NMOS transistors.(2) The two input CMOS
NAND gate It consists of two PMOS transistors (Q, and Q₂) and two NMOS transistors (Q3 and Q4). (3) Two
PMOS transistors (Q1 and Q2) are connected in parallel, while two NMOS transistors (Q3 and Q4) are
connected in series.(4)The common end of the parallel series connection is connected at the output (Y).
(5)Input A is applied to Q1 and Q3,while input B is applied to Q2 and Q4.Operation Q1,Q2 (PMOS)→ON when
input LOW | Q3,Q4 (NMOS)→ON when input HIGH Condition For high output When any of the transistors Q1
and Q2 or both are ON, then the output gets shorted to VDD resulting in high output. Condition for low output
When both transistors Q3 and Q4 are ON then only the output gets shorted to ground resulting in low output.
FigA CASE(i) A=0 B=0 ON transistors:Q1,Q2|OFF transistors:Q3,Q4 The output gets shorted to Vdd resulting in
Y=1 figB CASE (ii): A = 0, B = 1 ON transistors: Q1, Q4 |OFF transistors :Q2,Q3The output gets shorted to VDD
resulting in Y=1 figC CASE (iii):A=1 B=0 ON transistors:Q2,Q3|OFF transistors: Q1,Q4 The output gets shorted to
V DD resulting inY=1 figD CASE(iv): A=1,B= 1 ON transistors:Q3,Q4 |OFF transistors:Q1,Q2 The output gets
shorted to ground resulting in Y=0. TRUTH TABLE {Input[A (0,0, 1, 1) B(0 1 0 1)]} Q1[ON ON OFF OFF] Q2[ON
OFF ON OFF] Q3[OFF OFF ON ON] Q4[OFF ON OFF ON] output[1, 1, 1, 0]

Draw CMOS circuit for NOR gate. 2-input

fig(1)CMOS stands for complementary MOS, it uses both POMS and NMOS transistors.(2)The two input CMOS
NOR gate is as shown It consists of two PMOS transistors (Q1and Q2) and two NMOS transistors (Q3 and Q4)
(3)Two PMOS transistors (Q1and Q2) are connected in series, while two NMOS transistors Q3 and Q4 are
connected in parallel.(4)The common end of the parallel-series connection is connected at the output (Y).
(5)Input A is applied to Q1 and Q3 while input B is applied to Q2 and Q4 Operation Q1,Q2 (PMOS)→ ON when
input LOW | Q3,Q4 (NMOS)→ON when input HIGH Condition for high output(1)When both transistors Q1and
Q2are ON then only the output gets shorted to VDD resulting in high output Condition for low output(1)When
any of the transistors Q3 and Q4 or both are ON, then the output gets shorted to ground resulting in low
output.CASE(i) A= 0,B=0( fig.a) ON transistors:Q1,Q2 |OFF transistors:Q3,Q4 The output gets shorted to VDD
resulting in Y=1CASE(ii):A=0,B=1 (Fig.b)ON transistors:Q1,Q4|OFF transistors: Q2, Q3 The output gets shorted
to ground resulting in Y = 0CASE (iii): A = 1 B = 0 (Fig. c)ON transistors : Q2,Q3 |OFF transistor:Q1,Q4 The
output gets shorted to ground resulting inY=0case(iv)ON Q3,Q4 OFFQ1,Q2 output Y=0 Truth table var cha^
TTL characteristic detail

Supply Voltage They can operate with a single supply Vcc and ground.Typical values are 74 series =Vcc 4.75V to
5.25V 54 series=Vcc = 4.5 V to 5.5V Threshold Voltage TTL logic 0 represents 0 V and logic 1 represents 5 V.
Threshold voltage is calculated as the average of these two, Vth = 0+5/2=2.5VCurrent Specifications Currents
at input and output are different for HIGH and LOW states. (A)Output current sourcing and sinking In HIGH
output state,TTL output sources the current Fig(a).LOW state Typical values are Ioh=-400μA(out)|IoL=μA(in)(B)
Input current sourcing and sinking When logic 0 is applied at input, TTL input sources the current as shown in
Fig. 1.17.2(a). While for logic 1 at the input it sinks the current as shown in Fig(b).Typical values are IiL=-1.6 mA
(out)|IiH=40μA (in)

Draw and explain TTL to CMOS interface

1)the output of TTL is to be connected to the input of CMOS. (2) So we will see whether voltage parameters of
the TTL output are compatible with CMOS input.These parameters are shown below:The TTL circuit works with
Vcc= +5V, and CMOS works with Vdd=+3 V to + 18 V.Instead of using different supplies, let us use +5 V supply
for both. The voltage range shown below for CMOS input is for VOD +5 V(3) Fig. the low voltage range of TTL
output falls within the low voltage range of CMOS input. So low states of TTL and CMOS are compatible. This
means that logic 0 delivered by TTL, the CMOS can recognize it as logic 0, as condtion in Equationis satisfied.
(4)The problem is with high level of TTL output. The HIGH output voltage range for TTL is from 2.4 V to 5 V, but
for CMOS, the high input range is from 3.5 V to 5 V.(5) Thus if the TTL output is high and the voltage is 2.4 V
then the CMOS cannot recognize it as logic 1 input. This is because condition in Equation is not satisified. (6) So
we should make some arrangement so that the logic I delivered by TTL, the CMOS will recognize it.(7)This is
done by using a pullup resistor R from CMOS input to Vcc So whenever the TTL output is 2.4, the resistor pull it
up to 3.5 V. The circuit arrangement is as shown in Fig.a Vcc =5V 8)If we use different supplies,5V for TTL and
15 V for CMOS, the pull up resistor does not work.For this case we can use active pull up using a transistor as
shown in Fig. 1.23.3(b). One more arrangement using TTL buffer is Fig(c).(9) In the above discussion we
managed voltage compatibility. But what about currents? There is actually no need to worry about. Because
the input current values of CMOS are extremely low compared to the output currents of TTL. Thus TTL has no
problem in meeting the CMOS input current requirements.The TTL output currents are IoH=0.4 mA,IoL=16mA
The CMOS input currents are Iih=IiL=1μA condition given in Equations are satisfied. Thus no interfacing circuit is
required for currents.

Q)Applications of ASM chart? what is ASM?

1. ASM is used to represent diagrams of digital integrated circuits.2.The ASM diagram is like a state diagram but
it is more structured and easier to understand.3. ASM chart is a special type of flow-chart that is used to
describe the sequential operations of a digital circuit. 4.The ASM chart determines the sequence of events,
timing relationship between the states of sequential controller and the events that take place while going from
one state to another.5.They are used in the design of control unit of computer.6.They are also used in general
control networks in any digital systems.7. A flow chart serves as a useful aid in writing software programs,
algorithmic state machinery (ASM) charts help in the hardware design of digital systems.8. An ASM chart is a
special flow-chart and is developed specifically to define digital hardware algorithms.9.ASM charts provide a
conceptually simple and easy to visualise method of implementing algorithms used in hardware design.10.ASM
chart is a useful tool which leads directly to hardware realisation.