Sensors and Actuators A, 25-27 (1991) 741-751
Electronic Circuitry for a Smart Spinning-current Hall Plate with Low Offset
P. J. A. MUNTER
Derft University of Technology, Electronic Instrumentation
Abstract
The offset in silicon Hall plates is reduced
by multiple orthogonal switching of a single
symmetrical spinning-current Hall plate. The
offset virtually cancels out when the current
direction is made to spin with steps of n/8,
while the consecutively available Hall voltages
are averaged over time. The novel 16contact
spinning-current Hall plate shows less than
50 PV ( 100 pT) residual offset. A combination
of the spinning-current Hall plate and the
hybrid electronic circuitry obtains a 10 times
lower offset (at maximum 200 pT) when com-
pared to optimized commercially available
Hall plates without electronics.
1. Introduction
Over the past few decades, a great variety
of Hall plates made of different materials has
been realized [ 11. The general design proce-
dure was always to improve the sensor by
selecting a material with a high mobility,
which determines the magnetic field sensitiv-
ity, and then to adjust the geometry until the
characteristics of the sensor matched the de-
mands.
Silicon can also be used to make Hall
plates which show a relatively low sensitivity
and a high offset. The unknown offset in
silicon Hall plates is mainly caused by pack-
age stress, which cannot be compensated
for in the factory because the stress appears
to change with time and temperature.
Several offset-reduction methods have been
proposed, none of which solved the offset
problem completely [ 1,2]. The lowest offset
0924-4247/91/$3.50
747
Laboratory, P.O. Box 5031, 2600 GA Delfr (The Netherlands)
of about 2 mT is obtained by the incorpora-
tion of two or four orthogonally coupled
Hall plates which are nested closely together
PI.
However, silicon allows electronic cir-
cuitry to be merged on the same chip as
the sensor, resulting in a so-called smart sen-
sor. Now this smart sensor as a whole needs
to match the demands on sensitivity, offset,
etc.
In this paper first the spinning-current
offset-reduction method and some new re-
sults are presented and secondly the hybrid
electronic circuitry for implementing this
method is discussed. The experimental re-
sults on the offset of a 16-contact spinning-
current Hall plate itself and on the offset
when the hybrid electronic circuitry is added
are given.
2. The Spinning-current Offset-reduction
Method
A Hall plate is a thin resistive sheet of a
high-mobility material with two pairs of
diametrically opposed contacts. The bias cur-
rent which flows straight across the Hall
plate is deflected by a magnetic field and a
Hall voltage arises at the Hall contacts, see
Fig. 1:
VI-&(P) = S(q)Z,B + V,K(cp) (1)
with cp the direction of the current flow with
respect to the crystal orientation, S the sensi-
tivity, Z, the bias current, B the magnetic
induction and V,,(cp) the offset. The sensitiv-
ity is also q-dependent via the piezo-Hall
effect [3]. The sensitivity varies 2.5% at the
0 Elsevier Sequoia/Printed in The Netherlands
748
t ttAt
Fig. 1. Orthogonal switching of a Hall plate to itself.
At time I the current flows downwards, and at time
f + At the current flows perpendicularly to the initial
current flow direction. The Hall voltage is measured at
the contact pair which is perpendicularly oriented to the
current flow.
most by the piezo-Hall effect when the cur-
rent is made to spin [ 31 in the ( 110) plane of
silicon.
The offset in a Hall plate can be viewed as
an imbalance of a Wheatstone bridge. The
geometrical errors cancel out completely
when the bridge is switched orthogonally to
itself. The influence of stress on the offset can
be modelled using piezoresistances. The offset
becomes [ 41
V&(P) =
+++ +;))
(rc’(V
+;))x R
xcos(2(o-yl
Hall
with 11,and 71,the longitudinal and transverse
piezoresistive coefficients in the cp + n/4 cur-
rent direction, X the stress and 0 the stress
orientation. The piezoresistance coefficients
in (lOO)-oriented n-type silicon show a n/2
periodicity and the stress shows a n: periodic-
ity. The offset is the product of these two
periodic functions and consists of n and n/3
periodic terms.
Any periodic signal with the smallest pe-
riod T should be sampled at least every
T, = T/2, according to Shannon’s sampling
theorem. Thus in our case the sampling rate
becomes 7c/6. Using bipolar technology a
symmetrical 16-contact Hall plate was made,
which fulfils the sampling theorem, in which
the current is made to spin with steps of K/S
[5]. The current is forced straight across the
plate and the Hall voltage is measured at the
contact pair which is perpendicularly oriented
to the current flow. An integrator averages
the consecutively available Hall voltages. The
total Hall voltage is given by
= S’Z,B + V,,,(cp), Aso=2n/N (3)
with Vr,, the residual offset, S’ the average
sensitivity and N = 16 for a 16-contact Hall
plate. The integration takes place over mul-
tiple full rotations of the current.
3. The Electronic Implementation
The spinning-current offset-reduction
method requires electronic circuitry to be
added to the Hall plate. To examine the
concept, a hybrid circuit is built. First the
operating principle and next the various cir-
cuit sections are discussed.
z
The block scheme of the circuit is given in
Fig. 2. The current flow is made to spin by a
s
MOS multiplexer, while another MOS multi-
plexer selects the proper Hall-contact pair.
The consectively available Hall voltages are
amplified and an integrator averages out the
offset. The offset of the ‘chopper’ amplifier is
cancelled by reversing the bias current in the
Hall plate while the input terminals of the
amplifier remain connected to the same Hall
contacts and the output terminals are ex-
changed. The Hall voltage is treated as a
differential signal to obtain a maximum
power supply rejection ratio. Noise minimiza-
tion requires a bipolar amplifier input stage.
A dual-slope integrator yields a low offset,
requires no calibration, uses only a small
amount of space on the chip and is commer-
cially available [6 and refs. therein]. The
earth’s magnetic field of about 30-40 PT

(a)
(b)
Fig. 2. (a) Microphotograph of the 16-contact spin-
ning-current Hall plate. (b) Schematic diagram of the
implementation of the spinning-current offset-reduction
method.
results in a Hall voltage of about 100 PV
(SIS = 0.5 V/T). The earth’s magnetic field de-
termines the LSB of the integrator needed
and a 1Zbits plus 1 sign bit resolution covers
all voltages up to the maximum initial offset
of 50 mV. The integration time is set by the
quotient of the resolution and the reference
frequency, fO, and has a minimum value of
TCO”V = 4 ms (for 1Zbits and f0 = 1 MHz).
The resolution (and consequently the conver-
sion time) can be reduced by two to three bits
when the current is made to spin so that any
two consecutive Hall voltages have opposite
polarity, which results in a lower upper limit
of the dynamic range for the average input of
the integrator being almost zero. The current
is made to spin with a maximum sampling
frequency
749
Fig. 3. Schematic diagram of the electronic circuitry for
the smart spinning-current Hall plate. The polarity
reverser which follows the amplifier is part of the
‘chopper’.
with N the number of contacts used and fret
the rotation frequency of the current.
The spinning-current offset-reduction cir-
cuit is given in Fig. 3. The CM voltage at the
Hall contacts is cancelled by connecting one
Hall contact to the virtual ground and the
output of the opamp feedback loop to the
‘upper’ current contact [7]. When the direc-
tion of the current is made to spin, first all
switches open and next the selected switches
are closed. During the switching sequence,
the voltage across the Hall plate is memo-
rized by the internal capacitance of the plate.
The new Hall contacts are connected to the
Hall plate where the bias voltage across the
Hall plate is memorized. A large switching
peak results, which is proportional to any
resistive and capacitive asymmetries, where
the resistive asymmetries include the Hall
plate’s offset. The integrator integrates the
peaks and a voltage appears at the output.
The switching peaks are absent when the
direction of the current is reversed. The
switching peaks cancel each other out when a
proper switching sequence, that is cp from 0
to x to ?r/2 to 31112,is used [S]. A better way
to reduce these peaks is to short the input of
the integrator during transients when the cur-
rent is made to spin. Unfortunately, the sensi-
tivity is thus reduced proportional to the
duty-cycle (here 50%), which makes the offset
relatively twice as high. A high slew-rate am-
plifier is needed to minimize the influence of
the magnitude of the initial offset and the
magnetic field on the total offset and the
sensitivity respectively.
 15op piezoresistance coefficients and arises when
the orientation of the legs of the Wheatstone
75wv
bridge is modified in such a way that they
0
give a better representation of the actual cur-
rent flow at these sectors of the Hall plate. A
virtually non-periodic offset of about 25 PV
is obtained when the current is made to spin
0 2n
with steps of n/8. The residual offset is non-
Current Orienta& v at I, = 5mA zero due to contributory factors, like the
(a) Peltier effect, which rotate with the current
1 OmV 15opv
like the magnetic field sensitivity and, there-
fore, are not cancelled out. The exact nature
of the residual offset can be extracted from
the bias current dependency (see Fig. 4(b)).
5mV 75p
The offset contribution of the hybrid cir-
cuitry can be evaluated using various Hall
plate models. The total Hall voltage at the
0 0 output of the integrator, with the offsetless
6 2.5
resistive Wheatstone bridge as Hall plate
Current I, (mA) at 4 = 0

(b)
model, shows solely the offset of the electronic
circuitry (see Fig. 5(a)). The total Hall voltage
Fig. 4. The offset of the spinning-current Hall plate
itself. The offset, the orthogonal offset and the residual
remains unchanged when a resistive bridge
offset after averaging over eight samples (a) as a func-
tion of the direction of the current and (b) as a function
of the bias current.

4. Experimental Results

First, the need for a 16-contact spinning-

current Hall plate for the optimal offset 2 4
reduction is confirmed. Secondly, the contri- Current I, (mA)

bution to the total offset of the hybrid cir- (a)

cuitry using orthogonal switching is discussed.

Finally, the possibility of merging the elec-
tronic circuitry and the Hall plate on one chip
is evaluated. A high-resolution digital multi-
meter with a multi-slope integrator input is
used as the integrator in the experiments.
The offset of the Hall plate itself clearly
shows a x-periodic term, while the n/3 peri-
odic term is significantly smaller (see Fig. 0 2 4
Current I, (mA)
4(a)). The two periodic terms are a result of
(W
the periodicity of the piezoresistance co-
efficients and the stress. The ortogonal offset Fig. 5. (a) The total offset of the smart Hall plate as a
function of the bias current. The dashed line is for a
at cp, which is the average of the offset at cp
resistive Wheatstone bridge with offset comparable to
and at q + 7~12,is non-zero and periodic. The that of the real Hall plate, given by the solid lines. (b)
periodicity of the orthogonal offset is believed The total equivalent magnetic field as a function of the
to be a function of the periodicity of the bias current.
with offset is used because its orthogonal
offset is zero. The total offset becomes depen-
dent on bias current and rotation frequency
when a real Hall plate is used. The bias current
dependency is a result of the non-zero orthog-
onal offset voltage and of the finite slew-rate
of the amplifiers. The orthogonal offset re-
mains the same, independent of the rotation
frequency. At higher frequencies the width of
the pulses decreases, which increases the rela-
tive importance of the slew-rate errors. Conse-
quently, the rotation frequency dependence of
the offset is proportional to the magnitude of
the initial offset and, therefore, proportional
to the stress in the package.
The equivalent magnetic field is defined as
Beg = V,,/(SI,) and is used to compare the
offsets of different Hall plates (see Fig. 5(b)).
The maximum equivalent magnetic field is less
than 200 PT at I, = 4 mA, S’ = 110 V/A T and
fr,, = 4 kHz. This rotation frequency corre-
sponds to a 1 kHz rotation frequency when all
16 different current flow directions are used.
In that case the contribution of the residual
offset of the Hall plate itself is somewhat
smaller, (see Fig. 4(b)), while the number of
peaks over which it is integrated remains the
same. The equivalent offset is a factor of 10
smaller when compared to the offset of 2 mT
in commercially available Hall plates [2]. Fi-
nally, a magnetic field of 50 mT is applied to
test the dynamic range of the smart Hall plate
for magnetic fields. The total Hall voltage
appears to be virtually independent of the
rotation frequency up to 1 kHz at minimum.
Electronic circuitry can be merged on-chip
with a sensor when both can be made in the
same IC process and do not influence each
other thermally. The thermal influences of the
electronic circuit on the sensor are the temper-
ature rise and gradient. The effect of a temper-
ature rise is negligible, since the spinning of
the current also reduces the thermal offset
drift by about an order of magnitude. Exper-
iments have shown that a homogeneous 0.5 K
thermal gradient across the Hall plates in-
creases the offset by only 40 pV. Therefore, a
hybrid circuit is actually a reliable representa-
tion of an on-chip circuit.
5. Conclusions
The spinning-current offset-reduction
method reduces the offset significantly. The
Hall plate with hybrid circuit using single
orthogonal switching shows less than 200 PT
equivalent offset, which is a result of the
residual offset of the Hall plate itself and of
the finite slew-rate of the amplifiers. The inte-
gration time limits the bandwidth of the
smart Hall plate to about 1 kHz. This spin-
ning-current Hall plate with circuitry can be
integrated with BiCMOS technology, so that
we can expect that a single-chip smart spin-
ning-current Hall plate is feasible.
Acknowledgements
The author is grateful to several people:
the members of Professor Huijsing’s group
for their help on the electronics and the mem-
bers of the Delft Institute of MicroElectron-
its and Submicron Technology (DIMES) for
fabrication of the Hall plates. This work is
supported by the Delft University Fund.
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