1

UNIT-VI
D/A AND A/D CONVERTERS
Introduction
Most of the real-world physical quantities such as voltage, current, temperature,
pressure and time etc. are available in analog form. Even though an analog signal
represents a real physical parameter with accuracy, it is difficult to process, store
or transmit the analog signal without introducing considerable error because of
the superimposition of noise as in the case of amplitude modulation. Therefore,
for processing, transmission and storage purposes, it is often convenient to
express these variable in digital form. It gives better accuracy and reduces noise.
The operation of any digital communication system is based upon analog to digital
(A/D) and digital to analog (D/A) conversion.
Topics to be Covered: Basic DAC Technique & it’s types
1. Explain the block diagram of basic DAC or D/A technique
Basic DAC or D/A Technique:
The schematic of a DAC is shown in Fig. The input is an n-bit binary word D and is
combined with a reference voltage VR to give an analog output signal. The output
of a DAC can be either a voltage or current. For a voltage output DAC, the D/A
converter is mathematically described as

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Fig: Schematic of a DAC

2. What are the basic DAC techniques or different types of Digital to Analog
converters.
There are 3 different types of D/A Converters or DAC’s
• Binary Weighted Resistor DAC
• R-2R Ladder/Voltage Mode R-2R Ladder DAC
• Inverted R-2R Ladder /Current Mode R-2R Ladder DAC
Topics to be covered: Binary Weighted Resistor DAC
1. Explain about Binary weighted resistor DAC.
The binary weighted resistor DAC is shown in the below Fig. It consists of a set of
resistors, which are arranging from R/2 (R.2-1), R/4 (R.2-2) ------ R/2n (R.2-n) or 2R (21
.R), 4R (22.R), 8R (23.R)-------- 2nR (2n.R).
It has 4-electronic switches d1, d2, d3, d4------dn controlled by binary input
word. If the number of binary inputs is 3, the converter is called 3-bit converter.
For this converter there are 8(23) possible combinations of binary inputs for d1-d3,
an analog output have 8 possible corresponding values.
It has the negative reference voltage (-Vref or -VR). If the binary input to a
particular switch is 1, it connects the resistance to the reference voltage (-VR) and
if the input bit is 0, the switch connects the resistor to the ground.

Fig: Binary Weighted Resistor DAC

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The output voltage is given by

VO = −IO R f (2)
The output current IO for 2R(21 .R), 4R(22.R), 8R(23.R)-------- 2nR(2n.R) is given by
IO = I1 + I2 + − − − − − − + In
−VR −VR −VR
IO = d + d + − − − − + d
21 R 1 22 R 2 2n R n
VR VR VR
IO = − [ 1 d1 + 2 d2 + − − − − + n dn ]
2 R 2 R 2 R
VR
IO = − [d1 2−1 + d2 2−2 + − − − − + 2−n dn ] (3)
R

Substitute eq (3) in eq (2), we get

The output voltage is
VO = −IO R f
Rf
VO = VR [d1 2−1 + d2 2−2 + − − − − + 2−n dn ] (4)
R
(OR)
Rf d1 d2 d3 dn
Vo = VR ( + + + ----------------------- + 2n )
R 2 4 8
Comparing the equation (1) with (4), it can be seen that if Rf = R then K = 1 and VFS
= V R.
Another way
The output voltage is given by
VO = −IO R f (5)
The output current IO for R/2 (R.2-1), R/4 (R.2-2) ------ R/2n (R.2-n) is given by
IO = I1 + I2 + − − − − − − + In
−VR −VR −VR
IO = d1 21 + d2 2 2 + − − − − + d n 2n
R R R
VR VR VR
IO = − [ d1 21 + d2 2 2 + − − − − + dn 2 n ]
R R R
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VR
IO = − [d1 21 + d2 22 + − − − − + 2n dn ] (6)
R

Substitute eq (6) in eq (5), we get

The output voltage is
VO = −IO R f
Rf
VO = VR [d1 21 + d2 22 + − − − − + 2n dn ] (7)
R

Comparing the equation (1) with (7), it can be seen that if Rf = R then K = 1 and VFS
= V R.
Let the digital input be 3-bit binary word then the number of possible input
combinations equal to 8 (23).
Digital d1(MSB) d2 d3 (LSB) Analog Output Analog Output for
Input (V) VR = 5V
D0 0 0 0 0 0V
1
D1 0 0 1 VR 0.625V
8
2
D2 0 1 0 VR 1.25V
8
3
D3 0 1 1 VR 1.875V
8
4
D4 1 0 0 VR 2.5V
8
5
D5 1 0 1 VR 3.125V
8
6
D6 1 1 0 VR 3.75V
8
7
D7 1 1 1 VR 4.375V
8
Table: For 3-bit Input.
The analog output voltage is given by
Rf
VO = VR [d1 2−1 + d2 2−2 + − − − + 2−n dn ]
R
Rf D
Simply, we can write the output voltage, VO = V [ ]
R R 2n
For a 3-bit DAC, n = 3. Therefore 2n = 8
If D1 = 001 (1) i.e d1 = 0, d2 = 0, d3 = 1 then output voltage, (Assuming Rf = R)
1
VO = VR (0/21 + 0/22 +1/23) = VR
8

The smallest 3-bit number is D4 =100 (4) i.e d1 = 1, d2 = 0, d3 = 0 then

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1 4
VO = VR (1/21 + 0/22 +0/23) = VR= VR
2 8

If VR = 5V then Vo = (1/2) VR = (1/2) 5V = 2.5V

Therefore Resolution = 2.5V. i.e each bit of 3-bit DAC (000, 001……111) is
separated by 2.5V for VR = 5V. Similarly obtain the analog output Vo for other
digital inputs.

Fig: Transfer Characteristics of 3-Bit DAC

The output of the DAC is staircase. If it uses a negative reference voltage i.e -VR
then the analog output voltage is positive staircase as shown in the above Fig for
a 3-bit weighted resistor DAC. If it uses a positive reference voltage i.e +VR then
the analog output voltage is negative staircase. It may be noted that
(i) The op-amp in Fig. is connected in inverting mode, it can also be connected in
non-inverting mode.
(ii) The op-amp is simply working as a current to voltage converter.
The accuracy and stability of a DAC depends upon the accuracy of the
resistors and the tracking of each other with temperature.
Advantages:
• Weighted resistor DAC uses the simplest circuit.
• Analysis of weighted resistor DAC is very easy compared to R-2R DAC.
Disadvantages:
• The disadvantage of binary weighted type DAC is the wide range of resistor
values required. It may be observed that for better resolution the input
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binary word length has to be increased. Thus, as the number of bit increases,
the range of resistance value increases. For 8-bit DAC, the resistors required
are 21R, 22R………28R. The largest resistor is 256 times greater than the
smallest one for 8-bit DAC.
• For a 12-bit DAC, the largest resistance required is 5.12 MΩ if the smallest is
2.5kΩ. The fabrication of such a large resistance in IC is not practical.
• The difficulty of achieving and maintaining accurate ratios over such a wide
range especially in monolithic form restricts the use of weighted resistor DAC
to below 8-bits. Therefore accuracy is poor.
Topics to be covered: R-2R Ladder/Voltage Mode R-2R Ladder DAC.
1. Explain about R-2R Ladder/Voltage Mode R-2R Ladder DAC.
Wide range of resistors are required in binary weighted resistor type DAC. This can
be avoided by using R-2R ladder type DAC, where only two values of resistors i.e R
& 2R are required. It is well suited for integrated circuit realization. The typical
value of R ranges from 2.5 KΩ to 10 KΩ.
R-2R Ladder DAC for switch positions 100

Fig: (a) R-2R Ladder DAC for switch positions 100

Fig: (b) Equivalent circuit of Fig (a)

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(C)
Fig: (c) Equivalent circuit of Fig (b)
For simplicity, consider a 3-bit DAC as shown in Fig (a), where the switch positions
d1, d2, d3 corresponds to the binary word 100 (d1=1, d2=0, d3=0) . The circuit can
be simplified to the equivalent form of Fig (b) and finally to Fig (c).
Analysis:
Thevenizing the circuit to the left of switch d1, Thevenin’s equivalent resistance is
2
given by {[(2RII2R)+R] II 2R} + R = 2R and 2R II R = R
3
Then, voltage at node C is obtained by using potential divider rule is given by

• The output voltage for an inverting amplifier for the input 100 (4) i.e d1 = 1, d2
= 0, d3 = 0 is given by

1
If VR =5V then Vo = VR = 2.5V
2
• The output voltage for an inverting amplifier for the input 010 (2) i.e d1 = 0, d2
= 1, d3 = 0 is given by

• The output voltage for an inverting amplifier for the input 111 (7) i.e d1 = 1, d2
= 1, d3 = 1 is given by

The output voltage equation (assuming Rf = R) is given by

Vo = VR (d1 2-1+ d2 2-2+ d3 2-3+ d4 2-4+ ------------- + dn 2-n)
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d1 d2 d3 dn
Vo = VR ( + + + ----------------------- + 2n )
2 4 8

R-2R Ladder DAC for switch positions 001

The switch position corresponding to the binary word 001 (1) i.e d1=0, d2=0, d3=1
in 3 bit DAC is shown in Fig (a). The circuit can be simplified to the equivalent form
of Fig (b). The voltages at the nodes (A, B, C) formed by resistor branches are easily
calculated in a similar fashion as that of the above input 100 .

Fig: a) R-2R Ladder DAC for switch positions 001

Fig : b) Equvivalent circuit Fig (a)

• The output voltage for an inverting amplifier for the input 001 (1) i.e d1 = 0, d2
= 0, d3 = 1 is given by

For the digital input 001(1) i.e d1=0, d2=0, d3=1 then
1 VFS
Vo = VR (0 + 0 +1/8) = VR =
8 8
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1
If VR =5V then Vo = 5V = 0.625 V.
8
Similarly obtain the analog output Vo for other digital inputs.
Advantages:
• It requires only two resistors R & 2R.
Disadvantages:
• In weighted resistor type DAC and R-2R ladder type DAC, current flowing in
the resistors changes as the input data changes. More power dissipation
causes heating, which in turn, creates non-linearity in DAC. This is a serious
problem and can be avoided completely in Inverted R-2R ladder type DAC.
Topics to be covered: Inverted R-2R Ladder /Current Mode R-2R Ladder DAC
1. Explain Inverted R-2R Ladder /Current Mode R-2R Ladder DAC
A 3-bit Inverted R-2R ladder type DAC is shown in Fig (a), where the position of
MSB and LSB bits are interchanged. Here each input binary word connects the
corresponding switch either to ground or to the inverting input terminal of the op-
amp, which is also at virtual ground. Since both the terminals of switches di are at
ground potential, current flowing in the resistances is constant and independent of
switch position, i.e. independent of input binary word.
In Fig (a), when switch di is at logical '0' i.e., to the left, the current through
2R resistor flows to the ground and when the switch di is at logical '1' i.e., to the
right, the current through 2R sinks to the virtual ground. The circuit has the
important property that the currents divide equally at each of the nodes. This is
because the equivalent resistance to the right or to the left of any node is exactly
equal to 2R.

Fig: (a) Inverter R-2R ladder DAC

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Fig: (b) Inverter R-2R ladder DAC showing a division of current for input word
001 (d1 = 1, d2 = 0, d3 = 0)
The division of the current is shown in Fig (b). Consider a reference current of
2mA. Just to the right of node A, the equivalent resistor is 2R. Thus 2mA of
reference input current divides equally to value 1 mA at node A.
Similarly to the right of node B, the equivalent resistor is 2R. Thus 1 mA of
current further divides to value 0.5 mA at node B.
Similarly, current divides equally at node C to 0.25 mA. The equal division of
current in successive nodes remains the same in the ‘inverted R-2R ladder'
irrespective of the input binary word, Thus the currents remain constant in each
branch of the ladder. Since constant current implies constant voltage, the ladder
node voltages remain constant at VR/21, VR/22, VR/23, VR/23------ VR/2n
According to bit di, the corresponding switch gets connected either to
ground for di = 0 or to -VR for di = 1. The current flows from inverting input
terminal to -VR for di = 1 and from ground to - VR for di = 0. Regardless of the
binary input word, the current in the resistive branches of the inverted ladder
circuit remains always constant as explained in Fig (b).
The output voltage Vo is given by
VO = −IO R f
IO = I1 + I2 + − − − − − − + In
−VR
I1 =
2R

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−VR /2 −VR I1
I2 = = =
2R 4R 2
−VR /4 −VR I2
I3 = = =
2R 8R 2
−VR /8 −VR I3
I4 = = =
2R 16R 2
−VR /2𝑛− 1 In−1
In = =
2R 2
VO = −IO R f = − (I1 + I2 + − − − − − − + In ) R f
−VR −VR −VR −VR −VR
VO = −( d1 + d2 + d3 + d4 − − − − − − + 𝑛 dn ) R f
2R 4R 8R 16R 2 R
VR
VO = R f [d1 2−1 + d2 2−2 + d3 2−3 + d4 2−4 − − − − + dn 2−n ]
R
If Rf = R, Vo is given by
VO = VR [d1 2−1 + d2 2−2 + − − − − + dn 2−n ]
For the digital input 1001( 9) i.e d4=1, d3=0, d2 = 0, d1=1 then
VO = VR [1. 2−1 + 0. 2−2 + 0. 2−3 + 1.2−4 ]
OR
VO = VR [D/24 ] = VR [D/16]
9
VO = VR [1/2 + 0 + 0 + 1/16] = VR
16
9
If VR = 5V then Vo = 5V = 2.8125V
16
Advantage:
The most important advantage of the current mode or inverted ladder is that since
the ladder node voltages remain constant even with changing input binary words
(codes).

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Problems on DACs
1. What would be the output voltage produced by a D/A converter whose output
range is 0 to 10V with a binary number is
(i) 10 (for a 2-bit DAC).
(ii) 0110 (for a 4-bit DAC)
(iii) 10111100 (for a 8-bit DAC)

2. Calculate the values of the LSB, MSB and full scale output for an 8-bit DAC for
the 0 to 10V range.

3. The basic step of a 9-bit DAC is 10.3 mV. If 000000000 represents 0V, what
output is produced if the input is 101101111.
Solution: The output voltage for input 101101111 is
= 10.3mV (1.28+0.27+1.26+1.25+0.24+1.23+1.22+1.21+1.20) = 10.3mV (367) =3.78V
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Topics to be covered: Monolithic DAC or IC 1408 DAC

Monolithic DAC or IC 1408 DAC

Fig: 1408 DAC-Output Voltage in Unipolar Range

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Fig: 1408 DAC-Output Voltage in Bipolar Range

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Topics to be covered: Basic Block Diagram of ADC & its types

1. Explain the basic block diagram of ADC.
The block schematic of ADC shown in Fig, provides the function just opposite
to that of a DAC. It accepts an analog input voltage V a and produces an output
binary word d1d 2…….d n of functional value D, so that

D = d1 2 −1 + d 2 2 −2 + …… + d n 2 −n (1)
where d1 is the most significant bit and dn is the least significant bit.

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Fig: Schematic of ADC.

An ADC usually has two additional controls lines:
• The START input to tell the ADC when to start the conversion
• The EOC (End of Conversion) output to announce when the conversion is
complete.
Depending upon the type of application, ADCs are designed for microprocessor
interfacing or to directly drive LCD or LED displays.
2. What are the types of ADC’s.
ADCs are classified broadly into two groups according to their conversion
technique.
1. Direct type ADCs
2. Integrating type ADCs.

Direct type ADCs compare a given analog signal with the internally generated
equivalent signal. This group includes
1. Parallel comparator or flash type converter
2. Counter type converter
3. Tracking or servo/servo tracking converter
4. Successive Approximation type converter

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Integrating type ADCs perform conversion in an indirect manner by first changing

the analog input signal to a linear function of time or frequency and then to a
digital code. The two most widely used integrating type converters are:
1. Charge Balancing ADC
2. Dual slope or dual Ramp ADC
The most commonly used ADCs are successive approximation and the
integrator type.
The successive approximation ADCs are used in applications such as data
loggers and instrumentation where conversion speed is important.
The successive approximation and comparator type are faster but generally
less accurate than integrating type converters.
The flash (parallel comparator) type is expensive for high degree of accuracy.
The integrating type converter is used in applications such as digital meter, panel
meter and monitoring systems where the conversion accuracy is critical.
Topics to be covered: Parallel comparator or Flash Type of ADC
1. Explain about Parallel comparator or flash type A/D converter.
The Parallel comparator (FLASH) A/D converter:
This is the simplest possible A/D converter. It is at the same time, the
fastest and most expensive technique. Fig. (a) shows a 3-bit A/D converter. The
circuit consists of a resistive divider network, 8 op-amp comparators and a 8-line
to 3-line encoder (3-bit priority encoder).
The comparator and its truth table is shown in Fig. (b). A small amount of
hysteresis is built into the comparator to resolve any problems that might occur if
both inputs were of equal voltage as shown in the truth table.

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Fig. (a): Basic Circuit of a Flash or Parallel Comparator Type A/D Converter

In Fig (a), at each node of the resistive divider, a comparison voltage is available.
Since all the resistors are of equal value, the voltage levels available at the nodes
are equally divided between the reference voltage VR and the ground. The purpose
of the circuit is to compare the analog input voltage Va with each of the node
voltages. The truth table for the flash type A/D converter is shown in Fig. (c).

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Fig. (C) Truth Table for a Flash Type A/D Converter

Advantages:
1. The circuit has the advantage of high speed (fastest) as the conversion take
place simultaneously rather than sequentially.
2. Typical conversion time is 100 ns or less. Conversion time is limited only by the
speed of the comparator and of the priority encoder.
Disadvantages:
1. This type of ADC has the disadvantage that the number of comparators required
almost doubles for each added bit. A 2-bit ADC requires 4 comparators, 3-bit ADC
needs 8, whereas 4-bit requires 16 comparators. In general, the number of
comparators required are 2n, where n is the desired number of bits. Hence the
number of comparators approximately doubles for each added bit.
2. Also the larger the value of n, the more complex is the priority encoder.

Topics to be covered: Counter Type & Servo Tracking Type ADC.

1. Explain counter type ADC.
A 3-bit counting ADC is shown in Fig. (a). The counter is reset to zero count by the
reset pulse. Upon the release of RESET, the clock pulses are counted by the binary
counter. These pulses go through the AND gate which is enabled by the voltage
comparator high output. The number of pulses counted increase with time. The
binary word representing this count is used as the input of a D/A converter whose
output is a staircase of the type shown in Fig. (b).

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Fig. (a) Counter Type A/D Converter (b) D/A Output Stair Waveform
In Fig. (a), the analog output Vd of DAC is compared to the analog input Va by the
comparator. If Va > Vd, the output of the comparator becomes high and the AND
gate is enabled to allow the transmission of the clock pulses to the counter. When
Va < Vd, the output of the comparator becomes low and the AND gate is disabled.
This stops the counting at the time Va  Vd and the digital output of the counter
represents the analog input voltage Va.
For a new value of analog input Va, second reset pulse is applied to clear the
counter. Upon the end of the reset, the counting begins again as shown in Fig. (b).
The counter frequency must be low enough to give sufficient time for the
DAC to settle and for the comparator to respond.
If the maximum value of the analog voltage is represented by n-pulses and if
the clock period is T seconds, the minimum interval between samples is nT
seconds.
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Advantages:
1. It requires less hardware components.
2. Its operation is simple.
Disadvantages:
Low speed is the most serious drawback of this method. The conversion time can
be as long as (2n- 1) clock periods depending upon the magnitude of input
voltage Va. For instance, a 12-bit system with 1 MHz clock frequency, the counter
will take (212-1) s = 4.095 ms to convert a full scale input.
Problem on Counter Type DAC
1. Calculate the conversion time for a full scale input in case of a 12-bit counter
type analog to digital converter driven by 2MHZ clock?.
Sol: T = 1/(2ˣ106) = 0.5µs
The total time for a full scale input in case of a 12-bit counter type = (2n – 1) T
= (212 – 1) ˣ 0.5µs
= 2.0475ms
2. Explain about servo tracking A/D converter.
An improved version of counting ADC is the tracking or a servo converter shown in
Fig. (a). The circuit consists of an up/down counter with the comparator
controlling the direction of the count. The analog output of the DAC is Vd and is
compared with the analog input Va.

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Fig. (a) A tracking A/D converter (b) Waveforms.

If the input Va is greater than the DAC output signal, the output of the comparator
goes high and the counter is caused to count up.
The DAC output increases with each incoming clock pulse and when it
becomes more than Va, the counter reverses the direction and counts down (but
only by one count, LSB). This causes the control to count up and the count
increases by 1 LSB. The process goes on being repeated and the digital output
changes back and forth by  1 LSB around the correct value.
As long as the analog input changes slowly, the tracking A/D will be within
one LSB of the correct value. However, when the analog input changes rapidly, the
tracking A/D cannot keep up with the change and error occurs as shown in Fig. (b).
Advantages:
The tracking ADC has the advantage of being simple.
Disadvantages:
1. The time needed to stabilize as a new conversion value is directly proportional
to the rate at which the analog signal changes.
2. If the analog input changes rapidly, the tracking A/D cannot keep up with the
change and error occurs.
Topics to be covered: Successive approximation ADC
The successive approximation technique uses a very efficient code search
strategy to complete n-bit conversion in just n-clock periods. An eight bit
converter would require eight clock pulses to obtain a digital output.

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Fig: Functional Diagram of successive Approximation ADC

Fig. shows an eight bit converter. The circuit uses a successive approximation
register (SAR) to find the required value of each bit by trial and error. The circuit
operates as follows.
With the arrival of the START command, the SAR sets the MSB d1 = 1 with all
other bits to zero so that the trial code is 10000000. The output V d of the DAC is
now compared with analog input Va. If Va is greater than the DAC output Vd then
10000000 is less than the correct digital representation. The MSB is' left at '1' and
the next lower significant bit is made '1' and further tested.
However, if Va is less than the DAC output, then 10000000 is greater than
the correct digital representation. So reset- MSB to '0' and go on to the next lower
significant bit. This procedure is repeated for all subsequent bits, one at a time,
until all bit positions have been tested. Whenever the DAC output crosses V a, the
comparator changes state and this can be taken as the end of conversion (EOC)
command.

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Fig. (b): Successive Approximation Conversion Sequence for a Typical Analog Input

Fig. (c): The D/A Output Voltage is Approximately Close to Actual Input Voltage.
Fig (b) shows a typical conversion sequence and Fig. (c) shows the associated wave
forms. It can be seen that the D/A output voltage becomes successively closer to
the actual analog input voltage. It requires eight pulses to establish the accurate
output regardless of the value of the analog input. However, one additional clock
pulse is used to load the output register and reinitialize the circuit.
Advantages:
1. It’s conversion speed is high.
Disadvantages:
1. It is faster but less accurate than integrating type ADC.

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Comparison of conversion times for tracking and successive approximation ADCs

A comparison of the speed of an 8-bit tracking and an 8-bit successive
approximation ADC is shown in below Fig. the Given the same clock frequency, we
see that tracking circuit is faster only for small changes in the input. The successive
approximation technique is more versatile and superior than all other ADCs.

Topics to be covered: Integrating Type ADC’s

1) Explain about Charge Balancing ADC.
The principle of charge balancing ADC is to first convert the input signal to a
frequency using a voltage to frequency (V/F) converter. This frequency is then
measured by a counter and converted to an output code proportional to the
analog input.
Advantages:
The main advantage of these converters is that it is possible to transmit frequency
even in noisy environment or in isolated form.
Disadvantages:
The output of V/F converter depends upon an RC product whose value cannot be
easily maintained with temperature and time. The drawback of the charge
balancing ADC is eliminated by the dual slope conversion.
2) Explain dual slope or dual ramp ADC.
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Fig. (a) shows the functional diagram of the dual-slope or dual-ramp converter.
The analog part of the circuit consists of a high input impedance buffer AI,
precision integrator A2 and a voltage comparator.
The converter first integrates the analog input signal V a for a fixed duration
of 2n clock periods as shown in Fig. (b). Then it integrates an internal reference
voltage VR of opposite polarity until the integrator output is zero. The number N of
clock cycles required to return the integrator to zero is proportional to the value of
Va averaged over the integration period. Hence N represents the desired output
code.

Fig. (a) Functional Diagram of Dual slope ADC (b)Integrated output waveform
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Operation:
Before the START command arrives, the switch SW1 is connected to ground and
SW2 is closed. Any offset voltage present in the A1, A2, comparator loop after
integration, appears across the capacitor CAZ till the threshold of the comparator is
achieved. The capacitor CAZ thus provides automatic compensation for the input-
offset voltages of all the three amplifiers. Later, when SW 2 opens, CAZ acts as a
memory to hold the voltage required to keep the offset nulled.
At the arrival of the START command at t = t1, the control logic opens SW2
and connects SW1 to Va and enables the counter starting from zero.
The circuit uses an n-stage ripple counter and therefore the counter resets to
zero after counting 2n pulses. The analog voltage Va is integrated for a fixed
number 2n counts of clock pulses after which the counter resets to zero. If the
clock period is T, the integration takes place for a time T 1 = 2n X T and the Output is
a ramp going downwards as shown in Fig. (b).
The counter resets itself to zero at the end of the interval T I and the switch
SW1 is connected to the reference voltage (- VR). The output voltage V0 will now
have a positive slope. As long as Vo is negative, the output of the comparator is
positive and the control logic allows the clock pulse to be counted. However, when
Vo becomes just zero at time t = t3, the control logic issues an end of conversion
(EOC) command and no further clock pulses enter the counter. It can be shown
that the reading of the counter at t3 is proportional to the analog input voltage Va.
In Fig. (b)
2n counts
T1 = t2 − t 1 = (1)
clock rate
Digital count N
And t3 − t2 = (2)
clock rate
For an integrator,
v0 = (−1/ RC ) V (t) (3)
The voltage v0 will be equal to v1 at the instant t2 and can be written as
v1 = (−1/ RC )Va (t2 − t1)
The voltage v1 is also given by
v1 = (−1/ RC)(−VR )(t2 − t1)
Va (t2 − t1 ) = VR (t3 − t2)
Putting the values of (t2 − t1 ) = 2n and (t3 − t2 ) = N , we get
Va (2n )= (VR )N
Or, Va = (VR )(N / 2 n ) (4)
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The following observations can be made from the dual slope ADC as:
1. Since VR and n are constant, the analog voltage Va is proportional to the count
reading N and is independent of R, C and T.
2. The dual-slope ADC integrates the input signal for a fixed time, hence it provides
excellent noise rejection of ac signals whose periods are integral multiples of the
integration time T1 Thus ac noise superimposed on the input signal such as 50 Hz
power line pick-up will be averaged during the inputintegration time. So choose
clock period T, so that 2nT is an exact integral multiple of the line period (1/50)
second = 20 ms.
Advantages:
It provides excellent noise rejection of ac signals.
Disadvantage:
Dual-slope ADC is the long conversion time. For instance, if 2n.T = 1/50 is used to
reject line pick-up, the conversion time will be 20 ms.

Problems on Dual slope ADC

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2. Find the digital output, for 8-bit dual slope integrating ADC whose analog
input voltage =100mv, VR = 8V.
Sol: Va = (VR )(N / 2 n )
Digital count, N = 2n (Va/VR)
n = 8 & VR = 8V then N = 28 (100mV/8V) = 204.8 = 205.
Therefore (205)10 = (11001101)2
Digital output = (11001101)
3. Find the digital output, for 16-bit dual slope integrating ADC whose analog
input voltage = 4.129 V, VR = 8V.
Sol: Va = (VR )(N / 2 n )
Digital count, N = 2n (Va/VR)
n = 16 & VR = 8V then N = 216 (4.129V/8V) = 65536 (4.129V/8V) = 33825.
Therefore (338255)10 = (1000010000100001)2
Digital output = (1000010000100001)
Comparison between Flash, Successive Approximation & Dual Slope ADCs

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Topics to be covered: DAC/ADC Specifications

1. Explain the specifications of DAC/ADC.
Both D/A and A/D converters are available with wide range of specifications. The
various important specifications are
• Resolution
• Linearity
• Accuracy
• Monotonicity
• Settling time (Conversion Time)
• Stability
Resolution:
The resolution of a converter is the smallest change in voltage which may be
produced at the output (or input) of the converter. For example, an 8-bit D/A
converter has 28-1 = 255 equal intervals. Hence the smallest change in output
voltage is (1/255) of the full scale output range. In short, the resolution is the value
of the LSB.
Resolution is defined in two ways
• Resolution is the number of different analog output values that can be
provided by a DAC. For an n-bit DAC
Resolution = 2n
• Resolution is also defined as change in output voltage resulting from a
change of 1 LSB at the digital inputs. For an n-bit DAC it can be given as
V
Resolution (in volts) = n FS
2 −1
Where, VFS = VoFS = Full Scale Output Voltage
However, resolution is stated in a number of different ways. An 8-bit DAC is said to
have : 8 bit resolution
: a resolution of 0.392 percent of full-scale
: a resolution of 1 part in 255
Similarly, the resolution of an A/D converter is defined as the smallest change in
analog input for a one bit change at the output.
As an example, the input range of an 8-bit A/D converter is divided into 255
intervals. So the resolution for a 10 V input range is given by
VFS
Resolution (in volts) = = 39.22 mV (= 10 V/ 2 8-1 = 10 V/255 )
2n − 1
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Therefore, we can say that an input change of 1 LSB causes the output to
change by 39.22 mV
From the resolution, we can obtain the input-output equation for a DAC
Vo = Resolution * D
Where, D = Decimal value of the digital input
Vo = Output Voltage
Linearity:
The linearity of an A/D or D/A converter is an important measure of its accuracy
and tells us how close the converter output is to its ideal transfer characteristics.
In an ideal DAC, equal increment in the digital input should produce equal
increment in the analog output and the transfer curve should be linear.
However, in an actual DAC, output voltages do not fall on a straight line
because of gain and offset errors as shown by the solid line curve in Fig. The static
performance of a DAC is determined by fitting a straight line through the
measured output points. The linearity error measures the deviation of the actual
output from the fitted line and is given by £IΔ as shown in Fig.
The error is usually expressed as a fraction of LSB increment or percentage of
full-scale voltage. A good converter exhibits a linearity error of less than  1/2 LSB.

Fig: Linearity Error for 3-Bit DAC

Accuracy:
Absolute accuracy is the maximum deviation between the actual converter output
and the ideal converter output.

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Relative accuracy is the maximum deviation after gain and offset errors have
been removed. The accuracy of a converter is also specified in terms of LSB
increments or percentage of full scale voltage.
The accuracy of DAC should be at worst, ± 1/2 LSB. If the full scale output
voltage is 10.2V then for 8-bit DAC accuracy is given by
V 10.2 V 10.2 V
Accuracy = n FS = 8 = = 10mV
(2 – 1)2 (2 – 1)2 (255)2
Monotonicity:
A monotonic DAC is the one whose analog output increases for an increase in
digital input. The below Fig represents the transfer curve for a non-monotonic
DAC, since the output decreases when input code changes from 001 to 010. A
monotonic characteristic is essential in control applications, otherwise oscillations
can result. In successive approximation ADCs, a non-monotonic characteristic may
lead to missing codes.
If a DAC has to be monotonic, the error should be less than 1/2 LSB at each
output level. All the commercially available DACs are monotonic because the
linearity error never exceeds 1/2 LSB at each output level.

Fig : A Non – Monotonic 3-Bit DAC

Settling time (Conversion Time)
The most important dynamic parameter is the settling time. It represents the time
required for the output to 90 from Zero to full scale as the binary input is changed
from all 0s to all 1s to settle within a specified band 1/2 LSB of its final value.
It depends upon the switching time of the logic circuitry due to internal
parasitic capacitances and inductances. Settling time ranges from 100 ns to 10s
depending on word length and type of circuit used.

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Generally, DACs with a current output will have shorter settling times than
those with voltage outputs.
Stability:
The performance of converter changes with temperature, age and power supply
variations. So all the relevant parameters such as offset, gain, linearity error and
monotonicity must be specified over the full temperature and power supply
ranges.
2. What are the Specifications of AD 574 (12-Bit ADC)
Supply Voltage = + 5V
Supply Current = 800Ma (Max)
Power Dissipation = 390 mw (Typical ) & 725mW (Maximum)
Resolution = 12 bits
No of channels = 48-Single Ended or 24 differential
Polarity = Unipolar/Bipolar
Maximum Conversion Time = 35µsec
Accuracy = ± 0.01% of reading ± 1 LSB
Linearity Error = ± 1 LSB
Maximum Input Volage Range = ± 35V
Analog Input Range = -5V to 5V
Internal Reference Voltage = 9.98 V to 10.02 V
Operating Temperature = 0 – 70oC
Problems

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Raghu Institute of Technology Dept. of ECE LICA Unit - 6