EXPT.

NO: DESIGN AND IMPLEMENTATION OF SHIFT REGISTER USING

DATE: VERILOG

SERIAL IN SERIAL OUT

PIN DIAGRAM:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT

TRUTH TABLE:

DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

LOGIC DIAGRAM:
 SHIFT REGISTER- PROGRAMS IN VERILOG
PIPO module tb_pipo;
module pipo(pi,clk,po); reg clk;
input [3:0] pi; reg [3:0] pi;
input clk; wire [3:0] po;
output [3:0] po; pipo p1(pi,clk,po);
reg [3:0] po; always #100 clk=~clk;
always @ (posedge clk) initial
begin begin
po<=pi; clk=1'b1;
end pi=4'b1001;
endmodule #200 pi=4'b1100;
#200 pi=4'b0000;
#200 pi=4'b1010;
end
endmodule
SISO module tb_siso;
module siso(si,so,clk); reg si, clk;
input si,clk; wire so;
output so; siso s1(si,so,clk);
reg so; always #50 clk=~clk;
reg [3:0] temp; initial
always@(posedge clk) begin begin
so=temp[3]; clk=1'b1;
temp[0]=si; si=0;
temp[3:1]=temp[2:0]; #100 si=1;
end #100 si=0;
endmodule #100 si=1;
end

endmodule

SIPO module tb_sipo;

module sipo(si,clk,po); reg si,clk;
input si,clk; wire [3:0]po;
output [3:0] po; sipo s1(si,clk,po);
reg [3:0] po; initial clk=1'b1;
reg [3:0] temp; always #100 clk=~clk;
always @ (posedge clk) initial
begin begin
temp[3:1]<=temp[2:0];
temp[0]<=si; si=0;
po<=temp; #200 si=1;
end #200 si=0;
endmodule #200 si=1;
end
endmodule

PISO module tb_piso;

module piso(shift_load,clk,pi,so); reg shift_load,clk;
input shift_load, clk; reg [3:0] pi;
input [3:0] pi; wire so;
output so; piso p1(shift_load,clk,pi,so);
reg so; initial clk=1'b1;
reg [3:0]temp; always #10 clk=~clk;
always @ (posedge clk) initial begin
begin pi=4'b1101;
if(shift_load==0) shift_load = 1'b0;
temp[3:0]<=pi[3:0]; #20 shift_load = 1'b1;
else begin #120 pi=4'b1001; shift_load =
so<=temp[3]; 1'b0;
temp[3:1]<=temp[2:0]; #20 shift_load = 1'b1;
temp[0]<=0; end
end endmodule
end