IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24, NO.

10, OCTOBER 1977 517

Topological Generation and Analysis of Voltage

Multiplier Circuits
P. M.LIN, SENIORMEMBER,IEEE,AND LEON O.CHUA, FELLOW,IEEE

AbsWt-Voltage multipliers are used for transformerless conversion of

an UC input voltage t+(t) = E sin wl into a dc output voltage V,,, = PIE,
wbere n > 2. l%is paper investigates the topologicaI properties of voltage
multiplier circuits and presents a unified approach for generating new
voltage-multiplier circuit shwtures. In particular, an algoritbm is pre-
seuted for generating n-fold voltage multipliers with n capacitors and n
diodes. A theorem is presented for finding tbe dc capacitor voltages by
inspection when no load current is drawn. For the case with load, explicit
formulas for tbe ourpur dc wdtuge and tbe ourput resisrance are given.
Using the algorithm developed in tbis paper, three new voltage quadrupler
cimdts are generated and &own to have an output resistance only one-balf
of the conventional ladder quadrupler circuit.

I. INTRODUCTION

A VOLTAGE multiplier (abbreviated VM) is a capaci-

tor-diode’ network capable of converting an ac in-
put voltage u,(t)= E sin wt into a dc output voltage
(b)

voout= nE, where n > 2. Several commonly used voltage

multiplier circuit configurations (n = 2,3,4) are shown in
Fig. 1. Voltage multipliers have been used extensively in
the high-voltage power supply of television sets and in
many other applications requiring an ac-to-dc conversion
[lH2]. Fig. 2(a) shows a C-D ladder network with the
diodes forming the “rungs,” and with q(t) applied to one (cl
end of the ladder [3], [4, p. 8221. A dc capacitor voltage Fig. I. Voltage doubler, tripler, and quadrupler.
V, = nE may be obtained by connecting the output circuit
of Fig. 2(b) across an appropriate pair of nodes of the
ladder network. The output circuit consists of a diode in
series with a capacitor (called the output capacitor) and
will henceforth be referred to as the “output tank” to
emphasize the fact that in practice, the output capacitor lb)

has a much larger capacitance than the others in the Fig. 2. (a) Ladder C-D network. (b) Output tank.
ladder. Two tank connections for realizing even order and
odd order multipliers are shown in Fig. 3(a) and (b),
respectively [5].
As an aid for understanding the operating mechanisms
of voltage-multiplier circuits, let us first review some basic

Manuscript received November 17, 1976; revised April 15, 1977. This
work was supported in part by the Naval Electronic Systems Command
under Contract NBOO39-77-C-0022 and in part by the National Science
Foundation Grant ENG75-22282. L. 0. Chua’s research during the
1976-1977 academic year was supported by the Miller Institute as a
Miller Research Professor.
P. M. Lin is with the School of Electrical Engineering, Purdue Univer-
sity, Lafayette, IN 47907. The work of P. M. Lin was performed during
iris visit to the University of California, Berkeley, while on sabbatical
leave in 1976 From Purdue University.
L. 0. Chua is with the Department of Electrical Engineering and
Computer Sciences and the Electronics Research Laboratory, University
of Caliiornia, Berkeley, CA 94720.
‘We assume alF diodes are ided throughout this paper, i.e., the diode (b)
voltage oo and the diode current iD satisfy the constraints co $0, iD > 0, ,
and oDiD = 0. Fig. 3. N-Fold voltage multipliers derived from C-D ladder network.
 518 IEEE TRANSACTIONS ON CIRCUITS F SYSTEMS, VOL. CAS-24, NO. lo, OCTOBER 1977

v,=Eo+-‘&++;“tlvctt,
Fig. 4. Simple rectifier circuit.
6
+_ 2Osinwt

Fig. 5. Example showing that steady-state voltages depend on order

where diodes are connected.
properties of the simple rectifier circuit shown in Fig. 4. If
the capacitor is initially uncharged, i.e., v,(O) = 0, then the
stea&-state capacitor voltage is
obtained:
V,,=E
E,,+E, if E,+E>O
if E,+E<O’ (1) VC2= VC3=... = If,,,-,=2E
V,, = nE.
In other words, if the input voltage at any time forward
biases the diode, then the capacitor will be charged to the The preceding method is simple and gives correct re-
peak forward-biasing voltage and will retain that voltage sults (as will be proved ‘in Section ZZZ) for these circuits.
forever. Furthermore, if any passive load is now con- Unfortunately, its validity depends on whether Assumption
nected across the capacitor such that it draws only a finite Z is satisfied, or not. To demonstrate that not all capaci-
amount of charge from the capacitor for all t > 0, then it is tor-diodes networks satisfy the property stipulated in
intu@ively clear that the lost charge will eventually be Assumption 1, consider the circuit shown in Fig. 5, where
replenished by the source during the subsequent forward- both capacitors are assumed to be initially uncharged. If
biasing intervals of v,(t). Therefore t+(co) is again equal D, is reconnected at t =0 (D; not connected yet), then
to E, + E. Thus in steady state, the capacitor is equivalent vc,(t)=vc2(t)= 10 for t > :T, where T=2r/w. Now
to a dc voltage source of value E,, + E, provided that the suppose that D, is reconnected at t = T, then D, will be
passive load draws only a finite amount of charge. reverse biased at all times since vo2(t) =4 sin wt - 10 <0
Using the preceding equivalent voltage-source concept, for all t > T. Thus the steady-state solution is V,, = Vc2=
we can now find the steady-state solution of the VM 10. On the other hand, if we reconnect D, first at t =O,
circuits of Figs. 2 and 3 via an intuitive method, provided and subsequently reconnect D, at t = T, then a straight-
the following assumption is satisfied by these circuits. forward analysis gives the steady-state solution V,, = 8
and V,, = 12. This example shows that different orders of
Assumption I reconnecting the diodes .could lead to different steady-
The steady-state solution of the initially relaxed C- state solutions. Consequently the property stipulated in
D-1 E,, network is the same as the solution obtained by Assumption Z is certainly not true in general.
connecting the diodes to the initially relaxed C-l E,, sub- Even assuming that Assumption 1 is satisfied for the
network, one at a time, in any order, provided that a time being, the preceding Intuitive Method still has ,a
steady state is reached before each new diode is con- serious drawback: It is not applicable to all C-D-l E,,
nected.2 voltage-multiplier circuits, e.g., the one shown in Fig. 12.
As a specific example, consider the C-D-l E,, ladder One objective of this paper is therefore to present a
network of Fig. 3(a). The associated C-l E,, network is rigorous theory and a reasonably simple method for com-
obtained by disconnecting all diodes. Assuming that all puting the steady-state solution of voltage-multiplier
capacitors are initially uncharged at t = 0 when the diode circuits.
D, is reconnected, then it follows from (1) that Vc, = E. Another objective is to provide answers to the following
We now treat C, as if it is a voltage source Vc, = E. practical questions. Is the ladder network of Fig. 3 the
Looking to the left of nodes 1 and 2, we see an equivalent only general voltage-multiplier circuit configuration? If
voltage source v2,(t) = E + E sin wt. Hence if we reconnect not, what other general configurations are there? How
diode D, after C, has reached steady state, we would does one choose among different configurations? What is
obtain V,-2 =2E in accordance with (1). Continuing this the effect of the load on the dc output voltage? In Section
diode reconnection procedure, the following steady-state ZZ we present a topological procedure for constructing a
voltages for the circuits of Fig. 3(a) and (b) are easily variety of n-fold voltage-multiplier configurations using n
capacitors and n diodes. It will be clear that the conven-
tional ladder voltage-multiplier circuit is just a special
*For simplicity, we use the abbreviation “C-D-IL? network” to
denote any network containing capacitors, diodes, a;l’d exactly one case generated by our topological algorithm. In Section ZZZ
sinusoidal voltage source. Similarly, a C-l E,, network contains only we present a rigorous theory for determining the steady-
capacitors and exactly one voltage source. A network is said to be
initially relaxedif the initial voltages on the capacitors are equal to zero state capacitor voltages of the voltage multiplier circuits
prior to the application of the voltage source. generated in ‘Section II, unher no load condition. The
LIN AND CHUA: ANALYSIS OF VOLTAGE MULTIPLIER CIRCUITS 519

result of this section actually gives a justification for the

Intuitive Method described earlier. The effect of load
current on the dc output voltage is analyzed in Section IV.
The resulting analysis will enable one to choose the best
among several n-fold voltage-multiplier configurations,
when voltage regulation is the primary concern.

II. A TOPOLOGICAL METHODFORGENERATING

VOLTAGE-MULTIPLIER CIRCUITS
The problem at hand is to construct a network N made 6 x
up of ideal capacitors, ideal diodes, and one sinusoidal <I IL
voltage source (abbreviated C-D-l E,,) that will possibly +
7,V,-,‘E ,‘V_ CZ’E 7-V+o =Vc4 =2E
perform as a voltage multiplier. Since a general theory of --\,+
II
_
V c3=E
C-D-l E,, networks does not currently exist, we shall not
(b)
attempt to investigate the most general network configura-
tion in which the diodes and the capacitors can be con- ‘$2 =+E Dlu
\I
nected in an arbitrary fashion. Instead, we shall first I 1.

identify the features of the conventional ladder voltage

multiplier circuit which are fundamental to the operation
of the circuit and then develop a topological method for
generating other configurations possessing the same
fundamental features. The following two conditions on
the C-D-l E,, networks are two such features which we
will henceforth assume to hold for all networks to be
investigated in this paper.
. I) C-E Tree Hypothesis: The capacitors and the voltage Fig. 6. Networks with C-E and D-E trees.
source form a tree of the network.
2) D-E Tree Hypothesis: The diodes and the voltage
source form a tree of the network.
In Section ZZI we shall describe a rigorous and yet
simple method for finding the steady-state solution of any
C-D-l E,, network satisfying the C-E tree and the D-E
tree hypotheses. Although. our original motivation for
imposing these two hypotheses was to preserve partly the
conventional ladder voltage-multiplier circuit configura-
tion, several subsequent considerations have indicated
that these two hypotheses are in fact desirable for the Fig. 7. Enumeration of distinct 3C-1 E trees.
design of any practical voltage multipliers. For example, if
there is a loop consisting of the voltage source and some
capacitors, and hence violating the C-E tree hypothesis, Given n, we can construct all nC-nD-1 E networks satisfy-
then the capacitor voltages in the loop will no longer ing the C-E tree and D-E tree hypotheses. The conven-
remain constant even in steady state. If there are two tional voltage-multiplier circuits in Figs. 2 and 3 are rather
diodes connected in series, and hence violating the C-E special cases where the voltage source and (n-l) capacitors
tree hypothesis, then either one diode may be shorted, or form a path in the network. Upon eliminating the
both diodes may be removed without affecting the solu- (n-l)C-1 E path constraint, we immediately have a new
tion. If there are two diodes connected in parallel, and realm of nC-nD-1 E networks which can possibly perform
hence violating the D-E tree hypothesis, then either one as voltage multipliers. Fig. 6 shows three networks that
diode may be removed, or both diodes may be shorted satisfy hypotheses 1) and 2) but do not have (n-l)C-1 E
without affecting the solution. If there are two capacitors paths. The steady-state capacitor voltages are indicated in
connected in series (and hence violating the D-E tree the figure.
hypothesis), or in parallel (and hence violating the C-E We shall now examine the number of nC-1 E trees that
tree hypothesis), then the two capacitors can be replaced can be constructed, given the number n. As an illustra-
by an equivalent capacitor. tion, consider first the special case n =3. There are six
One immediate consequence of hypotheses 1) and 2) is distinct 3 C-l E trees as shown in Fig. 7. Label the nodes
that if the network N has n + 2 nodes, then of the voltage source E as nodes 0 and 1. If the E-branch
is removed from each of these graphs, the resulting graph
total number of capacitors = total number of diodes = n. separates into two subtrees Tc, and Tc,, with no and
 520 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24, NO. 10, OCTOBER 1977

n, C-branches, respectively, where no > 0, n, > 0, and n, + of components. With this practical consideration in mind,
n, = n. Now in the enumeration of all Tc, and T,, sub- we see that the diode D, in Fig. 6(c) is poorly located
trees, the nodes 0 and 1 are different from the rest because because its fundamental loop relative to the C-E tree
they serve as reference nodes and will henceforth be contains only capacitors (and D, of course). Since the ac
called the roots of T,, and Tc,, respectively. Given any n, voltage source is not included in the loop, we have a
and n, such that n= n,+ n,, our problem is to find all situation of charging some capacitors by other capacitors.
distinct combinations of rooted trees T,, containing n, We can not expect the highest dc voltage to be enhanced
branches, and all rooted trees T,, containing n, branches. by such a mechanism. Therefore, it is reasonable to con-
This problem can therefore be identified with the problem nect every diode only from one node of T,, to another
of enumerating “unlabeled rooted trees” for which well- node of T,,. In this way, every fundamental loop
known methods exist [6, p. 2461. In particular, if w, associated with the diodes relative to the C-E tree will
denotes the number of unlabeled rooted trees of k contain the voltage source. This procedure further implies
branches, then the value of wk corresponding to the first 9 that the fundamental cutset defined by the voltage source
values of k are listed below relative to the C-E tree will contain all the diodes [7].
Therefore, we have now justified the imposition of a third
k 1 234 5 6 7 8 9 hypothesis.
w, 1 2 4 9 20 48 115 286 719’ 3) D-E Cutset Hypothesis: The diodes and the voltage
source form a cutset of the network.
Applying this table to Fig. 7, we see that we have 1 rooted Next, let us review the action of the voltage multiplier
tree T,, of 1 branch, 2 rooted trees T,, of 2 branches, and of Fig. 3(a). When D, alone is connected to the C-E
4 rooted trees T,, of 3 branches. The value of w, for any k ladder, C, will be charged to Vc, = E. At this time, the
can be calculated by the use of a counting series [6, p. 2471 voltage drop from node 2 to node 1 is
which we will not elaborate here. The above list should
suffice for our present discussions. u*,(t)= E+ E sin wt
To get the total number of K-1 E trees we should:
1) consider all possible ways of partitioning n into which has positive peak of 2E. By connecting D, from
node 2 to node 3, we utilize the 2E peak voltage to charge
n=,n,+n,;
2) for each (n,,n,) pair, enumerate the unlabeled rooted C, and obtain Vc2 = 2E. At this point in time, if we
trees T,, and T,, ; connect another diode from node 2 to some other capaci-
3) consider all possible combinations of T,, and T,, tor, the voltage available for charging the capacitor is at -
most 2E. Hence, nothing is to be gained by connecting
which, together with E, form a C-E tree, and take care
to avoid duplications.
It can be shown that the result is
t,, L number of distinct K-1 E trees

=
w,+w,w,-,+“*+W(n-I)/2W(n+1)/2, for odd n
wn + WIWn-, + . . . + W((n/2)- I)W((n/2)+ I)+tw(n,*)bqn,2)+
l), for even n. (2)
The first seven values of t, are listed below
nl 23 4 5 6 7
4 1 3 6 16 37 96 237.

Observe that for the example in Fig. 7, we have n = 3 and more diodes to node 2. Thus in order to make the best use
hence we expect to have 6 distinct 3 C- 1E trees. Once a of every diode, it is advisable not to have more than two
particular C-E tree configuration has been selected, there diodes connected to every node. This, together with the
are still many ways to connect the n diodes to form a D-E D-E cutset hypothesis, suggests that a) the number of the
tree. The combinatorial problem becomes extremely com- capacitors in the two subtrees T,, and T,, differ by no
plicated. Fortunately some practical considerations de- more than 1. b) The diodes are contained in a path. We
scribed below will further restrict the class of C-E trees have therefore justified the imposition of still another
and D-E trees for our purpose. topological constraint.3
Consider the three circuits shown in Fig. 6, each of 4) Aligned D-Path Hypothesis: The diodes, possibly with
which uses 4 capacitors and 4 diodes. Fig. 6(a) is a voltage the voltage source, form a path and are forward biased in
quadrupler whereas the other two circuits can at. most the same direction in the path.
function as voltage doublers. Naturally, we are only inter-
ested in voltage-multiplier circuits which produce the ‘Hypotheses I) through 4) imply that at most two diodes are con-
highest dc output voltage possible with the given number nected to each node.
LIN AND CIiUA: ANALhIS OF VOLTAGE MULTTPLIER CIRCUITS
C - subtree
Fig. 8. General voltage multiplier configuration.
A network satisfying hypotheses 1)4) can be depicted
as shown in Fig. 8. We wish to emphasize that all four
hypotheses have been imposed through practical consider-
ations rather than theoretical development. The C-E tree
and D-E tree hypotheses are introduced so that the funda-
mental features of the conventional ladder voltage multi-
plier are preserved, and such that the steady-state solution
can be found by simple and rigorous method (Section
Ill). The D-E cutset and the aligned D-path hypotheses
are introduced in order that an n-fold voltage multiplier
with only n capacitors and n diodes may be developed.
The D-E cutset and D-path hypotheses can also be justi-
fied mathematically once the C-E tree and D-E tree
hypotheses have been imposed. This will be done in
Section III after a general steady-state analysis method is
developed. Observe that the conventional ladder circuits
of Figs. 2 and 3 satisfy all four hypotheses. In contrast,
the circuits shown in Fig. 6(b) and (c), which fail to
function as a voltage quadruplers violate the D-E path
hypothesis.
Taking into consideration the four hypotheses stated
above, we shall now describe an algorithm for producing
an n-fold voltage multiplier with n capacitors and n di-
odes. For the purpose of our subsequent analysis of the
circuit (Section 111) the algorithm also includes a scheme
for labeling the nodes, the capacitors, and the diodes.
Algorithm VM (Voltage Multipliers)
Step 1-C-E Tree Construction
Construct two rooted trees Tc, and Tc, with [(n/2)1
and [(n/2)1 capacitors, respectively.4 Connect the volt-
age source across the two roots of Tc, and T,,.
Step 2-Node Labeling
Case I: n is even. For Tc,, select any capacitor as
4We use the symbol lx] (floor of x) to denote the greatest integer equal
to or less than x and the symbol 1x1 (ceiling of x) to denote the least
integer equal to or greater than x.
521
the output capacitor and label its nodes with 1 and
n + 1. Label the remaining nodes of T,, with odd
integers (3,5, * * * , n - 1). For TcO, label the root with 0.
and the remaining nodes with even integers (2,
4;. . ,n).
Case 2: n is odd. For Tc,, select any capacitor as the
output capacitor and label its nodes with 1 and n + 2.
Label the remaining nodes of Tc, with odd integers
(3,5;. - ,n). For TcO, label the nodes with even integers
(2,4; - . , n + l), taking care that roots of Tc, and Tc,
are labeled with consecutive integers.
Step S-Diode Connection and Labeling
Case 1: n is even. Connect a string of n diodes to
node pairs (1,2), (2,3),. . . , (n, n + l), with each diode
forward biased from node j to node k, j < k. Label the
diodes consecutively as D,, D,; . . ,D,,.
Case 2: n is odd. Connect n diodes to the node pairs
(1,2),(2,3),. . . , (n, n + l), (n + 1,n + 2) disregarding the
pair associated with the nodes of the voltage source,
with each diode biased from node j to node k, j< k.
Label the diodes consecutively as D,, D,; . . , D,,.
Step 4-Capacitor Labeling
Label the output capacitor as C,, which is between
the node pair (1,n + 1) for the case n is even, or
between the node pair (1,n +2) for the case n is odd.
Label the remaining capacitors as C,, C,, . . . , C,- , in
any order.
Observe that the fundamental loop defined by C,, with
respect to the C-E tree contains n diodes. It will be
rigorously shown in Section 111 that Vc, = nE if uj = E sin
wt.
As examples, the conventional voltage-multiplier
circuits of Fig. 3 and the new quadrupler circuit of Fig.
6(a) have been generated and labeled according to the
algorithm. Observe that Algorithm VM has been presented
as one possible way of constructing voltage-multiplier
circuits. There may exist other voltage-multiplier circuits
that-cannot be generated by Algorithm VM. However, we
conjecture that ah nC-nD-1 Eat n-fold voltage multipliers
can be generated by Algorithm VM, provided that the
positions of any two series-connected elements may be
interchanged, if necessary. In the conjecture, it is under-
stood that the output voltage V,=nE must appear across
a capacitor. Consider n =4 for example. Algorithm VM
generates 9 distinct configurations which are listed in Fig.
9. For this simple case, one can exhaust all possible
connections of 4C-4D-1 E elements and show that there
are only 9 distinct voltage quadruplers and that all of
them are generated by Algorithm VM. Observe that in
counting the number of distinct VM circuits, if one circuit
is obtained from the other by reversing the connection of
every diode, then the two circuits are considered to be
identical.
522 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24, NO. 10, OCXOBER 1977

0 and
6’ At-J
v,<O, i,>O, vziD=O.

‘b b3
k-5
(a)
4+5
(b)
Equations (4H7) must be satisfied for all t, although we
are looking only at t-co. Assume that the steady-state
capacitor voltages are constant, i.e., vc(oo)= V,. We shall
outline a procedure for finding V,. From (6), we have
i&co) =O. Since the D-E elements also form a tree TOE,
we can express iE and iD in terms of the link (for TDE)
currents ic. Then, ic =0 implies iE =0 and iD = 0. It follows
that all currents are zero in steady state, a result that
obviously satisfies KCL.
Ld)
Letting v, = Vc, vE = E sin wt (E > 0), we have from (4)
and (7)
Ot-&l v,(t)=-BEEsin&-BB,V,<O, for all 1.
(8)

E3 ‘i”s
It is easy to see that the inequality
and only if,
(8) holds for all t if,

(g) (h) UE-B,V,<O

or

m (9)
(j)
Fig. 9. Generation of voltage quadruplers by Algorithm VM. where U is an n-vector with l’s and O’s as its elements
such that
III. STEADY-STATE ANALYSIS-WITHOUT LOAD if the jth element of BE is either 1 or - 1
uj = 1,
Consider an nC-nD-1 E,, network N which satisfies the i 0, otherwise
C-E tree and D-E tree hypotheses. To facilitate the for-
mulation of the equilibrium equations for N, we construct We have succeeded in obtaining an inequality devoid of
G,, the directed graph associated with N. In Cd, let each the time variable t. We will show that Inequality (9) is the
diode branch direction be the same as the forward current crux to the steady-state analysis of N.
direction. Branch directions for the capacitors and the .The matrix B, is a square matrix of order n. Since the
voltage source may be arbitrarily assigned. Then the capacitors form a cotree for the D-E tree, B, is nonsingu-
fundamental loop matrix with respect to the C-E tree may lar [8, p. 931. At this point, it is rather tempting to ignore
be partitioned as follows (see [7] for notation): the “ > ” sign in Inequality (9) and to find V, by solving
B, V, = UE and accepting the result as the steady-state
E C,;..,C,, D,;..,D,, solution. Unfortunately, such a procedure has no theoreti-
B= [ BE ; B, ; 1, 1. cal foundation. It may or may not give the correct
(3)
answers, as the following two simple examples will dem-
C-E tree Dxee onstrate.
The current and voltage vectors are denoted by iE, ic, iD,
VE, v,, and vD, respectively. Throughout the remaining Example I
sections, we use small letters for functions of time, and Consider the voltage doubler shown in Fig. 1. We have
capital letters for constants. The network is governed by
three laws which are expressed by matrix equations as
follows.
B=[B, B, ln]= y; :, y .
I 1
Kirchhoff Voltage Law (KVL): Then U=[ 1 llT, and ec 2 B;‘UE=[E,2ElT which
B,I$E + BcVc + V, ~0.
is indeed the correct solution for Vc.
(4)
Kirchhoff Current Law (KCL) [ 7, p. 1453: Example 2
Consider the circuit shown in Fig. 10. We have
(5) ’ 1 0 0’ 1 0 0
B=[B, B, &I= -1 I-I 1 o’ o 1 o
Branch u-i relationships: 5 -1 IO 1 II0 0 1
dvc
ic=C- (6)
dt Then U=[l 1 l]‘, tic A B,-‘UE=[E,2E, - EIT,
which is obviodsly not a solution, as V,, can never be
51n the paper, cz> b means n, > b, for all i. negative in Fig. 10.
LIN AND CHUA: ANALYSIS OF VOLTAGE MULTIPLIER CIRCUITS
c2
Fig. 10. Example showing that B, V, = UE gives incorrect solution.
In view of these examples, it is clear that we should use
Inequality (9) as the basis for the steady-state analysis.
Observe that Inequality (9) is or+ a necessary, but not a
sufficient condition for V, to be the steady-state solution of
N. A general inequality of the form AX > K may have no
solution, a unique solution, or infinitely many solutions.
For the case of infinitely many mathematical solutions,
further information must be used to determine which can
be accepted as the solution to a physical problem. To see
the significance of the above observation, consider the
voltage doubler circuit of Fig. 1 again. The equation
corresponding to (9) is given by
One obvious solution is V, = [E,2E]r. But another solu-
tion is Vc = [4E, 6E]r, among infinitely many others. Con-
sider now the actual operation of the circuit. Vc, =4E,
V,, =6E is possible only if we charge C, and C, up to 4E
and 6E, respectively, before the ac’source is applied. If the
circuit starts with uncharged capacitors, then a transient
analysis will reveal that the voltages finally approach
uc,(cc)= V,, = E, and uc2(co)= Vo=2E. Therefore, we
will reject [4E, 6ElT, but accept [E, 2EJ* as the steady-
state solution of V,.
Except for some extremely simple circuits, finding the
steady-state solutions of C-D-l E,, networks through tran-
sient analysis is not a practical approach. Therefore, we
should try to find some features that will distinguish the
steady-state solution (for initially relaxed networks) from
all other feasible solutions of (9). Fortunately this is
possible with the aid of some physical reasoning. Consider
again the doubler circuit of Fig. 1. Suppose that we have
capacitors initially charged to U,-,(O) =4E, I&O) = 6E.
Then Vc=[4E,6ElT is a solution to Inequality (9). But
now imagine that due to some temporary leakage the
capacitor voltages drop to [3.9E,5.9E]. These reduced
voltages also satisfy Inequality (9). Since the ac voltage
source uj = E sin wt does not have the capability to restore
the capacitor voltages to their previous values [4E,6E],
we shall say that the solution voltages [4E,6E] are not
maintainable. Next, consider the solution Vc = [ E, 2E]*
which, by transient analysis, has been found to be the
steady-state solution if ‘the network is initially relaxed.
Imagine again that due to some temporary leakage, the
capacitor voltages drop to. V, =[0.9E, 1.9EJr. It can im-
mediately be shown that these lower capacitor voltages
cannot satisfy Inequality (9). The consequence of violating
Inequality (9) is that the diodes begin to conduct (Zo >O),
523
Fig. 11. Examples and geometrical interpretations for illusirating con-
cept of irreducible solutions of AX > K.
and charges will be restored to the capacitors until VC=
[E, 2E]* is again reached. Consequently, in this case we
shall say that the voltages [E,2E] are maintainable.
Thus one feature that distinguishes the steady-state
solution of an initially relaxed network from the other
feasible solutions of Inequality (9) is their “maintainabil-
ity.” The mathematical counterpart of this observation
will now be defined precisely.
Definition: Let X= X* be a solution of AX > K, where
A and K are n x n and n x 1 real matrices, respectively. X*
is called a. reducible solution if there exists another solu-
tion X= X# X* such that for i = 1,2,. . . , n, the following
is true:
x* > ii > 0, if xi*>0
XT < ii < 0, if xi*<0
,q = 0, if xi* = 0.
Otherwise, the solution is said to be irreducible.
For the two-dimensional case, this definition can be
illustrated geometrically. In Fig. 11, the feasible solutions
of AX= K are indicated by the hatched areas. For Fig.
11(a), X7 = [ 1,2]r is the only irreducible solution, and X*
is also the solution of AX = K. In Fig. 1 l(b),
X=A-‘K=[l -11 ’ is a solution of AX > K, but it is
reducible. The only irreducible solution in Fig. 1l(b) is
X= [ 1 0] * which is not a solution of AX=.K. To show
that an irreducible solution need not be unique, observe
that all points along the solid bold line segment in Fig.
1l(c) are irreducible solutions. A moment’s reflection will
reveal that for the Inequality (9) a reducible solution
corresponds to a nonmaintainable set of capacitor voltages,
while an irreducible solution corresponds to a maintainable
set of capacitor voltages. Clearly, the correct steady-state
solution. must be an irreducible solution of Inequality (9).
For the general case of AX > K, finding the irreducible
solution, or solutions, is a complicated problem. However,
there are some special cases that can be solved quite
 524 IEEE TRANSACXIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24, NO. 10, OCTOBER 1977

Theorem I
Let N be an nC-nD-1 E,, network which satisfies the
‘ollowing topological constraints:
a) the capacitors and the voltage source form a tree;
b) the diodes and the voltage source form a tree;
c) the diodes and the voltage source form a cutset;
d) the diodes, possibly with the voltage source, form
a path and are forward biased in the same direction
Fig. 12. Voltage tripler defying intuitive method of solution.
in the path.
If u,(t)= E sin at, E >0 and the capacitors are initially
.
easily. The following lemma is of great usefulness in the uncharged, then in steady state the capacrtor voltages
present study. are constant, and are given by
Lemma I Vq=+kjE

Let A be an n X n nonsingufar matrix, and K an n-vector
where K > 0. If for each row of A -I, all nonzero elements
have the same sign, then the inequality AX > K has one,
and on& one, irreducible solution given by X= A _ ‘K:
Proof: See [9].
We shall now illustrate the use of Inequality (9) and
Lemma I with an example.
where kj denotes the number of diodes contained in the
Fundamental loop defined by the capacitor Ci with
respect to the diodes-voltage-source tree, and where the
positive sign holds when the reference direction of Vci
is aligned with the diode’s forward directions, and is
rlegatiue otherwise.

Example 3 Proof: Let B and b be the fundamental loop matrices

with respect to the C-E tree and the D-E tree, respec-
Find the steady-state capacitor voltages for the circuit tively. Let Q be the fundamental cutset matrix with re-
shown in Fig. 12. spect to the C-E tree. These three matrices may be parti-
Solution: For (3), we have tioned as follows (assuming, of course, columns are
ordered correspondingly in all matrices):
E’C, C, c3 4 4 4
C,.e-C,, E 0,.-0D,,

B=[B,B,l,]=
-1;
1:
0
1; 01
The matrix B, and vector U associated with the Inequal-
1
00
0
1
0. 1 B= [ \ Bf
C-E tree
,: BE : ‘n
D-cotree
] (10)

ity (9) can now be identified as follows:

(11)
lb=[ -y -i -j], u=[ i]. C-E tree D-cotree

The inverse of B, is
g=[ 1, I &! 6D 1. (12)
--
C-cotree D-E tree
From BQT=O [8, p. 971, we obtain
B,+Q&=O (13)
Since the nonzero elements in each row of B; ’ have the
same sign, it follows from Lemma I that the unique and
irreducible solution is given by B,+Q,T=O. (14)
V,= B,-‘z/E= [ -2E,2E,3E] From iQT=O, we obtain

and this solution is the steady-state so’ution of this circuit. l,+bDQ,T=O. (15)
We see that the circuit is a voltage tnpler. Observe that it Substituting QCT from (13) into (15), we obtain
is not possible to find the steady-state voltages of this
circuit by the intuitive reasoning described in Section I. 1, - f&B,=O. (16)
We shall now present a theorem which will once again Since B, is nonsingular [8, p. 931, (16) yields
make it possible for us to obtain the steady-state solution
by inspection. The theorem is a major result of this paper, pq. (17)
and therefore will be stated clearly in words.
LIN AND CHUA: ANALYSIS OF VOLTAGE MULT’IPLIER CIRCUITS 525

Now consider any jth row of iD, which corresponds to

the fundamental loop defined by Ci with respect to the
D-E tree. Due to the Aligned Diode_Path Hypothesis, the
nonzero elements in the jth row of BD and hence the jth
row of B; ‘, must all be equal to + 1 or - 1. Since B; ’
satisfies the conditions of Lemma 1, it follows that In-
equality (9) has a unique irreducible solution given by
(0)
Fig. 13. Voltage multiplier with load connected.
(b)

V, = BF’ZJE. Hence the steady-state voltage is given by

V,=B,-‘UE=&JE. and QED be nonzero [see (9) and (14)]. From (1 1), a QEn
(18)
with all nonzero elements is equivalent to the requirement
Let us next observe that the D-E cutset constraint c) that all diodes and the voltage source form a cutset, a
implies each element of QE,, in (11) is equal to either + 1 condition introduced earlier in Section II through intuitive
or - 1. It follows from (14) that every element of BE is reasoning, and which serves as a hypothesis for Theorem
either + 1 or - 1. According to the definition of U in 1.
Inequality (9) we see that all elements of (I are equal to 1. 3) It follows from (19) that the maximum capacitor
Therefore, the steady-state solution (18) may be rewritten voltage magnitude 1V,I = nE can be attained only with a
as row of &, having all elements nonzero and of the same.
Vc=liDE (19) sign. This immediately leads to the “aligned-diode path”
constraint introduced in Section II, and which serves also
where E g [E, E; . . ,&IT.
as a hypothesis for Theorem 1.
Since for any jth row of iD, the nonzero elements are 4) If all diodes have a cut-in voltage V,>O (i.e., the
all 1, or all - 1, it is clear from (19) that diode is characterized by i. > 0, v, - V, < 0, and iD(vD -
VG= tkjE (20) V,) =O), then the basic Znequuli@ (9) becomes B, V, >
where Qs the total number of nonzero elements in the jth U(E- V,), and Theorem 1 is easily extended to give
row of B,, which is simply the number of diodes in the Vci = + kj(E - V,.). Hence, for an n-fold voltage multi-
fundamental loop defined by q with respect to the D-E plier, the output voltage will be actually lower than the
tree. ideal output voltage V,,= nE by n V,..
Now if we redefine the reference polarity of each capa- 5) From (4) and (18), it is easily seen that the peak
reverse voltage experienced by every diode is 2E.
citor voltage Vci so that VG is aligned with the forward-
bias direction of the diodes, then (20) reduces to
IV. STEADY-STATEANALYSIS-WITH LOAD
Vci = kjE. (21)
In the previous sections, we have considered two volt-
This completes the proof of Theorem 1. Cl age quadruplers (Figs. l(c) and 6(a)). We now ask which
With the aid of Theorem I, the conventional voltage- is the better circuit? To answer this question, we must first
multiplier circuits of Figs. 2 and 3, as well as the new define some criteria for “goodness.” For example, if we
circuits of Fig. 6(a) and Fig. 12 can now all be solved by are most concerned with the capacitor dielectric break-
inspection. The solutions of the steady-state voltage are down requirements, then Fig. l(c) ‘might be selected be-
indicated in the figures. Observe that the answers ob- cause its four capacitors are charged to [ E,2E, 2 E,4E],
tained earlier in Section I for the circuits of Figs. 2 and 3 whereas the corresponding capacitor voltages for Fig. 6(a)
using the Intuitive Method are in fact correct. However, are [ E,2E,3 E,4E]. But in many cases we may be more
for the circuit of Fig. 12, this intuitive method cannot be concerned with the voltage regulation, i.e., the drop in the
applied. In any event, since Theorem I is much easier to output voltage when a load is present, in the form of an
use, there is no reason to resort to the intuitive method of equivalent resistor R, connected in parallel with the out-
Section I, even if it is applicable. put capacitor C, (see Fig. 13(a)). In order to derive a
Every voltage-multiplier circuit generated by Algorithm quantitative comparison of such voltage drops, we shall
VM (Section II) satisfies all hypotheses of Theorem I. extend the concept of output resistance of a linear circuit
Furthermore, the -fundamental loop defined by C, with to voltage multipliers. This will be done after we make
respect to the C-E tree contains n diodes. It follows from some simplifying assumptions concerning loaded voltage
Theorem I that V,,=nE. multipliers.
For a given value of R,, the steady-state output voltage
Remarks
u,(t), and load current iL(t) will be periodic with the same
1) Theorem 1 remains valid for any periodic function period T= l/f of the input waveform. Since our objective
u,(t) as long as E g max [u,(t)]>O, and min [u;(t)]= -E. is to obtain a dc output voltage, it is desirable to choose as
2) It follows from (18) that in order to attain the large a value of the capacitance C, as possible in order to
highest capacitor voltage, we should make all elements of reduce the ripple components in u,(t) and iL(t). For the
U nonzero. This in turn requires that all elements in B E purpose of carrying out a quantitative analysis, we will
526 IEEE TRANSACTIONS ON CIRCUIT’s AND SYSTEMS, VOL. CAS-24, NO. 10, OCTOBER 1971

assume that C,,-+cc so that the output voltage becomes a

constant dc voltage v,(oo)= V, = Vcn in steady state. The
exact value of vO(co) of course depends on the amplitude
E and frequency f=w/2~ of v,(t), as well as on the load
current IL drawn by the equivalent load resistor R,, and
the values of the remaining capacitors; namely,
f”i

vo)o(m)= V,(E,w;Z,,C,,C,,...,C,-,). (22)

The voltage regulation of the multiplier depends on the
sensitivity of V, relative to It, and a convenient measure
of this sensitivity is therefore given by
n av, t iDn

R”= -al,
(23)
where R, has the unit of resistance and will henceforth be
called the output resistance of this voltage multiplier. Not-
ice that the negative sign in (23) is due to our reference
direction of IL in Fig. 13(b) which is out of the one-port
seen by the load resistor R,. Note also that (23) implicitly
assumes C,-+ cc. I (d)
We shall now describe a method for calculating R, for
any voltage multiplier N yM generated by Algorithm VM. Fig. 14. Current waveforms in output circuit.
To facilitate the discussions we shall assume without loss
of generality that the reference polarity of the input volt-
during the time interval ($ -At,t,) (respectively, (t, -
age v,(t) has been assigned in such a way that D,,-the
At, t,)), it follows that
diode in series with the output capacitor C,,- conducts
during positive peaks of u,(t) = E sin wt. We will let $, and Aqo+-=0 (27)
t, denote the positive peak and negative peak instants of Aq;+ = 0.
q(t), i.e., vi($)= E and v,(t,J= -E. The calculation of R,
is accomplished in two stages. Our next task is to determine the remaining surge charges
Ad, A&, Aq; , and Aq; in terms of AqL. Consider a
Stage I-Calculation of Surge Charges typical node “rn” as shown in Fig. 13. Kirchhoff current
During each period T=2a/w, the charge passing law requires that
through the load R, is given by for all t.
ic,(t)-i,,(t)-iC2(t)=0, (28)
AqL = IL. T= IL/f (24) If we iutegrate both sides of (28) from $,-At to tp, we
where I, is a constant current in view of our assumption obtain
that C,,+co. It was shown in Section III that when there
is no ‘load (IL =O), all currents in NV, are zero in steady
Ad, - Ad, - Aq& = 0. (29)
state. However, when a load current is drawn (ZL#O) Equation (29) is exactly of the same form as (28). This
thereby causing the output voltage to drop slightly, cur- means that KCL must be satisfied by the surge charges,
rents will also be flowing in the other branches of the provided they are referred to the same time interval.
network for short time intervals At just before the positive Although the capacitor voltages uc,, vc2,. . . , v,-~_, now
and negative peaks of v,(t). The surge charges through a vary as a function of time, they must nevertheless have
branch with current i(t) are therefore given, respectively, constant average values in steady state. This implies that
by Aq,:i+Aqcj=O, j=l;..,n-1
or
Aq<j = -Aqzj, j=l;.*,n-I. (30)
and The condition prevailing at the output,tank- consisting
of the output capacitor C,, and the load resistor R,, Fig.
Aq- k
J/,-Al‘I i(7) dr. 14(a)-requires special attention. Refer to Fig. 14(b)-(d),
and observe that when the diode D,, conducts near tp,a
The diodes D,,,D,,-2,. ++ will be collectively denoted by surge current flows into C,,. But immediately after tp,the
D, to emphasize that they conduct near the positive peak diode D,, is cut-off. Since C,, is assumed to be infinite, the
of v;(t) from tp - At to tp. Similarly, the diodes voltage vcn is equal to a constant Vcn (the steady-state
D,,-,,Q,-3,. .. will be denoted by D- to emphasize that voltage). This voltage maintains the constant load current
they conduct near the negative peaks of q(t). Since the IL = - i, = V,,/R, throughout the whole period. ,Since
diodes belonging to D _ (respectively, D+) are cut-off there should be no net increase or decrease of the charge
LIN AND CHUA: ANALYSIS OF VOLTAGE MULTIPLIER CIRC”,TS 521

on C, in steady state, it follows from Fig. 14(a) that Using QAq’ =0 and Aqg- =0 from (27) we obtain
whatever surge charge Aq& injected into C,, during the
Aq,+ -(II,+ )‘AqD’, =O. (37)
short interval At near the positive peak tp must be trans-
ferred to the load resistor R,; namely, Substituting (35) for Aqg+ in (37) we obtain
Aq&= I,.T=Aq,. (31)
Aqc+ = (B,+ )‘. Aq;+ = (B,+ )=. AqL. (38)
Since D,, is connected in series with C,,, KCL requires that
Ad, = Ad,, =h.- (32) Finally, we observe from (30) that Aq; is simply equal to
To determine other diode surge charges, consider first the -Aq,+. Note that Aq,;, does not appear as a surge (see
case n is even. The network N,, has an aligned diode Fig. 14(d)).
path starting from node 1 and terminating at node n + 1.
Example 4
Thus for each node j = 2,3,. . . , n - 1, there are exactly two
diodes connected to it, with one directed toward node j, Consider the voltage quadrupler circuit of Fig. 6(a) with
and the other away from node j. Besides, there are two or a load resistor connected across C,. The fundamental loop
more capacitors (the number of capacitors is unimportant matrix for this circuit is given by
in the argument) connected to node j. By way of illustra- C-E tree D, D-
tion, consider node 3 in Fig. 3(b). We have
C, G c3 Cd E DTD2 FD,
near $,: AqD+,-Aqc+, +Aq&=O (33)
near tn: - Aq,-, - Aq;, + Aq;s = 0. (34) B= i 0 0 -1 1’ -1; 1 0; 0 0 (39)
-1
------___ 1 00’ , -?I P- _‘c o-o_
Adding (33) and (44) and invoking (30) we obtain 0 -1 101 II 0 01 1 0
Ad, = Aq,. 1 0 0 01 II 0 01 0 1
Thus the two diode surge charges have the same magni- Hence we identify
tude although they occur at different time intervals. Ski-
lar situation applies at nodes 3,4,. . . ,n - 1 and also for
the case n is odd. Therefore we conclude that for NV,, all
-1
0
1
0 1
diode surge charges are equal to Aq,, i.e., if we define from (35): Aq;, = q&=Ab%,=Aq&=AqL
A!7D’+ g [Aq0+,, AqD+n-2, * . . 1’ and Aq& f from (38): Aq: =(Bg )‘AqL= [ -AqL,AqL, -Aq,,Aq,]’
W&i,-,,Aq,-,-3,. . . IT, then we have
from (30): Aq; = [ AqL, -AqL,AqL, -Aq,] ‘.
Aq;+ F Aq,_ = Aa. (35)
where AqL 42 [AqL, AqL,. . . , AqJT. Stage 2-Calculation of Capacitor Voltages
We shall now turn our attention to the calculation of In Section III, we have shown that the steady-state
AqC+. This is easily done by applying KCL to NV, near solution of NV, when IL = 0 must satisfy (18); namely,
t = $. During this time interval, all diodes in the D- group
B, Vc = UE. (40)
{Dn-,,Q-3,. . . > are cut-off, whereas each diode belong-
ing to the D, group { D,,, DnP2,. . * } behaves as a current Substituting this equation into (8), we observe that in
source. The capacitor surge charges Aq: can be expressed every scalar equation of (8), the equality sign will be
in terms of Aqz+ through a relationship similar to (5). An reached periodically, at positive peaks or at negative
explicit formula for Aqc will now be derived. peaks of u,(t). The physical meaning is that for this class
Further partition the fundamental loop matrix given by of networks, each diode reaches the breakpoint (iD =O,u,
(3) as follows: =0) periodically in steady state. Now when a load is
connected across C,, to draw current IL, the diodes will
C E D, D- not only reach the breakpoint, but will actually be for-
ward biased for a brief time interval. In particular, the
(36) diodes in the D, group {D,,, Dnm2,. . . } will be conduct-
ing currents from 5 -At to 5, while the diodes in the D-
C-E ‘tree D-&tree group {Dn-I,Q-3,.-- } will be conducting currents from
t, -At to t,,. Therefore, in applying (40), the scalar equa-
The associated fundamental cutset matrix is given by
tions should be separated into two groups, one applicable
CE D, D- at t = $, while the other applicable at t = t,,. The matrix B
-- in (36) has already been partitioned for this purpose.
Q=
-(B,+)T! -(B,-)’ Hence, (40) decomposes into two equations:
-(BE+)=; -(BE_)=
----I. B,+V,+=U+E (41)
D-co&& B,-V,-=U-E (42)
Let the surge charge vector Aq be similarly partitioned. where U+ and U- are associated with BE+ and BF in
528 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24, NO. 10, OCTOBER 1977

(40) respectively. See the explanatory note in Inequality
(9) for the construction of U+ and U- from BE+ and B;,
respectively.
For each capacitor q, the surge charge Aq; has been
found earlier by the use of (38). The voltage difference
VG - Vc; is therefore given by
V&J- Vc7 = Aq; / Cj, j= 1,2;. . ,n.
Again, the output capacitor C,, requires special attention.
Since C, is assumed to be infinitely large, we have VA =
Vc;l = V,. Equation (43) may be expressed more com-
pactly as
Vc’ - V; = SAq;
where
The explicit formulas (48) and (49) have been derived
for VM circuits where the output capacitor C, is in series
with a diode D,,. Voltage-multiplier circuits generated by
Algorithm VM may or may not have a series-connected
C, - D,, output tank (see the tripler of Fig. 12 for an
example of the latter case). It can be shown that (48) and
(49) are also valid for the latter case, and even for the case
(43) of finite (but large) C,,, provided that we consider V, to be
V+
Cfl’
We shall now illustrate the use of the explicit formulas
(48) and (49) with an example.
Example 5
(9 Let us continue with the voltage quadrupler circuit of
Example 4 [Fig. 6(a)]. Suppose that C, = C,= C,= C and
c,+oo

From (42), (44) and (38) we can eliminate V; and Aq;

to obtain From (39), we obtain
B,-V,+ = U-E+B,-S(B,+
Equations (41) and (45) can be combined
)TAqL. (45)
into a single B,+= [ -; y -1 0 1
01
equation

Substituting
-1 0 01 0’ 0
the above matrices into (48) and (49) we
1
obtain
(46) 31,
(50)
S$ce B, is nonsingular, and its inverse is given by Bc ’ = V”=4E- fc
BD [see (17)], we obtain the following explicit formula for and
V +.
C’ RO=+ (51)
0 By the same method, we find the output resistance for the
V,+=i$JJE+i$, (47)
B,-StB,+ IT4 voltage quadrupler circuit of Fig. l(c) to be R, =6/fC.
II
The output resistance of Fig. l(c) can also be obtained
where from the equation given in [5, (3)] by letting n = 4. It is
important to note that RO for the new voltage quadrupler
Bg and B; are defined in (36)
circuit of Fig. 6(a) is only one-half of the conventional
U is defined in (9)
quadrupler of Fig. l(c).
S is defined in (44)
Using (49) we can prove the following theorem which
kqL is defined by (35) and (24)
BD is defined in (12). constitutes the second major result of this paper.

If V, = Vcz is the only information desired, the calculation Theorem 2

of (47) should be carried out without the full effort of
finding V$. For the voltage multipliers generated by For any network generated by Algorithm VM (i.e., an
Algorithm VM, we have U= [ 1,l;. . ,l] , V,= VA, and nC-nD-1 E network which, besides satisfying the four
conditions of Theorem I, has the D-path or D-E-path
[thenthrowofgo]=[l,l,l;..,l]. Define WA terminated in C,), if the output capacitor C-co, then
[ 1,l; * * , 1 ] , then (47) leads to the output resistance is given by
V,=nE+ WTBkS(BC+ )=AqL. mj 2

Substituting (24) for AqL in (48) and using (23) we obtain

(48)

“=fE,
n-1 (1 T
lq (52)
the following explicit formula for the output resistance:
where mj is the number of diodes contained in the funda-
R, = - ( WTB;SBc+ TW)/f. (49) mental.cutset defined by Cj with respect to the C-E tree.
LIN AND CHUA: ANALYSIS OF VOLTAGE MULTIPLIER
Proof In the derivation of (32) we have assumed that
the output capacitor C,, is in series with the diode D,. This
condition can be relaxed. By a reasoning similar to that
given in (33~(34) we can easily see that Aq& =AqL, as
long as one node of C,, has only one diode D,, and
possibly several other capacitors connected to it. Since
this is true for all circuits generated by Algorithm VM, we
can repeat the derivation of the subsequent equations
(33)<49). Therefore the explicit formulas (48) and (49) are
valid for all circuits generated Algorithm VM.
Equation (49) has a topological interpretation. First,
note that from (49)
R,=-~~[allelementsofB;S(B~)T].
Since S is a diagonal matrix (see (44)) the triple product
B; ‘S(B,‘)T can be expanded quite easily to give the
contribution of 1/C, in the output resistance. We have
6 term in (53)
J multipliers:
= - -&, [jth column of BF][jth row of (B,+)T]
J
= L[no. of diodes in D- group whose f-loops contain Cj]
fq
. [no. of diodes in D, group whose f-loops contain Cj]
= -&[no. of d’to d es in D- group contained in the f-cutset
J Since Roan 3, for large n, the voltage regulation is a
defined by C, w.r.t. the C-E tree]
. [no of diodes in D, group contained in the f-cutset
defined by C, w.r.t. the C-E tree]. (54)
Summing up all of such terms in the expansion of (53) one
obtains
R, = $ ‘z’ k m/+m,-
J 1 J
where mji and mj- are the number of diodes in the D,
group and D- group, respectively, which are contained in
the fundamental cutset defined by Cj with respect to the
D-E tree.
Now for any circuit generated by Algorithm VM, we
shall show that
mj+ = mj- = -? , j=1,2;*.,n-1. (56)
2
Recall that a) when n is even, C,, has D,, connected to one
node and D, connected to the other, with D,, in the D,
group and D, in the D- group (or vice versa); b) node
labeled 0, if present, which is not a node of E has no
diode connected to it; c) each of the other nodes has
exactly two diodes connected to it, one in the D, group,
and the other in the D- group. Now consider the forma-
tion of a f-cutset defined by Cj, j# n, with respect to the
C-E tree. Removal of Cj from the C-E tree produces two
subtrees, which we shall denote by T,,, and Ts,C-E, with
the voltage source in the latter subtree. Now consider the
subtree Ts,c . The fundamental cutset defined by Ci sim-
CIRCUITS 529
ply consists of all diodes connected between one node of
T s,= and another node of T,,.-,. Upon reviewing the
properties a+z) described above, we immediately con-
clude that the number of diodes connected to T,-, is even,
and are equally divided in the D, and D- groups. Thus
(56) is valid. As an example, consider Fig. l(c). For C,,
the fundamental cutset contains all four diodes, with
ml+ =2, m,- =2, and m, =4.
Putting (56) into (55), we have (52). This completes the
proof of Theorem 2. cl
We observe that the expressions for the output resis-
tance as shown in [5, (1) and (2)] are just special cases of
Theorem 2. With Theorem 2, the problem of determining
(53) the output resistance is reduced to that of finding the
fundamental cutsets defined by the capacitors (with re-
spect to the C-E tree) and counting the diodes in the
cutsets. In particular, if we assume C, = C, = . . . = C,- , =
C, then Theorem 2 leads to (see also [5, (3) and (4)]) the
following expressions for the conventional ladder voltage
for n even, Fig. 3(a)
* (57)
for n odd, Fig. 3(b)
serious problem in voltage multipliers of large n. The
output resistance can be greatly reduced by choosing T,,
and T,, to be rooted “star” subtrees (see Fig. 6(a), for
example). For such voltage multipliers, Theorem 2 leads to
R = (n-1)
0
(55) fC
which varies only linearly with n for large n. It can be
shown that RO=(n - l)/fC is the smallest output resis-
tance obtainable with the circuits generated by Algorithm
VM. This smallest output resistance is achieved at the
expense of more costly capacitors, because the capacitor
voltages for this case are [E, 2 E, 3 E, . . . , (n - l)E, nE], in-
stead of [E,2E,2E;. . ,2E,nE] for the conventional
ladder voltage multipler.
V. CONCLUSIONS
We have described an algorithm for generating n-fold
voltage-multiplier circuits with n capacitors and n diodes.
It is shown that the conventional ladder VM circuit [3]-[5]
is just a special case generated by our Algorithm VM. A
rigorous steady-state analysis for NV, is presented both
without load and with load. For the unloaded case,
Theorem I makes it possible to determine the capacitor
voltages by inspection.
Three important factors to be considered in selecting
different voltage multiplier configurations are the capaci-
tor voltage ratings, the output resistance, and the common-
530
Esin
(b)
Fig. 15. These two voltage quadruplers, as well as Fig. 6(a), have
output resistance R, =3/fC.
ground requirement. Consider the voltage quadruplers, for
example. Algorithm VM generates a total of 9 distinct
quadruplers whose C-E trees and labeling of nodes, are
shown in Fig. 9(aHi). The connection of diodes is shown
in Fig. 9(j). After connecting the diodes, Fig. 9(a) and (b)
result in the quadruplers of Figs. l(c) and 6(a), respec-
tively. Fig. 9(c) and (d) lead to two more quadruplers
shown in Fig. 15(a) and (b), respectively, both having
RO=3/fC (assuming C, = C,= C,= C, and C4+co). The
quadruplers derived from Fig. 9(e)(i) all have R,=6/fC.
From these circuits, it is seen that Fig. 15(b) is the best
voltage quadruplers as far as the output resistance and
capacitor voltages are concerned. But this circuit has no
common terminal between the input and the output,
which makes it unsuitable for some applications. The
quadruplers of Fig. 6(a) and 15(a) are better than the
conventional quadrupler of Fig. l(c) as far as the output
resistance is concerned. But the capacitor voltages for the
former are [E, 2E, 3E,4E], whereas those for the latter are
[E,2E,2E,4E]. In other words, the third capacitor has
E-volts higher steady-state voltage across it.
Our conclusion about the selection of voltage multi-
pliers is that the conventional ladder configuration of Fig.
3 is among the best, if the capacitor voltage is the primary
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-24,N0. 10, OCTOBER 1977
concern, and the common ground is a requirement. On
the other hand, if one can tolerate the use of capacitors
with higher voltage ratings, then other voltage multiplier
circuits generated by Algorithm VM should be considered
as some of them have output resistance smaller than the
conventional ladder configuration of Fig. 3.
REFERENCES
111 M. E. Buechel, “High voltage multipliers in TV receivers,” IEEE
Trans. on Broadcast and Television Receivers, vol. 16, pp. 32-36,
Feb. 1970.
121 J. R. Woodyard, “Cockcroft-Walton accelerators,” in Encyclopedia
of Electronics, C. Susskind, Ed. New York: Reinhold, 1962.
I31 D. L. Waidhch and C. L. Shackelford, “Characteristics of voltage-
multiplying rectifiers,” Proc. IRE, vol. 32, pp. 470476, Aug. 1944.
[41 L. 0. Chua, Inrroduction to Nonlinear Network Theoty. New York:
McGraw-Hill, 1969.
151 J. S. Bruder, “Theoretical oerfonnance of voltaee multiolier
circuits,” IEEE Journal of Solid State Circuits, vol. Sc6, no. 3: pp.
132-135. June 1971.
161 N. Dee; Graph Theory with Applications to Engineering and Com-
puter Sciences. Englewood Cliffs, NJ: Prentice-Hall, 1974.
I71 L. 0. Chua and P. M. Lin, Computer-aided Analysis of Electronic
Circuits: Algorithms and Computational Techniques. Engiewood
Cliffs, NJ: Prentice-Hall, 1975.
181 S. Seshu and M. B. Reed, Linear Graphs and Electrical Networks.
Reading, MA: Addison-Wesley, 1960.
I91 P. M. Lin and L. 0. Chua, “Topological generation and analysis of
voltage multiplier circuits,” Memo ERL-M6 16, Electronics Re-
search Laboratory, College of Engineering, University of California,
Berkeley, Nov. 29, 1976.
+
P. M. Lin (M%%SM’72) was born in Liaoning,
China, on October 17, 1928. He received the
B.S. degree from National Taiwan University,
Taipei, Taiwan, in 1950, the MS. degree from
North Carolina State University, Raleigh, in
1956, and the Ph.D. degree from Purdue Uni-
veristy, Lafayette, IN, in 1960, all in electrical
engineering.
Since 1956 he has been with Purdue Univer-
sity, where he is now a Professor of Electrical
Engineering. From June 1960 to August 1961 he
was on leave of absence from Purdue University; during this time he was
with Bell Telephone Laboratories, Murray Hill, NJ, as a Member of the
Technical Staff. He visited University of California, Berkeley, on his
sabbatical leave from Purdue University in 1976. His current research
interest is in the applications of digital computer and graph theory to
electrical networks analysis. He is the coauthor of the book Computer-
aided Analysis of Electronic Circuits: Algorithms and Computational
Techniques, Published by Prentice-Hall in 1975. From 1971 to 1973, he
was an Associate Editor for IEEE TRANSACTIONS ON CIRCUIT THEORY.
Dr. Lin is a member of Sigma Xi, Tau Beta Pi, Kappa Nu, and Phi
Kappa Phi.
*
Leon 0. Chua (Ss(rM’62-SM’7(rF’74), for a photograph and biogra-
phy please see page 117 of the March 1977 issue of this TRANSACTIONS.