Winery13 Dis 09288 Ra00 0113 Final

5 4 3 2 1
D D
Winery13 CALPELLA DIS N11M-GE1 Schematics

uFCPGA Mobile Arrandale
C
Intel Ibex Peak-M C
2010-01-13
REV : A00
B B
DY : Nopop Component
UMA : Pop when schematic is UMA
DIS : Pop when schematic is DIS
A A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
www.vinafix.vn
Size Document Number Rev
Custom
Winery13 MB DIS A00
Date: Wednesday, January 13, 2010 Sheet 1 of 88
5 4 3 2 1
5 4 3 2 1
CPU DC/DC
PCB LAYER
Winery CALPELLA Block Diagram INPUTS
ISL62883
OUTPUTS
47,48
L1: Top Project code : 91.4EX01.001 +PWR_SRC +VCC_CORE
L2: GND Part Number : 48.4EX01.001

L3: Signal SYSTEM DC/DC
RT8205B 46
D
L4: Signal PCB P/N : 09288 D
L5: VCC INPUTS OUTPUTS

L6: Signal Clock Generator
Revision : A00 +15V_ALW
+3.3V_RTC_LDO
+PWR_SRC +5V_ALW
L7: GND SLG8SP585 7 +3.3V_ALW
L8: Bottom
DDRIII 1066 Channel A
DDRIII Slot 0 SYSTEM DC/DC
1066 18 TPS51116 50
100MHz/ Intel CPU 800/1066MHz Power SW
INPUTS OUTPUTS
2.5Gbps TPS2231R 34
Nvidia DDR III 1066 Channel B DDRIII Slot 1 +PWR_SRC
+1.5V_SUS
+0.75V_DDR_VTT
VRAM(gDDR3) 19 +V_DDR_REF
VRAM
N11M-GE1(40nm) PCIe x 16 800/1066MHz 1066
64Mbx16x4 (512MB)484,85 Arrandale
Bandwidth New Card SYSTEM DC/DC
PCIE x 1 & USB 2.0 x 1
80,81,82,83 :8GB 34 53
(FPC Cable to Connect) ADP3211
INPUTS OUTPUTS
LVDS RGB CRT 10/100/1000LOM RJ45
8,9,10,11,12,13,14 PCIE x 1 +PWR_SRC +CPU_GFXCORE
C C
RTL8111DL 35 CONN
CRT 55
RGB CRT RGB CRT
USB 2.0 x 2 PCIE x 1 Mini-Card SYSTEM DC/DC
WWAN/ WiMAX? TPS51218 86
Switchable DMIx4 FDI(UMA)
LCD LVDS LVDS 2.5 GT/s 2.7 GT/s 100MHz Left Side: INPUTS OUTPUTS
(Single Chanel) 54 74 USB 2.0 x 1
USB x 1
2.5Gbps +PWR_SRC +VCC_GFX_CORE
RGB CRT PCIE (On daughter board)
CHARGER
LVDS
Intel BQ24745 45
USB 2.0 USB 2.0 x 1 PCIE x 1 Mini-Card

PCH WLAN 802.11a/b/g/n 64 INPUTS OUTPUTS
480Mbps
CardReader +DC_IN
+PBATT
+PWR_SRC
(3 in 1) 14 USB 2.0/1.1 ports Right Side:

USB 2.0 x 1
SD/MMC/MMC+ USB x 1 63
33
REALTEK
ETHERNET (10/100/1000Mb) SYSTEM DC/DC
49
USB 2.0 High Definition Audio TPS51218
B
RTS5138 B
480Mbps SATA ports (6) Free fall sensor USB 2.0 x 1

SM Bus
40 Bluetooth 73 INPUTS OUTPUTS
32
PCIE ports (8)
400KHz +PWR_SRC +1.05V_VTT
LPC I/F
CAMERA ACPI 1.1
USB2.0 x 1 USB 2.0 x 1 Biometric
73 78
PCI/PCI BRIDGE LPC Bus LDO
51
33MHz APL5930
Digital Mic Array AZALIA 20,21,22,23,24,25,26,27,28
INPUTS OUTPUTS
Azalia 24MHz
+3.3V_ALW +1.8V_RUN
CODEC KBC
MIC IN SPI NUVOTON SM Bus Thermal & Fan LDO
OP AMP
SATA,USB
37 EMC2102 39,58 RT9025 51

NPCE781BA0DX
SPI
SATA
3Gbps
HP OUT INPUTS OUTPUTS

IDT
Capacity Board
92HD81UA30 78
+3.3V_ALW +1.8V_RUN_GPU
A A
1st Samsung
Flash ROM Touch Int.
256kB 62 PAD 68
KB 68 Wistron Corporation
USB,ESATA ODD Flash ROM Taipei Hsien 221, Taiwan, R.O.C.
1CH SPEAKER Multi-Port x1
63 HDD59 4MB 62 Title
60
Block Diagram
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
+PWR_SRC TPS51116PWPRG4
Adapter 50
ISL62883 ADP3211 TPS51218 TPS51218DSCR

AO4407A 、48
47 53 86 49 +V_DDR_REF +0.75V_DDR_VTT +1.5V_SUS
45 Charger
BQ24745
+VCC_CORE +CPU_GFXCORE +VCC_GFX_CORE +1.05V_VTT FDS8880
Battery +PBATT 87
45 For Intel GPU For NVIDIA GPU Arrandale : 1.05V
FDS8880 +1.5V_RUN_GPU
87
RT8205B
46
+1.05V_GFX_PCIE
C
AO3420 C
52 AO4468
+5V_ALW +5V_ALW2 +3.3V_ALW_2
42
+5V_ALW +3.3V_ALW +1.5V_CPU
+15V_ALW +3.3V_RTC_LDO +1.5V_RUN
TPS2062AD AO4468 TPS2062AD AO3403 TPS2231R AO4468 APL5930 RT9025 AO3434 TPS2231R
I/O BD 42 63 I/O BD 34 42 51 51 87 34
+5V_USB2 +5V_RUN +5V_USB1 +3.3V_LAN +3.3V_CARDAUX +3.3V_RUN +1.8V_RUN +1.8V_RUN_GPU

+3.3V_RUN_GPU +1.5V_CARD
B
For USB2 For USB1 & ESATA1 B
RTL8111DL
I/O BD
SI3456BDV TPS2231R
54 34
+1.2V_LOM
+LCDVDD +3.3V_CARD
Power Shape
Regulator LDO Switch

A A
1st Samsung
Wistron Corporation
Title
Size
Power Block Diagram
Document Number Rev
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN

Switchable Graphic SMBus Block Diagram
‧ ‧ PCH ‧ ‧
+3.3V_RUN+3.3V_RUN
+3.3V_RUN
PCH
SRN2K2J-1-GP
‧ SRN2K2J-1-GP
DIMM 1
SRN2K2J-1-GP SRN2K2J-1-GP
+3.3V_RUN
‧‧ ‧‧ ‧ ‧
+3.3V_RUN
‧
D
SMBCLK SMB_CLK PCH_SMBCLK SCL D
L_DDC_CLK L_DDC_CLK B1
VCC
SMBDATA SMB_DATA PCH_SMBDATA SDA 18 LDDC_CLK
B0 A
23 SMBus Address:A0 L_DDC_DATA GND S
‧‧
2N7002SPT PCH_SMBCLK
DIMM 2 NC7SB3157P6X-1GP
SRN2K2J-1-GP
SCL
‧‧
PCH_SMBDATA SDA 19
SMBus Address:A2 LDDC_CLK_CON
LCD Conn.
Clock LDDC_DATA_CON
54
‧‧ PCH_SMBCLK
Generator
SMBCLK +3.3V_RUN
PCH_SMBDATA SMBDATA 07
Express
SMBus address:D2
Minicard
L_DDC_DATA
LDDC_DATA
‧ ‧ B1
B0
VCC
‧‧
Card WLAN GND S
PCH_SMBCLK SMB_CLK NC7SB3157P6X-1GP
SMB_CLK SMB_CLK PCH_SMBDATA SMB_DATA 64 CRT_DDC_CLK
SMB_DATA CRT_DDC_DATA +3.3V_RUN
SMB_DATA
Minicard
‧ ‧
+3.3V_RUN
‧
34 +3.3V_RUN
‧‧
PCH_SMBCLK
WWAN
SMB_CLK
I/O BD
PCH_SMBDATA SMB_DATA SRN2K2J-1-GP
SRN2K2J-1-GP
Free fall +3.3V_RUN DY +5V_CRT_RUN
‧ ‧ ‧
C C
‧‧
sensor
‧
GMCH_DDCCLK VCC
PCH_SMBCLK SCL/SPC B1
PCH_SMBDATA 40 CRT_CLK_DDC DDC_CLK_CON2
SDA/SDI/SDO B0 A +3.3V_RUN_GPU
‧
GND S
SRN2K2J-1-GP
NC7SB3157P6X-1GP
‧‧
DDC_CLK_CON
CRT CONN
55
KBC SMBus Block Diagram N11M-GE1 +3.3V_RUN

2N7002DW-1-GP
DDC_DATA_CON
‧ ‧
+5V_RUN
‧
I2CC_SCL
GMCH_DDCDATA VCC
‧
B1
I2CC_SDA CRT_DAT_DDC DDC_DATA_CON2
B0 A
GND S
NC7SB3157P6X-1GP
SRN10KJ-5-GP
TouchPad Conn.
B
PSDAT1
PSCLK1
TPDATA
TPCLK
‧‧ TPDATA
TPCLK
TPDATA
TPCLK 68
B
I2CA_SCL
+3.3V_RTC_LDO
I2CA_SDA
‧ SCL
SDA
BQ24745
45
SMBus address:12
SRN4K7J-8-GP
Battery Conn.
‧
‧‧ ‧
SCL1 BAT_SCL PBAT_SMBCLK1 CLK_SMB
SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB 44
SRN100J-3-GP SMBus address:16
Remove HDMI
KBC ‧
NPCE781 +3.3V_RTC_LDO
+3.3V_RUN
IFPC_AUX_I2CW_SCL
‧ ‧ SRN4K7J-8-GP
+3.3V_RUN
Thermal
IFPC_AUX_I2CW_SDA#
SRN4K7J-8-GP
‧
‧
THERM_SCL SMCLK
A THERM_SDA SMDATA 39 A
SMBus address:7A
‧
‧
GPIO73/SCL2 KBC_SCL1 1st Samsung
2N7002DW-1-GP
GPIO74/SDA2 KBC_SDA1
Capacity Wistron Corporation
THERM_SCL Board 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SCL
THERM_SDA SDA (On daughter board) Title
SMBus address:0A SMBUS Block Diagram
www.vinafix.vn
C A00
Winery13 MB DIS
5 4 3 2 1
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPEAKER
AUD_SPK_L- AUD_SPK_L-_C
SPKR_PORT_D_L-
AUD_SPK_L+ AUD_SPK_L+_C
SPKR_PORT_D_L+
0R3-0-U-V-GP
DP1 EMC2102_DP1 60
MMBT3904-3-GP
SC470P50V3JN-2GP
2 Q3905 2
DN1 EMC2102_DN1
HP1_PORT_B_L AUD_HP1_JACK_L
HP
Close to PCH HP1_PORT_B_R AUD_HP1_JACK_R
Thermal OUT
EMC2102 Codec 60
DP2 VGA_THERMDA DPLUS

92HD81
SC470P50V3JN-2GP GPU
DN2 VGA_THERMDC DMINUS
54 DIS HP0_PORT_A_L
HP0_PORT_A_R
AUD_EXT_MIC_L
AUD_EXT_MIC_R
MIC
VREFOUT_A_OR_F AUD_VREFOUT_B
IN
60
3 3
DP3 T8_THERMDC
MMBT3904-3-GP
DMIC_CLK/GPIO1 AUD_DMIC_CLK
33R2J-2-GP
AUD_DMIC_CLK_G Digital
DN3 T8_THERMDA
SC470P50V3JN-2GP
Q3901
DMIC0/GPIO2
AUD_DMIC_IN0
MIC
33R2J-2-GP AUD_DMIC_IN0_R
Array 73
39
HW T8 sensor
30
4 4
1st Samsung
Wistron Corporation
Title
Thermal/Audio Block Diagram
www.vinafix.vn
Custom
Winery13 MB DIS A00
A B C D E
A B C D E
PCH Strapping Calpella Schematic Checklist Rev1.6 Processor Strapping Calpella Schematic Checklist Rev1.6
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
1 unless specified otherwise) Value
Reboot option at power-up
SPKR Default Mode: Internal weak Pull-down. CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ DisplayPort Embedded DisplayPort.
- 10-kΩ weak pull-up resistor. Intel suggest 1K resistor (Fonseca) Presence 0: Enabled - An external Display Port device is
connected to the Embedded Display Port.
INIT3_3V# Internal pull-up. Leave as "No Connect"
4 CFG[3] PCI-Express Static 1: Normal Operation. 1 4
Default Mode: Internal pull-up. Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
GNT3#/ Low (0) = Top Block Swap Mode
GPIO55 Note: Connect to ground with 4.7-kΩ weak pull-down resistor. CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
CRB uses a 1 kΩ; do not stuff resistor.
Configuration 0: Bifurcation enabled
Select
INTVRMEN High (1) = Integrated VRM is enabled
Low (0) = Integrated VRM is disabled
Note: CRB uses a 330-kΩ resistor.
Default (SPI): Leave both GNT0# and GNT1# floating. No pull up

GNT0#, required.
GNT1#
Boot from PCI:
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ
pull-down resistor. Connect GNT1# to ground with 1-kΩ pull-down
resistor. Leave GNT0# Floating.
GNT2#/ Default - Internal pull-up.
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers
only. Not for mobile/desktops).
Enable Intel Anti-Theft Technology:Connect to Vcc3_3

3 SPI_MOSI with 8.2-kΩ weak pull-up resistor. 3
Disable Intel Anti-Theft Technology:Left floating, no pull-down PCIE Routing
required.
LANE1 Card reader
NV_ALE Enable Intel Anti-Theft Technology:Connect to +NVRAM_Vccq with
8.2-kΩ weak pull-up resistor.[CRB has it pulled up with 1-kΩ
no-stuff resistor]
LANE2 MiniCard WLAN
Disable Intel Anti-Theft Technology:Leave floating (internal pull-down)
LANE3 LAN
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
LANE4 MiniCard WWAN
Low (0)- Flash Descriptor Security will be overridden. Also, when
HAD_DOCK_EN#
/GPIO[33]
this signals is sampled on the rising edge of PWROK then it will also
disable Intel ME and its features.
LANE5 New Card
High (1)-:Security measure defined in the Flash Descriptor
will be enabled.
Platform design should provide appropriate pull-up or pull-down

USB Table
depending on the desired settings. If a jumper option is used to USB
tie this signal to GND as required by the functional strap, Pair Device
the signal should be pulled low through a weak pull-down in order
to avoid asserting HDA_DOCK_EN# inadvertently. 0 USB1
Note:CRB recommends 1-kΩ pull-down for FD Override.
1 USB for ESATA
2 There is an internal pull-up of 20 kΩ for HDA_DOCK_EN# which is only
enabled at boot/reset for strapping functions.
2
2 USB2
3 RESERVE
4 WLAN
HDA_SDO Weak internal pull-down. Do not pull high. 5 WWAN
Sampled at rising edge of RSMRST#.
6 RESERVED
(Not available for HM55)
HDA_SYNC Weak internal pull-down. Do not pull high. 7 RESERVED
Sampled at rising edge of RSMRST#. (Not available for HM55)
8 BlUETOOTH
GPIO15 Low (0)-Intel ME Crypto Transport Layer Security (TLS) cipher suite 9 Card Reader
with no confidentiality
High (1)-:Intel ME Crypto Transport Layer Security (TLS) cipher suite 10 Biometric
with confidentiality 11 CAMERA
Note:
This is an unmuxed signal. 12 New Card
This signal has a weak internal pull-down of 20 KΩ which is enabled
when PWROK is low. 13 RESERVED
CRB has a 1-kΩ pull-up on this signal to +3.3VA rail.
1 GPIO8 Weak internal pull-up. Do not pull low.

1st Samsung 1
Wistron Corporation
GPIO27 Default = Do not connect (floating). Internal pull-up. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit. Title
Low (0) = Disables the VccVRM. Need to use on-board filter
Table of Content
www.vinafix.vn
circuits for analog rails.
Custom
Winery13 MB DIS A00
5 4 3 2 1
SSID = Clock GEN

D D
+3.3V_RUN +3.3V_RUN_SL585 +1.05V_VTT

+1.05V_RUN_SL585_IO
1 R708 2 1 R709 2
0R0603-PAD-2-GP 0R0603-PAD-2-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A00-0104-1 SC10U10V5ZY-1GP A00-0104-1
1
1
C702
C710 C711 C712
C703
C704
C705
C707
C708
C701 C709 SC10U10V5ZY-1GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
SC4D7P50V2CN-1GP DY DY SC1U6D3V2KX-GP
2
2
SC-1130-1
change C701 to 4.7pF for RF
+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
C C
24
17
29
15
18
1
5
U701 VGA 27M R706 R710
VDD_27
VDD_SRC_IO
VDD_CPU_IO
VDD_CPU
VDD_SRC
VDD_REF
VDD_DOT
SS DY Mount
NON-SS Mount DY +3.3V_RUN_SL585
A00-0104-1
VR_CLKEN# [47]
2
RN701 CLK_MCH_DREFCLK1# CLK_27M R706 2 1 33R2J-2-GP
[23] DREFCLK# 0R4P2R-PAD
2 3
CLK_MCH_DREFCLK1
4 DOT_96# 27MHZ 6
CLK_27M_SS R710 2 DY 1 33R2J-2-GP
CLK_VGA_27M [81]
R705
1 4 3 7
DY
G
[23] DREFCLK DOT_96 27MHZ_SS 10KR2J-3-GP
RN702 2 3 CLK_IN_DMI# 14 +3.3V_RUN
[23] CLKIN_DMI# SRC_2#
RN
[23] CLKIN_DMI 0R4P2R-PAD 1 4 CLK_IN_DMI 13 16 CPU_STOP# R701 2 1 2K2R2J-2-GP
1
SRC_2 CPU_STOP# CK_PW RGD CK_PW RGD
CKPWRGD/PD# 25 D S
[23] CLK_PCIE_SATA# RN703 2 3 CLK_PCIE_SATA1# 11 30 FSC R703 2 1 33R2J-2-GP CLK_PCH_14M [23]
SRC_1/SATA# REF_0/CPU_SEL
1
RN
RN
[23] CLK_PCIE_SATA 0R4P2R-PAD 1 4 CLK_PCIE_SATA1 10 SRC_1/SATA EC701

[23] CLK_CPU_BCLK# RN704 1 4 CLK_CPU_BCLK1# 22 28 CLK_XTAL_IN DY SC4D7P50V2CN-1GP Q701
2
CPU_0# XTAL_IN
RN
[23] CLK_CPU_BCLK 0R4P2R-PAD 2 3 CLK_CPU_BCLK1 23 27 CLK_XTAL_OUT 2N7002A-7-GP

CPU_0 XTAL_OUT
TPAD14-GP TP701 1 TP_CPU_1# 19 31 1ST: 84.2N702.E31
CPU_1# SDA PCH_SMBDATA [18,19,23,40,64,76]
TPAD14-GP TP702 1 TP_CPU_1 20 32
CPU_1 SCL PCH_SMBCLK [18,19,23,40,64,76] 2ND: 84.2N702.D31
VSS_SATA
VSS_CPU
VSS_SRC
VSS_DOT
VSS_REF
VSS_27
GND
CLK_XTAL_IN
B SLG8SP585VTR-GP B
X701
33
26
21
12
1 2 CLK_XTAL_OUT
X-14D31818M-37GP
1
CLK_VGA_27M
2
C714 C715
1st Silego 71.08585.003 SC12P50V2JN-3GP SC12P50V2JN-3GP
2
2nd ICS 71.93197.003 DY R749
0R2J-2-GP
+1.05V_VTT
1CLK_VGA_27M_RC
1st: HARMONY 82.30005.901
2
R704
2nd: ITTI 82.30005.C51
4K7R2J-2-GP
DY 3rd: TXC 82.30005.B81
2 1
FSC
2
FSC 0 1
R707
10KR2J-3-GP
DY C718
SC4D7P50V2CN-1GP
1
133MHz
SPEED 100MHz
1
(Default)
A 1st Samsung A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Clock Generator SLG8SP585

5 4
www.vinafix.vn 3 2
Date: W ednesday, January 13, 2010
Winery13 MB DIS
Sheet
1
7 of 88
A00
5 4 3 2 1
SSID = CPU
D D
CPU1A 1 OF 9
B26 PEG_IRCOMP_R R801 1 2 49D9R2F-GP
PEG_ICOMPI R802 1
PEG_ICOMPO A26 2 750R2F-GP
[22] DMI_PTX_CRXN0 A24 DMI_RX#0 PEG_RCOMPO B27
[22] DMI_PTX_CRXN1 C23 A25 EXP_RBIAS
DMI_RX#1 PEG_RBIAS PCIE_MRX_GTX_N[0..15]
[22] DMI_PTX_CRXN2 B22 DMI_RX#2 PCIE_MRX_GTX_N[0..15] [80]
A21 K35 PCIE_MRX_GTX_N15
CLARKSFIELD
[22] DMI_PTX_CRXN3 DMI_RX#3 PEG_RX#0
J34 PCIE_MRX_GTX_N14
PEG_RX#1 PCIE_MRX_GTX_N13
[22] DMI_PTX_CRXP0 B24 DMI_RX0 PEG_RX#2 J33
[22] DMI_PTX_CRXP1 D23 G35 PCIE_MRX_GTX_N12
DMI_RX1 PEG_RX#3
DMI
[22] DMI_PTX_CRXP2 B23 G32 PCIE_MRX_GTX_N11
DMI_RX2 PEG_RX#4 PCIE_MRX_GTX_N10
[22] DMI_PTX_CRXP3 A22 DMI_RX3 PEG_RX#5 F34
F31 PCIE_MRX_GTX_N9
PEG_RX#6 PCIE_MRX_GTX_N8
[22] DMI_CTX_PRXN0 D24 DMI_TX#0 PEG_RX#7 D35
[22] DMI_CTX_PRXN1 G24 E33 PCIE_MRX_GTX_N7
DMI_TX#1 PEG_RX#8 PCIE_MRX_GTX_N6
[22] DMI_CTX_PRXN2 F23 DMI_TX#2 PEG_RX#9 C33
[22] DMI_CTX_PRXN3 H23 D32 PCIE_MRX_GTX_N5
DMI_TX#3 PEG_RX#10 PCIE_MRX_GTX_N4
PEG_RX#11 B32
[22] DMI_CTX_PRXP0 D25 C31 PCIE_MRX_GTX_N3
DMI_TX0 PEG_RX#12 PCIE_MRX_GTX_N2
[22] DMI_CTX_PRXP1 F24 DMI_TX1 PEG_RX#13 B28
[22] DMI_CTX_PRXP2 E23 B30 PCIE_MRX_GTX_N1
DMI_TX2 PEG_RX#14 PCIE_MRX_GTX_N0
[22] DMI_CTX_PRXP3 G23 DMI_TX3 PEG_RX#15 A31
PCIE_MRX_GTX_P[0..15]
PCIE_MRX_GTX_P[0..15] [80]
J35 PCIE_MRX_GTX_P15
PEG_RX0 PCIE_MRX_GTX_P14
PEG_RX1 H34
C [22] FDI_TXN0 FDI_TXN0 E22
PEG_RX2 H33
F35
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P12 C
FDI_TXN1 FDI_TX#0 PEG_RX3 PCIE_MRX_GTX_P11
[22] FDI_TXN1 D21 FDI_TX#1 PEG_RX4 G33
[22] FDI_TXN2 FDI_TXN2 D19 E34 PCIE_MRX_GTX_P10
[22] FDI_TXN3 D18 FDI_TX#3 PEG_RX6 F32
[22] FDI_TXN4 FDI_TXN4 G21 D34 PCIE_MRX_GTX_P8
[22] FDI_TXN5 E19 FDI_TX#5 PEG_RX8 F33
[22] FDI_TXN6 FDI_TXN6 F21 B33 PCIE_MRX_GTX_P6
FDI_TX#6 PEG_RX9
Intel(R) FDI
[22] FDI_TXN7 FDI_TXN7 G18 D31 PCIE_MRX_GTX_P5
FDI_TX#7 PEG_RX10 PCIE_MRX_GTX_P4
PEG_RX11 A32
PCI EXPRESS -- GRAPHICS

C30 PCIE_MRX_GTX_P3
FDI_TXP0 PEG_RX12 PCIE_MRX_GTX_P2
[22] FDI_TXP0 D22 FDI_TX0 PEG_RX13 A28
[22] FDI_TXP1 FDI_TXP1 C21 B29 PCIE_MRX_GTX_P1
FDI_TXP2 FDI_TX1 PEG_RX14 PCIE_MRX_GTX_P0 PCIE_MTX_GRX_N[0..15]
[22] FDI_TXP2 D20 FDI_TX2 PEG_RX15 A30 PCIE_MTX_GRX_N[0..15] [80]
[22] FDI_TXP3 FDI_TXP3 C18
FDI_TXP4 FDI_TX3 PCIE_MTX_GRX_C_N15 C829 SCD1U10V2KX-5GP PCIE_MTX_GRX_N15
[22] FDI_TXP4 G22 FDI_TX4 PEG_TX#0 L33 1 2
[22] FDI_TXP5 FDI_TXP5 E20 M35 PCIE_MTX_GRX_C_N14 C827 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N14
FDI_TXP6 FDI_TX5 PEG_TX#1 PCIE_MTX_GRX_C_N13 C832 SCD1U10V2KX-5GP PCIE_MTX_GRX_N13
[22] FDI_TXP6 F20 FDI_TX6 PEG_TX#2 M33 1 2
[22] FDI_TXP7 FDI_TXP7 G19 M30 PCIE_MTX_GRX_C_N12 C812 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N12
FDI_TX7 PEG_TX#3 PCIE_MTX_GRX_C_N11 C803 SCD1U10V2KX-5GP PCIE_MTX_GRX_N11
PEG_TX#4 L31 1 2
[22] FDI_FSYNC0 F17 K32 PCIE_MTX_GRX_C_N10 C811 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N10
FDI_FSYNC0 PEG_TX#5 PCIE_MTX_GRX_C_N9 C828 SCD1U10V2KX-5GP PCIE_MTX_GRX_N9
[22] FDI_FSYNC1 E17 FDI_FSYNC1 PEG_TX#6 M29 1 2
J31 PCIE_MTX_GRX_C_N8 C810 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N8
PEG_TX#7 PCIE_MTX_GRX_C_N7 C823 SCD1U10V2KX-5GP PCIE_MTX_GRX_N7
[22] FDI_INT C17 FDI_INT PEG_TX#8 K29 1 2
H30 PCIE_MTX_GRX_C_N6 C804 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N6
[22] FDI_LSYNC0 F18 FDI_LSYNC0 PEG_TX#10 H29 1 2
[22] FDI_LSYNC1 D17 F29 PCIE_MTX_GRX_C_N4 C825 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N4
FDI_LSYNC1 PEG_TX#11 PCIE_MTX_GRX_C_N3 C821 SCD1U10V2KX-5GP PCIE_MTX_GRX_N3
PEG_TX#12 E28 1 2
D29 PCIE_MTX_GRX_C_N2 C813 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_N2
B Calpella Platform Design Guide PEG_TX#14 D27
PCIE_MTX_GRX_C_N0 C816
1 2
SCD1U10V2KX-5GP PCIE_MTX_GRX_N0 B
PEG_TX#15 C26 1 2
Revision 1.6 PCIE_MTX_GRX_P[0..15]
Page 89 PCIE_MTX_GRX_C_P15 C826 SCD1U10V2KX-5GP PCIE_MTX_GRX_P15 PCIE_MTX_GRX_P[0..15] [80]
PEG_TX0 L34 1 2
2.4 Arrandale Graphics Disable Guideline M34 PCIE_MTX_GRX_C_P14 C822 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P14
PEG_TX1 PCIE_MTX_GRX_C_P13 C818 SCD1U10V2KX-5GP PCIE_MTX_GRX_P13
PEG_TX2 M32 1 2
It applies to Arrandale and Clarksfield discrete graphic designs. L30 PCIE_MTX_GRX_C_P12 C815 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P12
PEG_TX4 M31 1 2
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Arrandale. The GFX_IMON, K31 PCIE_MTX_GRX_C_P10 C802 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P10
M28 1 2
FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PEG_TX6
H31 PCIE_MTX_GRX_C_P8 C805 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P8
the Arrandale side should be tied to GND (through 1-kΩ ±5% resistors). PEG_TX8 K28
PCIE_MTX_GRX_C_P6 C801
1 2
SCD1U10V2KX-5GP PCIE_MTX_GRX_P6
PEG_TX9 G30 1 2
G29 PCIE_MTX_GRX_C_P5 C814 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P5
PEG_TX11 F28 1 2
E27 PCIE_MTX_GRX_C_P3 C830 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P3
PEG_TX13 D28 1 2
C27 PCIE_MTX_GRX_C_P1 C807 1 2 SCD1U10V2KX-5GP PCIE_MTX_GRX_P1
PEG_TX15 C25 1 2
CLARKUNF
A 1st Samsung
A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
www.vinafix.vn
Winery13 MB DIS A00
Date: W ednesday, January 13, 2010 Sheet 8 of 88
5 4 3 SA 07/01 Check 2
1.assign GPIO EC_GPIO91 ??
SB-1020-1 1
DY R935, POP C915,R934, Q901
Processor Compensation Signals SB-1022
+1.05V_VTT CPU1B 2 OF 9 RN901 change to 22 ohm
Processor Pullups H_COMP3
DDR_RST_GATE# [25] +3.3V_ALW
1 2 AT23 COMP3
R901 20R2F-GP A16 BCLK_CPU_P_R 2 3 RN901 C915
BCLK BCLK_CPU_P [25]
1
MISC
R902 1 2 49D9R2F-GP H_CATERR# 1 2 H_COMP2 AT24 B16 BCLK_CPU_N_R 1 4 SRN22J-7-GP SCD047U10V2KX-2GP
COMP2 BCLK# BCLK_CPU_N [25]
R903 20R2F-GP
H_COMP1 +1.5V_SUS
CLOCKS
1 2 G16 AR30
Check
2
COMP1 BCLK_ITP
RN
R933 1 2 68R2-GP H_PROCHOT_R# R905 49D9R2F-GP AT30 A00-0104-1 DDR_RST_GATE#1 2
BCLK_ITP#
CLARKSFIELD
1 2 H_COMP0 AT26 R937 10KR2J-3-GP
COMP0
1
R906 49D9R2F-GP E16 PEG_CLK_R 1 4 RN903 CLK_EXP_P [23]
PEG_CLK PEG_CLK#_R
PEG_CLK# D16 2 3 0R4P2R-PAD CLK_EXP_N [23] R934
D TPAD14-GP TP901 1 SKTOCC#_R AH24 SKTOCC#
A18 DPLL_REF_SSCLK_R 2 3
Q901
BSS138-7-F-GP
1KR2J-1-GP
SB-1103
D
G
DPLL_REF_SSCLK DPLL_REF_SSCLK#_R SRN1KJ-7-GP
A17 1 4 change Q901 to 84.00138.F31
2
H_CATERR# DPLL_REF_SSCLK# RN904
AK14 CATERR#
THERMAL
S D DDR3_DRAMRST# [18,19]
SSID = CPU [25] H_PECI AT15 PECI

SM_DRAMRST# F6 SM_DRAMRST#
RN905
+1.05V_VTT
Vgs(th)<=1.5V
AL1 SM_RCOMP_0 4 1 1ST: 84.00138.E31
R936 SM_RCOMP0 SM_RCOMP_1 SM_DRAMRST#
SM_RCOMP1 AM1 3 2 2ND: 1 2
RN
0R2J-2-GP AN1 SM_RCOMP_2 R935
H_PROCHOT_R# SM_RCOMP2 SRN10KJ-5-GP R988
[47] H_PROCHOT# 1
DY 2 AN26 PROCHOT#
AN15 PM_EXTTS#0_C 1 4 PM_EXTTS#0 [18]
1
DY 2
100KR2J-1-GP
PM_EXT_TS#0
PM_EXT_TS#1 AP15 PM_EXTTS#1_C 2 3 PM_EXTTS#1 [19] 0R2J-2-GP SB-1023
RN906
0R4P2R-PAD
pop R988 for S3
Calpella Platform S3 Power Reduction Platform
DDR3
MISC
[25,37,42] H_THRMTRIP# AK15 THERMTRIP#
A00-0104-1 reduce function
Check S3 Power Reduction CRB Implementation
SB-1026 PRDY# AT28 Design Details Revision 0.1
1. remove 1K ohm for remove XDP PREQ# AP27
TCK AN28 R923

TP902 1 TP_RESET_OBS# AP26 RESET_OBS# TMS AP28
PWR MANAGEMENT
TPAD14-GP AT27 XDP_TRST# 1 2 DDR3 Compensation Signals
TRST#
JTAG & BPM

AL15 AT29 SM_RCOMP_0 R907 1 2 100R2F-L1-GP-U
[22] H_PM_SYNC PM_SYNC TDI 51R2J-2-GP
AR27 XDP_TDO_R
TDO TDI_M SM_RCOMP_1
TDI_M AR29 1 R908 2 A00-0104-1 R910 1 2 24D9R2F-L-GP
AN14 AP29 TDO_M 0R0402-PAD-2-GP
VCCPW RGOOD_1 TDO_M
C DBR# AN25 H_DBR#_R 1 R909 2 XDP_DBRESET# [22]
SM_RCOMP_2 R911 1 2 130R2F-1-GP
C
H_PWRGOOD AN27 0R0402-PAD-2-GP
[25,42] H_PWRGOOD VCCPW RGOOD_0
BPM#0 AJ22
[22] PM_DRAM_PWRGD AK13 SM_DRAMPW ROK BPM#1 AK22
BPM#2 AK24
AJ24 +1.05V_VTT
BPM#3
[49] H_VTTPWRGD AM15 VTTPW RGOOD BPM#4 AJ25
BPM#5 AH22
BPM#6 AK23 R928
TPAD14-GP TP903 1 TP_TAPPWRGOOD AM26 TAPPW RGOOD BPM#7 AH23
XDP_TDO_R 2 1
R913
1 2 PLT_RST#_R AL14
[21,34,36,37,64,70,76,80] PLT_RST# RSTIN# 51R2J-2-GP
1
1K6R2F-GP
R915
750R2F-GP CLARKUNF
Check
2
Normal
+3.3V_ALW
+1.5V_CPU
R919 R920 R977
B B
R989 1 2 10KR2J-3-GP AUB 1.27k 3k 1.6k(DY)
1
R919
U927 1K27R2F-L-GP
DY CFD 1.1k 3k 1.5k(DY)
U927_B 1 B
5 R977
2
VCC
[37,49,52] VTT_PWRGD 2 A S3 Power Reduction circuit
4 VTT_PWRGD_R3 2 1 PM_DRAM_PWRGD
Y
3 GND
1
1K6R2F-GP R919 R920 R977
R920
74LVC1G08GW-1-GP 750R2F-GP
AUB 1.1k(DY) 0.75k 1.6k
1ST: 73.01G08.L04
2
2ND:
CFD 1.1k(DY) 0.75k 1.5k
SB-1020-1
POP R977 for S3 redution
DY R919, change R920 to 0.75K
Remove XDP function for layout concern

A 1st Samsung
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
Winery13 MB DIS A00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
SSID = CPU CPU1D 4 OF 9
CPU1C 3 OF 9
SB_CK0 W8 M_CLK_DDR2 [19]

M_B_DQ[63..0] W9
[19] M_B_DQ[63..0] M_CLK_DDR#2 [19]
CLARKSFIELD
M_B_DQ0 SB_CK#0
SA_CK0 AA6 M_CLK_DDR0 [18] B5 SB_DQ0 SB_CKE0 M3 M_CKE2 [19]
AA7 M_CLK_DDR#0 [18] M_B_DQ1 A5
SA_CK#0 SB_DQ1
CLARKSFIELD
M_A_DQ[63..0] P7 M_B_DQ2 C3
[18] M_A_DQ[63..0] SA_CKE0 M_CKE0 [18] SB_DQ2
M_A_DQ0 A10 M_B_DQ3 B3 V7 M_CLK_DDR3 [19]
M_A_DQ1 SA_DQ0 M_B_DQ4 SB_DQ3 SB_CK1
D C10 SA_DQ1 E4 SB_DQ4 SB_CK#1 V6 M_CLK_DDR#3 [19] D
M_A_DQ2 C7 M_B_DQ5 A6 M2 M_CKE3 [19]
M_A_DQ3 SA_DQ2 M_B_DQ6 SB_DQ5 SB_CKE1
A7 SA_DQ3 SA_CK1 Y6 M_CLK_DDR1 [18] A4 SB_DQ6
M_A_DQ4 B10 Y5 M_CLK_DDR#1 [18] M_B_DQ7 C4
M_A_DQ5 SA_DQ4 SA_CK#1 M_B_DQ8 SB_DQ7
D10 SA_DQ5 SA_CKE1 P6 M_CKE1 [18] D1 SB_DQ8
M_A_DQ6 E10 M_B_DQ9 D2
M_A_DQ7 SA_DQ6 M_B_DQ10 SB_DQ9
A8 SA_DQ7 F2 SB_DQ10 SB_CS#0 AB8 M_CS2# [19]
M_A_DQ8 D8 M_B_DQ11 F1 AD6 M_CS3# [19]
M_A_DQ9 SA_DQ8 M_B_DQ12 SB_DQ11 SB_CS#1
F10 SA_DQ9 SA_CS#0 AE2 M_CS0# [18] C2 SB_DQ12
M_A_DQ10 E6 AE8 M_CS1# [18] M_B_DQ13 F5
M_A_DQ11 SA_DQ10 SA_CS#1 M_B_DQ14 SB_DQ13
F7 SA_DQ11 F3 SB_DQ14
M_A_DQ12 E9 M_B_DQ15 G4 AC7 M_ODT2 [19]
M_A_DQ13 SA_DQ12 M_B_DQ16 SB_DQ15 SB_ODT0
B7 SA_DQ13 H6 SB_DQ16 SB_ODT1 AD1 M_ODT3 [19]
M_A_DQ14 E7 AD8 M_ODT0 [18] M_B_DQ17 G2
M_A_DQ15 SA_DQ14 SA_ODT0 M_B_DQ18 SB_DQ17
C6 SA_DQ15 SA_ODT1 AF9 M_ODT1 [18] J6 SB_DQ18
M_A_DQ16 H10 M_B_DQ19 J3
G8 SA_DQ17 G1 SB_DQ20
M_A_DQ18 K7 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ19 SA_DQ18 M_B_DQ22 SB_DQ21 SB_DM0 M_B_DM1
J8 SA_DQ19 J2 SB_DQ22 SB_DM1 E1
M_A_DQ20 G7 M_B_DQ23 J1 H3 M_B_DM2
M_A_DQ21 SA_DQ20 M_B_DQ24 SB_DQ23 SB_DM2 M_B_DM3
G10 SA_DQ21 J5 SB_DQ24 SB_DM3 K1
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ25 K2 AH1 M_B_DM4
M_A_DQ23 SA_DQ22 SA_DM0 M_A_DM1 M_B_DQ26 SB_DQ25 SB_DM4 M_B_DM5
J10 SA_DQ23 SA_DM1 D7 L3 SB_DQ26 SB_DM5 AL2 M_B_DM[7..0] [19]
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ25 SA_DQ24 SA_DM2 M_A_DM3 M_B_DQ28 SB_DQ27 SB_DM6 M_B_DM7
M6 SA_DQ25 SA_DM3 M7 K5 SB_DQ28 SB_DM7 AT8 M_B_DQS#[7..0] [19]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ29 K4
M_A_DQ27 SA_DQ26 SA_DM4 M_A_DM5 M_B_DQ30 SB_DQ29
L9 SA_DQ27 SA_DM5 AM7 M_A_DM[7..0] [18] M4 SB_DQ30
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ31 N5 M_B_DQS[7..0] [19]
M_A_DQ29 SA_DQ28 SA_DM6 M_A_DM7 M_B_DQ32 SB_DQ31
K8 SA_DQ29 SA_DM7 AN13 M_A_DQS#[7..0] [18] AF3 SB_DQ32
C M_A_DQ30 N8 M_B_DQ33 AG1 M_B_A[15..0] [19]
C
M_A_DQ31 SA_DQ30 M_B_DQ34 SB_DQ33 M_B_DQS#0
P9 SA_DQ31 AJ3 SB_DQ34 SB_DQS#0 D5
M_A_DQ32 AH5 M_A_DQS[7..0] [18] M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ33 SA_DQ32 M_B_DQ36 SB_DQ35 SB_DQS#1 M_B_DQS#2
AF5 SA_DQ33 AG4 SB_DQ36 SB_DQS#2 J4
M_A_DQ34 AK6 C9 M_A_DQS#0 M_A_A[15..0] [18] M_B_DQ37 AG3 L4 M_B_DQS#3
M_A_DQ35 SA_DQ34 SA_DQS#0 M_A_DQS#1 M_B_DQ38 SB_DQ37 SB_DQS#3 M_B_DQS#4
AK7 SA_DQ35 SA_DQS#1 F8 AJ4 SB_DQ38 SB_DQS#4 AH2
M_A_DQ36 AF6 J9 M_A_DQS#2 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ36 SA_DQS#2 SB_DQ39 SB_DQS#5
DDR SYSTEM MEMORY A
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

SA_DQ37 SA_DQS#3 SB_DQ40 SB_DQS#6
DDR SYSTEM MEMORY - B

M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ41 AK4 AR8 M_B_DQS#7
M_A_DQ39 SA_DQ38 SA_DQS#4 M_A_DQS#5 M_B_DQ42 SB_DQ41 SB_DQS#7
AJ6 SA_DQ39 SA_DQS#5 AK9 AM6 SB_DQ42
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ43 AN2
M_A_DQ41 SA_DQ40 SA_DQS#6 M_A_DQS#7 M_B_DQ44 SB_DQ43
AJ9 SA_DQ41 SA_DQS#7 AT13 AK5 SB_DQ44
M_A_DQ42 AL10 M_B_DQ45 AK2
AK12 SA_DQ43 AM4 SB_DQ46
M_A_DQ44 AK8 M_B_DQ47 AM3
M_A_DQ45 SA_DQ44 M_B_DQ48 SB_DQ47 M_B_DQS0
AL7 SA_DQ45 AP3 SB_DQ48 SB_DQS0 C5
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ49 AN5 E3 M_B_DQS1
M_A_DQ47 SA_DQ46 SA_DQS0 M_A_DQS1 M_B_DQ50 SB_DQ49 SB_DQS1 M_B_DQS2
AL8 SA_DQ47 SA_DQS1 F9 AT4 SB_DQ50 SB_DQS2 H4
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ51 AN6 M5 M_B_DQS3
AM10 SA_DQ49 SA_DQS3 M9 AN4 SB_DQ52 SB_DQS4 AG2
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ53 AN3 AL5 M_B_DQS5
AL11 SA_DQ51 SA_DQS5 AK10 AT5 SB_DQ54 SB_DQS6 AP5
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ53 SA_DQ52 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS7
AN9 SA_DQ53 SA_DQS7 AR13 AN7 SB_DQ56
M_A_DQ54 AT11 M_B_DQ57 AP6
AP12 SA_DQ55 AP8 SB_DQ58
M_A_DQ56 AM12 M_B_DQ59 AT9
AN12 SA_DQ57 AT7 SB_DQ60
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ61 AP9
B M_A_DQ59 SA_DQ58 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 B
AT14 SA_DQ59 SA_MA1 W1 AR10 SB_DQ62
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ61 SA_DQ60 SA_MA2 M_A_A3 SB_DQ63 SB_MA0 M_B_A1
AL13 SA_DQ61 SA_MA3 AA3 SB_MA1 V2
M_A_DQ62 AR14 V1 M_A_A4 T5 M_B_A2
M_A_DQ63 SA_DQ62 SA_MA4 M_A_A5 SB_MA2 M_B_A3
AP14 SA_DQ63 SA_MA5 AA9 SB_MA3 V3
V8 M_A_A6 R1 M_B_A4
SA_MA6 M_A_A7 SB_MA4 M_B_A5
SA_MA7 T1 [19] M_B_BS0 AB1 SB_BS0 SB_MA5 T8
Y9 M_A_A8 [19] M_B_BS1 W5 R2 M_B_A6
SA_MA8 M_A_A9 SB_BS1 SB_MA6 M_B_A7
[18] M_A_BS0 AC3 SA_BS0 SA_MA9 U6 [19] M_B_BS2 R7 SB_BS2 SB_MA7 R6
[18] M_A_BS1 AB2 AD4 M_A_A10 R4 M_B_A8
SA_BS1 SA_MA10 M_A_A11 SB_MA8 M_B_A9
[18] M_A_BS2 U7 SA_BS2 SA_MA11 T2 SB_MA9 R5
U3 M_A_A12 [19] M_B_CAS# AC5 AB5 M_B_A10
SA_MA12 M_A_A13 SB_CAS# SB_MA10 M_B_A11
SA_MA13 AG8 [19] M_B_RAS# Y7 SB_RAS# SB_MA11 P3
T3 M_A_A14 [19] M_B_W E# AC6 R3 M_B_A12
SA_MA14 M_A_A15 SB_WE# SB_MA12 M_B_A13
[18] M_A_CAS# AE1 SA_CAS# SA_MA15 V9 SB_MA13 AF7
[18] M_A_RAS# AB3 P5 M_B_A14
SA_RAS# SB_MA14 M_B_A15
[18] M_A_W E# AE9 SA_WE# SB_MA15 N1
CLARKUNF
A CLARKUNF 1st Samsung A
Wistron Corporation
Title
CPU (DDR)
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
10 of 88
A00
5 4 3 2 1
SSID = CPU
CPU1E 5 OF 9
AJ13
RSVD#AJ13
D AJ12 D
RSVD#AJ12
AP25
RSVD#AP25
CLARKSFIELD
AL25 AH25
RSVD#AL25 RSVD#AH25
AL24 AK26
RSVD#AL24 RSVD#AK26
AL22
RSVD#AL22
AJ33 AL26
RSVD#AJ33 RSVD#AL26
AG9 AR2
RSVD#AG9 RSVD_NCTF_37
M27
CFG0 RSVD#M27
L28 AJ26
TP1116 SA_DIMM_VREF# RSVD#L28 RSVD#AJ26
PCI-Express Configuration Select 1 J17
SA_DIMM_VREF RSVD#AJ27
AJ27
1
TP1117 1 SB_DIMM_VREF# H17

R1101 SB_DIMM_VREF
G25
3KR2F-GP RSVD#G25
DY 1:Single PEG G17
RSVD#G17
CFG0 0:Bifurcation enabled E31
RSVD#E31
E30
2
RSVD#E30
改5%
AL28
CFG0 RSVD#AL28
AM30 AL29
CFG0 RSVD#AL29
DIS AM28
AP31
CFG1 RSVD#AP30
AP30
AP32
CFG3 CFG2 RSVD#AP32
AL32 AL27
CFG3 CFG4 CFG3 RSVD#AL27
AL30 AT31
CFG4 RSVD#AT31
CFG3 - PCI-Express Static Lane Reversal AM31
CFG5 RSVD#AT32
AT32
1
AN29 AP33
R1102 CFG6 RSVD#AP33
AM32 AR33
3KR2F-GP CFG7 RSVD#AR33
1 :Normal Operation AK32
CFG8
CFG3 AK31
RESERVED
0 :Lane Numbers Reversed AK28
CFG9
C C
2
15 -> 0, 14 -> 1, ... CFG10

AJ28
CFG11
AN30 AR32
CFG12 RSVD#AR32
AN32
CFG13
AJ32
CFG14
DW AJ29
AJ30
CFG15 RSVD_TP#E15
E15
F15
07/10 Reversal CFG16 RSVD_TP#F15
AK30 A2
1.PCI-Express Static Lane Reversal CFG17 KEY
H16 D15
RSVD_TP_86 RSVD#D15
C15
RSVD#C15 TP_RSVD64_R TP1121 TPAD14-GP
AJ15 1
RSVD#AJ15 TP_RSVD65_R TP1122 TPAD14-GP
AH15 1
CFG4 RSVD#AH15
CFG4 - Display Port Presence B19
1
RSVD#B19
A19
R1103 RSVD#A19
3KR2F-GP 1:Disabled; No Physical Display Port TPAD14-GP TP1119 TP_H_RSVD17_R A20
DY CFG4 TPAD14-GP TP1120
1
1 TP_H_RSVD18_R B20 RSVD#A20
attached to Embedded Display Port RSVD#B20
AA5
2
0:Enabled; An external Display Port SA_CK2

U9 AA4
RSVD#U9 SA_CK#2
device is connected to the Embedded T9
RSVD#T9 SA_CKE2
R8
AD3
Display Port AC9
SA_CS#2
AD2
RSVD#AC9 SA_ODT2
AB9 AA2
RSVD#AB9 SA_CK3
AA1
SA_CK#3
R9
SA_CKE3
AG7
SA_CS#3
AE3
SA_ODT3
Calpella Platform Design Guide
Revision 1.6 V4
SB_CK2
V5
SB_CK#2
4.8.3.1 LVDS Switching SB_CKE2
N2
B J29 AD5 B
RSVD#J29 SB_CS#2
Switchable GFX, just like integrated GFX only, to enable LVDS it is required that the J28
RSVD#J28 SB_ODT2
AD7
W3
OEM set the LDVS (L_DDC_DATA) strap to present (pulled up) and the eDP strap SB_CK3
W2
SB_CK#3
(CFG[4]) to disabled (not pulled down). SB_CKE3
N3
AE5
SB_CS#3
4.8.3.2 eDP Switching SB_ODT3
AD9
eDP for Switchable GFX can only be driven out of Port D of PCH. To configure Port D for
AP34
embedded DP it is required to set the DDPD_CTRLDATA strap high to 3.3V Core rail VSS
through 2.2 kΩ ±5% resistor, LVDS (L_DDC_DATA) strap as no connect and the eDP
strap CFG[4] as no connect. Page 482,486
CLARKUNF
DW
07/02 Added
CFG7(Reserved) - Temporarily used for early 1.Added display Switchable strap commentariat
Clarksfield samples.
CFG7 Clarksfield (only for early samples pre-ES1) -

Connect to GND with 3.01K Ohm/5% resistor.
Note: Only temporary for early CFD sample

(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
DW30 Only support Arrandale, the pull-down resistor shouble be used. Does
A
CFG7 no need pull down not impact AUB functionality. A
1st Samsung
Wistron Corporation
Title
CPU (RESERVED)
www.vinafix.vn
Winery13 MB DIS A00

5 4 3 2 1
5 4 3 2 1
CPU1F 6 OF 9
SSID = CPU +VCC_CORE

18A
CLARKSFIELD
+1.05V_VTT
PROCESSOR CORE POWER
AG35 AH14
VCC VTT0
AG34 AH12
1
VCC VTT0 C1201 C1202 C1203 C1216 C1217 C1218 C1219 C1204 C1205
AG33 AH11
+VCC_CORE 48A (Arburdale) AG32
VCC
VCC
VTT0
VTT0
AH10
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC1U6D3V2KX-GP
AG31 J14
2
VCC VTT0
D AG30 J13 D
VCC VTT0
AG29 H14
C1206 C1207 C1208 C1209 C1220 C1210 VCC VTT0
AG28 H12
VCC VTT0
1
1
AG27 G14
VCC VTT0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
DY DY AG26
AF35
VCC VTT0
G13
G12
2
2
VCC VTT0
AF34 G11
VCC VTT0
AF33 F14
VCC VTT0
AF32 F13
VCC VTT0 +1.05V_VTT
AF31 F12
VCC VTT0
AF30 F11
VCC VTT0
AF29
VCC VTT0
E14
C1211 C1221 C1222
The decoupling capacitors, filter
AF28 E12
VCC VTT0 recommendations and sense resistors on the
1
AF27 D14
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
AF26
VCC VTT0
D13
DY DY CPU/PCH Rails are specific to the CRB
1.1V RAIL POWER

C1212 C1213 C1214 C1215 C1223 C1224 AD35 D12
2
VCC VTT0 Implementation. Customers need to follow the
1
1 AD34
VCC VTT0
D11
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
DY DY DY AD33
VCC VTT0
C14 recommendations in the Calpella Platform
AD32 C13
2
AD31
VCC VTT0
C12 Design Guide.
VCC VTT0
AD30 C11
VCC VTT0
AD29 B14
VCC VTT0
AD28 B12
VCC VTT0
AD27 A14
VCC VTT0
AD26 A13
VCC VTT0
AC35 A12
VCC VTT0
AC34 A11
VCC VTT0
AC33
C1225 C1226 C1227 C1228 C1229 C1230 C1231 C1232 VCC +1.05V_VTT
AC32
VCC
1
AC31
VCC
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY DY AC30
AC29
VCC VTT0
AF10
AE10
2
VCC VTT0 C1233 C1234

AC28 AC10
VCC VTT0
1
CPU CORE SUPPLY
C AC27 AB10 C
VCC VTT0
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
AC26
AA35
VCC VTT0
Y10
W10
DY
2
VCC VTT0
AA34 U10
VCC VTT0
AA33 T10
VCC VTT0
AA32 J12
VCC VTT0
AA31 J11
VCC VTT0
AA30 J16
C1235 C1236 C1237 C1238 C1239 C1240 C1241 C1242 VCC VTT0
AA29 J15
1
VCC VTT0
AA28
VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
DY DY DY DY DY AA27
AA26
VCC
2
VCC
Y35
Y34
VCC Please note that the VTT Rail
VCC
Y33
Y32
VCC Values are
VCC
Y31
VCC Arrandale VTT=1.05V;
Y30
VCC
Y29
VCC Clarksfield VTT=1.1V
Y28
VCC
Y27
VCC H_VTTVID1 = Low, 1.1V
Y26
H_VTTVID1 = High, 1.05V
1
C1243 VCC
V35 AN33 PSI# [47]
SCD1U50V3KX-GP VCC PSI#
V34
VCC
V33 CPU_VID[6..0] [47]
2
VCC CPU_VID0
V32 AK35
VCC VID
V31
V30
V29
VCC
VCC
POWER VID
VID
AK33
AK34
AL35
CPU_VID1
CPU_VID2
CPU_VID3
VCC VID
V28
VCC CPU VIDS VID
AL33 CPU_VID4
SA
V27 AM33 CPU_VID5
VCC VID 07/01 Check
SC-1207-1 V26
VCC VID
AM35 CPU_VID6
1.DPRSLPVR ??
pop C1243 and change size to 0603 for EMI U35 AM34 PM_DPRSLPVR [47]
VCC PROC_DPRSLPVR
B U34 B
VCC
U33
VCC
U32
VCC TP_H_VTTVID1
U31 G15 1
VCC VTT_SELECT TP1203 TPAD14-GP
U30
VCC
U29
VCC
U28
VCC
U27
VCC +VCC_CORE
U26
VCC
R35
VCC
R34
1
VCC
R33
VCC R1201
R32 AN35 IMVP_IMON [47]
VCC ISENSE 100R2F-L1-GP-U
R31
VCC
R30
VCC
R29
2
VCC VCC_SENSE
SENSE LINES
R28 AJ34 VCC_SENSE [47]

VCC VCC_SENSE VSS_SENSE
R27 AJ35 VSS_SENSE [47]
VCC VSS_SENSE
R26
1
VCC
P35
VCC R1204
P34 B15 VTT_SENSE [49]
VCC VTT_SENSE TP_VSS_SENSE_VTT 1 100R2F-L1-GP-U
P33 A15
VCC VSS_SENSE_VTT TP1202
P32
VCC TPAD14-GP
P31
2
VCC
P30
VCC
P29
VCC
P28
VCC
P27
VCC
P26
VCC
A A
1st Samsung
CLARKUNF
Wistron Corporation
Title
CPU (VCC_CORE)
www.vinafix.vn
Winery13 MB DIS A00

5 4 3 2 1
5 4 3 2 1
+1.5V_CPU +1.5V_CPU +1.5V_CPU +1.5V_CPU
SSID = CPU
1
DYC1376 DYC1377 DYC1378 DYC1379
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
+CPU_GFXCORE
+1.5V_SUS +1.5V_SUS +1.5V_SUS +1.5V_SUS
22A CPU1G 7 OF 9
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9.pdf"
AT21 document.
VAXG
D AT19 VAXG VAXG_SENSE AR22 VCC_AXG_SENSE [53] D
SENSE
LINES
AT18 VAXG VSSAXG_SENSE AT22 VSS_AXG_SENSE [53]
TC1303 C1324 C1327 C1326 C1329 C1328 C1325 C1323 C1330 AT16 VAXG
CLARKSFIELD
1
1
AR21 VAXG
SE330U2VDM-L-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
DY DY DY DY AR19 VAXG
SC1U6D3V2KX-GP
AR18
2
VAXG
AR16 VAXG GFX_VID AM22 GFX_VID0 [53]
AP21 VAXG GFX_VID AP22 GFX_VID1 [53]
GRAPHICS VIDs
AP19 VAXG GFX_VID AN22 GFX_VID2 [53]
AP18 VAXG GFX_VID AP23 GFX_VID3 [53]
AP16 VAXG GFX_VID AM23 GFX_VID4 [53]
AN21 VAXG GFX_VID AP24 GFX_VID5 [53]
GRAPHICS
AN19 VAXG GFX_VID AN24 GFX_VID6 [53]
AN18 VAXG
AN16 VAXG
AM21 VAXG GFX_VR_EN AR25 GFX_VR_EN [53]
AM19 AT25 TP_GFX_DPRSLPVR1 TP1303TPAD14-GP
VAXG GFX_DPRSLPVR
AM18 VAXG GFX_IMON AM24 GFX_IMON [53]
AM16 VAXG
AL21 VAXG For no use switch graphic function
AL19 VAXG
AL18 +1.5V_CPU
AL16
AK21
VAXG
VAXG
AJ1
3A
VAXG VDDQ
AK19 VAXG VDDQ AF1
1
C1301 C1302 C1303 C1304 C1305 C1306 C1307
AK18 AE7
DY
- 1.5V RAILS
VAXG VDDQ
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AK16 AE4 TC1301
VAXG VDDQ SE330U2D5VDM-2GP
AJ21 AC1
2
VAXG VDDQ
AJ19 VAXG VDDQ AB7
C AJ18 AB4 C
VAXG VDDQ
AJ16 VAXG VDDQ Y1
AH21 VAXG VDDQ W7
AH19 VAXG VDDQ W4
AH18 VAXG VDDQ U1
AH16 T7
POWER
VAXG VDDQ
VDDQ T4
VDDQ P1
VDDQ N7
+1.05V_VTT N4
VDDQ
DDR3
VDDQ L1
J24 VTT1 VDDQ H1
FDI
J23 VTT1
H25 VTT1
1
C1308 C1309 +1.05V_VTT

SC10U6D3V5MX-3GP SC10U6D3V5KX-1GP
DY P10
2
VTT0
VTT0 N10
1
L10 C1310 C1311
VTT0 SC10U6D3V5MX-3GP SC10U6D3V5KX-1GP
VTT0 K10
DY
2
+1.05V_VTT
+1.05V_VTT
18A
1.1V
VTT1 J22
K26 VTT1 VTT1 J20
1
J27 J18 C1316 C1317
VTT1 VTT1
PEG & DMI

SC10U6D3V5KX-1GP
J26 VTT1 VTT1 H21
DYSC10U6D3V5MX-3GP
1
C1312 C1313 C1314 C1315 J25 H20
2
B VTT1 VTT1 B
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
DY H27
G28
VTT1 VTT1 H19
2
VTT1
G27 VTT1
G26 +1.8V_RUN
F26
E26
VTT1
VTT1
L26
1.35A
VTT1 VCCPLL
1.8V
E25 VTT1 VCCPLL L27
1
M26 C1318 C1319 C1320 C1321 C1322
VCCPLL
SC1U25V5KX-1GP
SC1U25V5KX-1GP
SC4D7U6D3V5KX-3GP
SC2D2U6D3V3KX-GP
SC10U6D3V5MX-3GP
2
CLARKUNF
A 1st Samsung A
Wistron Corporation
Title
Size Document Number

CPU (VCC_GFXCORE) Rev
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
13 of 88
A00
5 4 3 2 1
SSID = CPU CPU1H 8 OF 9 CPU1I 9 OF 9
AT20 VSS VSS AE34

AT17 VSS VSS AE33
AR31 VSS VSS AE32 K27 VSS
CLARKSFIELD
CLARKSFIELD
D AR23 VSS VSS AE28 J32 VSS D
AR20 VSS VSS AE27 J30 VSS
AR12 VSS VSS AD10 H35 VSS
AR9 VSS VSS AC8 H32 VSS
AP20 VSS VSS AB35 H24 VSS
AN34 VSS VSS AB28 H5 VSS
AN31 VSS VSS AB27 H2 VSS
AN23 VSS VSS AB26 G34 VSS
AN20 VSS VSS AB6 G31 VSS
AN17 VSS VSS AA10 G20 VSS
AM29 VSS VSS Y8 G9 VSS
AM20 VSS VSS W35 F30 VSS
C AM2 W29 E35 C
VSS VSS VSS
AL34 W28 E32
AL31
AL23
VSS
VSS
VSS
VSS VSS
VSS
VSS
W27
W26
E29
E24
VSS
VSS
VSS
VSS
AL20 VSS VSS W6 E21 VSS
AL17 VSS VSS V10 E18 VSS
AL12 VSS VSS U8 E13 VSS
AL3 VSS VSS T35 E5 VSS
AK29 VSS VSS T34 E2 VSS
AK27 VSS VSS T33 D33 VSS
AK25 VSS VSS T32 D30 VSS VSS_NCTF AR34
AK20 VSS VSS T31 D26 VSS VSS_NCTF B34
AK17 T30 D9 B2
NCTF
VSS VSS VSS VSS_NCTF
AJ31 VSS VSS T29 D6 VSS
AJ23 VSS VSS T28 D3 VSS
A35,AT1,AT35,B1,A3,A33,A34,
AJ20 T27 C34 A35 TP_MCP_VSS_NCTF2 1 TP1402
AP1,AP35,AR1,AR35,AT2,AT3,
VSS VSS VSS VSS_NCTF#A35 TP_MCP_VSS_NCTF3 TP1406
AJ17 VSS VSS T26 C32 VSS VSS_NCTF#AT1 AT1 1
AJ14 T6 C29 AT35 TP_MCP_VSS_NCTF4 1 TP1405
VSS VSS VSS VSS_NCTF#AT35 TP_MCP_VSS_NCTF1 TP1401
AJ11 VSS VSS R10 C28 VSS VSS_NCTF#B1 B1 1
AJ8 P8 C24 A3
AT33,AT34,C1,C35,B35
VSS VSS VSS RSVD_NCTF#A3
AJ5 VSS VSS P4 C22 VSS RSVD_NCTF#A33 A33
AJ2 VSS VSS P2 C20 VSS RSVD_NCTF#A34 A34
AH35 VSS VSS N35 C19 VSS RSVD_NCTF#AP1 AP1
AH34 VSS VSS N34 C16 VSS RSVD_NCTF#AP35 AP35
NCYF TEST PIN:

AH33 VSS VSS N33 B31 VSS RSVD_NCTF#AR1 AR1
AH32 VSS VSS N32 B25 VSS RSVD_NCTF#AR35 AR35
AH31 VSS VSS N31 B21 VSS RSVD_NCTF#AT2 AT2
B B
AH27 VSS VSS N27 B11 VSS RSVD_NCTF#C1 C1
AH26 VSS VSS N26 B8 VSS RSVD_NCTF#C35 C35
AH20 VSS VSS N6 B6 VSS RSVD_NCTF#B35 B35
AH17 VSS VSS M10 B4 VSS
AH13
AH9
VSS VSS L35
L32
A29
A27
VSS For layout request
VSS VSS VSS
AH6 VSS VSS L29 A23 VSS
AH3 VSS VSS L8 A9 VSS
AG10 VSS VSS L5
AF8 VSS VSS L2
AF4 VSS VSS K34
AF2 VSS VSS K33
AE35 VSS VSS K30
CLARKUNF CLARKUNF
A 1st Samsung A
Wistron Corporation
Title
CPU (VSS)
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
14 of 88
A00
5 4 3 2 1
D D
C C
(Blanking)
B B
A 1st Samsung A
Wistron Corporation
Title
Reserved
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A 1st Samsung A
Wistron Corporation
Title
Reserved
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
DM1
D SSID = MEMORY M_A_A0

M_A_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
D
M_A_A2 96
M_A_A3 A2
95 A3 RAS# 110 M_A_RAS# [10]
M_A_A4 92 113 M_A_WE# [10]
M_A_A5 A4 WE#
91 115 M_A_CAS# [10]
M_A_A6 A5 CAS#
90 A6
M_A_A7 86 114 M_CS0# [10]
M_A_A8 A7 CS0#
[10] M_A_DQS#[7..0] 89 A8 CS1# 121 M_CS1# [10]
M_A_A9 85
M_A_A10 A9
[10] M_A_DQ[63..0] 107 73 M_CKE0 [10]
M_A_A11 A10/AP CKE0
84 74 M_CKE1 [10]
M_A_A12 A11 CKE1
[10] M_A_DM[7..0] 83
M_A_A13 A12 M_CLK_DDR0
119 101 M_CLK_DDR0 [10]
M_A_A14 A13 CK0 M_CLK_DDR#0 SA0_DM1
[10] M_A_DQS[7..0] 80 103 M_CLK_DDR#0 [10]
M_A_A15 A14 CK0# SA1_DM1
78 A15
M_A_BS2 79 102 M_CLK_DDR1 M_CLK_DDR1 [10]
[10] M_A_A[15..0] [10] M_A_BS2 A16/BA2 CK1
104 M_CLK_DDR#1 M_CLK_DDR#1 [10]
CK1#
1
M_A_BS0 109
[10] M_A_BS0 M_A_BS1 BA0 M_A_DM0 R1802 R1801
[10] M_A_BS1
108 BA1 DM0 11
28 M_A_DM1 10KR2J-3-GP 10KR2J-3-GP
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
2
15 136
17 153
4 170
M_A_DQ6
6
16
DQ5
DQ6
DM7
187
SMBUS address:A0
M_A_DQ7 18 200 PCH_SMBDATA
DQ7 SDA PCH_SMBDATA [7,19,23,40,64,76]
M_A_DQ8 PCH_SMBCLK
M_A_DQ9
21
23
DQ8 SCL
202 PCH_SMBCLK [7,19,23,40,64,76] DW
M_A_DQ10 DQ9 07/02 Reserve
33 DQ10 EVENT# 198 PM_EXTTS#0 [9]
M_A_DQ11 35 +3.3V_RUN 1.Added SA0_DM1 pull-up resistor
M_A_DQ12 DQ11 07/07
Layout Note: 22
DQ12 VDDSPD
199 2.Reserve pull-hi,lo resistor
M_A_DQ13 24
+1.5V_SUS Place near DM1 M_A_DQ14 34
DQ13
197 SA0_DM1
DQ14 SA0
1
M_A_DQ15 36 201 SA1_DM1 C1806 C1807
M_A_DQ16 DQ15 SA1 SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP
39
C
ST330U2D5VBM-1-GP M_A_DQ17 DQ16 DY C
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
41 77
2
DQ17 NC#1
1
1
C1802
C1803
C1804
C1811
C1812
C1816
M_A_DQ18 51 122
1 DQ18 NC#2 +1.5V_SUS
TC1803
M_A_DQ19 53 125
M_A_DQ20 DQ19 NC#/TEST
40
DY
2
M_A_DQ21 DQ20
42 75
2
M_A_DQ22 DQ21 VDD1

50 DQ22 VDD2 76
M_A_DQ23 52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
67 88
M_A_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
M_A_DQ28 56 94
M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ30 DQ29 VDD9
68 100
M_A_DQ31 DQ30 VDD10
70 105
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111
DQ33 VDD13
Height 5.2mm
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD14
143 117
M_A_DQ36 DQ35 VDD15
Layout Note: Layout Note: 130
DQ36 VDD16
118
M_A_DQ37 132 123
Put close to VTT1,VTT2. Put between two SO-DIMM M_A_DQ38 140
DQ37 VDD17
124
+0.75V_DDR_VTT M_A_DQ39 DQ38 VDD18
142 DQ39
M_A_DQ40 147 2
DQ40 VSS
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQ41 149 3
DQ41 VSS
SC10U6D3V5MX-3GP
M_A_DQ42 157 8
DQ42 VSS
1
1
C1801
C1813
C1814
C1815
M_A_DQ43 159 9
DQ43 VSS
C1823
M_A_DQ44 146 13
DY DY DY M_A_DQ45 148
DQ44 VSS
14
2
M_A_DQ46 DQ45 VSS

158
DQ46 VSS
19 put near connector
M_A_DQ47 160 20
M_A_DQ48 DQ47 VSS M_CLK_DDR0
163 25
M_A_DQ49 DQ48 VSS M_CLK_DDR#0
165 26
M_A_DQ50 DQ49 VSS M_CLK_DDR1
175 31
M_A_DQ51 DQ50 VSS M_CLK_DDR#1
DG: 177
DQ51 VSS
32
M_A_DQ52 164 37
B 1uF*4 (per SO-DIMM) M_A_DQ53 166
DQ52 VSS
38 B
M_A_DQ54 DQ53 VSS
10uF*3 (two close to VR and one between the two SO-DIMM) 174
DQ54 VSS
43
M_A_DQ55 176 44
DQ55 VSS
1
M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
DUMMY-C2
DUMMY-C2
DUMMY-C2
DUMMY-C2
183 49
DQ57 VSS
C1821
C1819
C1820
C1818
M_A_DQ58 191 54
M_A_DQ59 DQ58 VSS
193 55
M_A_DQ60 DQ59 VSS
180 60
+1.5V_SUS M_A_DQ61 DQ60 VSS
182 61
2
M_A_DQ62 DQ61 VSS
192 65
M_A_DQ63 DQ62 VSS
194 66
DQ63 VSS
VSS 71
M_A_DQS#0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10 DQS0# VSS 72
M_A_DQS#1
SCD1U10V2KX-4GP
27 DQS1# VSS 127

1
M_A_DQS#2 45 128
DQS2# VSS
C1872
C1873
C1874
C1875
M_A_DQS#3 62 133
M_A_DQS#4 DQS3# VSS
135 134
2
M_A_DQS#5 DQS4# VSS

152 138
M_A_DQS#6 DQS5# VSS
169 139
M_A_DQS#7 DQS6# VSS
186 144
DQS7# VSS
145
M_A_DQS0 VSS
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_A_DQS1
12
DQS0 VSS
150
29 151
pdf" document. M_A_DQS2 DQS1 VSS
47 155
M_A_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_A_DQS4 137 161
M_A_DQS5 DQS4 VSS
154 162
M_A_DQS6 DQS5 VSS
171 167
M_A_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
M_ODT0 VSS
[10] M_ODT0 116 173
+V_DDR_REF M_ODT1 ODT0 VSS
[10] M_ODT1 120 178
ODT1 VSS
179
VSS
126 184
VREF_CA VSS
1 185
VREF_DQ VSS
1
C1810 C1817 C1809 189

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP VSS
30 190
A DY +0.75V_DDR_VTT [9,19] DDR3_DRAMRST# RESET# VSS
195 A
2
VSS
VSS 196
203 VTT1 VSS 205
204 VTT2 VSS 206
1st Samsung
DDR3-204P-25-GP
Wistron Corporation
Title
www.vinafix.vn Size Document Number

DDRIII-SODIMM SLOT1 Rev
Custom A00
Winery13 MB DIS
5 4 3 2 1
5 4 3 2 1
DM2
Change CONN
SSID = MEMORY M_B_A0
M_B_A1
98
97
A0
A1
NP1
NP2
NP1
NP2
2009/06/01
M_B_A2 96
M_B_A3 A2
95 110 M_B_RAS# [10]
M_B_A4 A3 RAS#
92 113 M_B_WE# [10]
M_B_A5 A4 WE#
91 115 M_B_CAS# [10]
M_B_A6 A5 CAS# +3.3V_RUN +3.3V_RUN
90
M_B_A7 A6
86 114 M_CS2# [10]
A7 CS0#
1
M_B_A8 89 121 M_CS3# [10]
A8 CS1#
1
M_B_A9 EC1901
D
[10] M_B_DQS#[7..0]
M_B_A10
85
107
A9
73 M_CKE2 [10] R1903 R1904
DY SCD1U25V3KX-GP D
2
M_B_A11 A10/AP CKE0 10KR2J-3-GP 10KR2J-3-GP
[10] M_B_DQ[63..0]
M_B_A12
84
A11 CKE1
74 M_CKE3 [10] DY
83
M_B_A13 A12 M_CLK_DDR2
[10] M_B_DM[7..0] 119 101 M_CLK_DDR2 [10]
2
M_B_A14 A13 CK0 M_CLK_DDR#2 SA1_DM2
80 103 M_CLK_DDR#2 [10]
M_B_A15 A14 CK0# SA0_DM2
[10] M_B_DQS[7..0] 78
M_B_BS2 A15 M_CLK_DDR3
[10] M_B_BS2 79 102 M_CLK_DDR3 [10]
A16/BA2 CK1 M_CLK_DDR#3
[10] M_B_A[15..0] 104 M_CLK_DDR#3 [10]
CK1#
1
M_B_BS0 109
[10] M_B_BS0 M_B_BS1 BA0 M_B_DM0 R1901 R1902
[10] M_B_BS1 108 11
BA1 DM0 M_B_DM1 10KR2J-3-GP
M_B_DQ0 DM1
28
M_B_DM2
DY 10KR2J-3-GP
5 46
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
2
15 136
17 153
4 170
6 187
M_B_DQ6 DQ5 DM7
M_B_DQ7
16
18
DQ6
DQ7 SDA
200 PCH_SMBDATA
PCH_SMBDATA [7,18,23,40,64,76]
SMBUS address:A4
M_B_DQ8 21 202 PCH_SMBCLK
DQ8 SCL PCH_SMBCLK [7,18,23,40,64,76]
Layout Note: M_B_DQ9 23
M_B_DQ10 DQ9 +3.3V_RUN
Place near DM2 33 198 PM_EXTTS#1 [9]
+1.5V_SUS M_B_DQ11 DQ10 EVENT#
35
M_B_DQ12 DQ11
22 199
M_B_DQ13 DQ12 VDDSPD
24
M_B_DQ14 DQ13 SA0_DM2
SC10U6D3V5MX-3GP
ST330U2D5VBM-1-GP
34 197
DQ14 SA0
1
M_B_DQ15 36 201 SA1_DM2 C1906 C1921
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
1
DQ15 SA1
C1905
C1911
C1913
C1919
C1920
M_B_DQ16 SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP
39
DQ16 DY
C1916
TC1903
M_B_DQ17
DY 41 77
2
M_B_DQ18 DQ17 NC#1
51 122
2
2
M_B_DQ19 DQ18 NC#2 +1.5V_SUS
53
DQ19 NC#/TEST
125 Note:
M_B_DQ20 40
M_B_DQ21 42
DQ20
75
If SA0_DIM0 = 0, SA1_DIM0 = 0
M_B_DQ22 DQ21 VDD1 SO-DIMMA SPD Address is 0xA0
C 50 76 C
M_B_DQ23 DQ22 VDD2
52
DQ23 VDD3
81 If SA0_DIM0 = 1, SA1_DIM0 = 0
M_B_DQ24 57 82
M_B_DQ25 59
DQ24 VDD4
87
SO-DIMMA SPD Address is 0xA2
M_B_DQ26 DQ25 VDD5 If SA0_DIM0 = 0, SA1_DIM0 = 1
67 88
M_B_DQ27 DQ26 VDD6
69 93 SO-DIMMA SPD Address is 0xA4
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
Layout Note: 130
DQ36 VDD16
118
M_B_DQ37 132 123
+0.75V_DDR_VTT Put close to VTT1,VTT2. M_B_DQ38 DQ37 VDD17
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
147 2
DQ40 VSS
Height 9.2mm
M_B_DQ41 149 3
DQ41 VSS
1
1
C1908
C1917
C1918
C1909
M_B_DQ42 157 8 put near connector

M_B_DQ43 DQ42 VSS
DY DY M_B_DQ44
159
146
DQ43 VSS
9
13 M_CLK_DDR2
2
M_B_DQ45 DQ44 VSS M_CLK_DDR#2

148 14
M_B_DQ46 DQ45 VSS M_CLK_DDR3
158 19
M_B_DQ47 DQ46 VSS M_CLK_DDR#3
160 20
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS
DG: 177
DQ51 VSS
32
1
M_B_DQ52 164 37
1uF*4 (per SO-DIMM) M_B_DQ53 166
DQ52 VSS
38
DUMMY-C2
DUMMY-C2
DUMMY-C2
DUMMY-C2
DQ53 VSS
10uF*3 (two close to VR and one between the two SO-DIMM)
C1901
C1904
C1902
C1903
M_B_DQ54 174 43
M_B_DQ55 DQ54 VSS
B 176 44 B
M_B_DQ56 DQ55 VSS
181 48
M_B_DQ57 DQ56 VSS
183 49
2
M_B_DQ58 DQ57 VSS
191 54
M_B_DQ59 DQ58 VSS
193 55
M_B_DQ60 DQ59 VSS
180 60
M_B_DQ61 DQ60 VSS
182 61
M_B_DQ62 DQ61 VSS
192 65
M_B_DQ63 DQ62 VSS
194 66
DQ63 VSS
71
+1.5V_SUS M_B_DQS#0 VSS
10 72
M_B_DQS#1 DQS0# VSS
27 127
M_B_DQS#2 DQS1# VSS
45 128
M_B_DQS#3 DQS2# VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
62 133
M_B_DQS#4 DQS3# VSS
135 134
DQS4# VSS
1
M_B_DQS#5 152 138

DQS5# VSS
C1976
C1977
C1978
C1979
M_B_DQS#6 169 139

M_B_DQS#7 DQS6# VSS
186 144
2
DQS7# VSS
145
M_B_DQS0 VSS
12 150
M_B_DQS1 DQS0 VSS
29 151
M_B_DQS2 DQS1 VSS
47 155
M_B_DQS3 DQS2 VSS
64 156
M_B_DQS4 DQS3 VSS
Follow Intel "425302_Calpella_S3PowerReduction_WhitePaper_Rev0.9. M_B_DQS5
137
DQS4 VSS
161
154 162
pdf" document. M_B_DQS6 DQS5 VSS
171 167
M_B_DQS7 DQS6 VSS
188 168
DQS7 VSS
172
M_ODT2 VSS
[10] M_ODT2 116 173
+V_DDR_REF M_ODT3 ODT0 VSS
[10] M_ODT3 120 178
ODT1 VSS
179
VSS
126 184
VREF_CA VSS
1 185
VREF_DQ VSS
A 189 A
1
C1907 C1910 C1914 VSS

[9,18] DDR3_DRAMRST# 30 190
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP RESET# VSS
DY +0.75V_DDR_VTT VSS
195
196
1st Samsung
2
VSS
203 205
VTT1 VSS
204
VTT2 VSS
206
Wistron Corporation
DDR3-204P-24-GP
Title
DDRIII-SODIMM SLOT2
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
DW
07/05 LCDVDD_EN_PCH 1
SSID = PCH 1. LCD brightness control are separated by GPU,PCH,EC DY 2
2. LCD Power Enable control are separated by GPU,PCH,EC
A00-0104-1 R2003
3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
07/07 100KR2J-1-GP
4. Dummy R2003
R2011
0R0402-PAD-2-GP U2001D 4 OF 10
[37] PANEL_BKEN_PCH 1 2PANEL_BKEN_PCHR
T48 L_BKLTEN SDVO_TVCLKINN BJ46
[54] LCDVDD_EN_PCH LCDVDD_EN_PCH T47 L_VDD_EN BG46
SDVO_TVCLKINP
D D
[54] LBKLT_CTL_PCH Y48 L_BKLTCTL SDVO_STALLN BJ48
SDVO_STALLP BG48
[54] L_DDC_CLK AB48 L_DDC_CLK
[54] L_DDC_DATA Y45 L_DDC_DATA SDVO_INTN BF45
RN2001 BH45
LCTLA_CLK SDVO_INTP
+3.3V_RUN 1 4 AB46 L_CTRL_CLK
2 3 LCTLB_DATA V48 L_CTRL_DATA
SRN10KJ-5-GP LIBG AP39 T51
TPAD14-GP TP2001 TP_LVDS_VBG AP41 LVD_IBG SDVO_CTRLCLK
1 LVD_VBG SDVO_CTRLDATA T53
Place near PCH
1
AT43 LVD_VREFH
R2002 AT42 BG44
2K37R2F-GP LVD_VREFL DDPB_AUXN
DDPB_AUXP BJ44
DDPB_HPD AU38
LVDS
[74] MCH_LVDSA_CLK# AV53
2
LVDSA_CLK#
[74] MCH_LVDSA_CLK AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
[74] MCH_LVDSA_DAT0# BB47 LVDSA_DATA#0 DDPB_1N BJ42
[74] MCH_LVDSA_DAT1# BA52 BG42
Digital Display Interface

LVDSA_DATA#1 DDPB_1P
[74] MCH_LVDSA_DAT2# AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
[74] MCH_LVDSA_DAT0 BB48 LVDSA_DATA0 DDPB_3P BA38
[74] MCH_LVDSA_DAT1 BA50 LVDSA_DATA1
[74] MCH_LVDSA_DAT2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49
C C
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
37.5 ohm trace to 150R resistor AT51 BB36
LVDSB_DATA3 DDPC_3N
DDPC_3P BA36
50 ohm trace to filter
[74] MCH_BLUE MCH_BLUE AA52 U50

MCH_GREEN CRT_BLUE DDPD_CTRLCLK
[74] MCH_GREEN AB53 CRT_GREEN DDPD_CTRLDATA U52
[74] MCH_RED MCH_RED AD53 CRT_RED
DDPD_AUXN BC46
2
[55] GMCH_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46

R2007 R2006 R2005 [55] GMCH_DDCDATA V53 AT38
150R2F-1-GP CRT_DDC_DATA DDPD_HPD
150R2F-1-GP 150R2F-1-GP
DDPD_0N BJ40
[74] GMCH_HSYNC Y53 BG40
1
CRT_HSYNC DDPD_0P
[74] GMCH_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38
CRT
DDPD_2N BF37
B B
Place near PCH 1 2 CRT_IREF AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
R2004 BD36
1KR2J-1-GP DDPD_3P
IBEXPEAK-M-GP-NF
SB-1023
change R2004 from 0.5% to 5%.
A 1st Samsung A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
20 of 88
A00
5 4 3 2 1
RN2101
DW
PCI_DEVSEL# 1 10 07/02 Added U2001E 5 OF 10
+3.3V_RUN 1. using the single buffers for 4 device with
PCI_IRDY# 2 9 DGPU_SELECT# H40 AY9
PCI_SERR# INT_PIRQD# equivalent capability. AD0 NV_CE#0
3 8 N34 BD1
+3.3V_RUN
INT_PIRQC# 4
5
7
6
PCI_STOP#
INT_PIRQA#
2.Rename PCI_PLTRST#
C44
A38
AD1
AD2
AD3
NV_CE#1
NV_CE#2
NV_CE#3
AP15
BD8
SSID = PCH
+3.3V_RUN C36
SRN8K2J-2-GP-U AD4
J34 AD5 NV_DQS0 AV9
A40 AD6 NV_DQS1 BG8
D45 AD7
1
C2101 E36 AP7
RN2102 SCD1U10V2KX-4GP U2101 AD8 NV_DQ0/NV_IO0
H48 AD9 NV_DQ1/NV_IO1 AP6
PCI_PERR# 1 10 +3.3V_RUN 1 E40 AT6
2
PCI_REQ0# INT_PIRQB# B AD10 NV_DQ2/NV_IO2
D 2 9 5 VCC C40 AD11 NV_DQ3/NV_IO3 AT9 D
PCI_REQ3# 3 8 PCI_PLOCK# 2 PLTRST#_PCH M48 BB1
A AD12 NV_DQ4/NV_IO4
PCI_FRAME# PCI_REQ1# DMI Termination Voltage
+3.3V_RUN
4
5
7
6 PCI_TRDY#
[9,34,36,37,64,70,76,80] PLT_RST# 4 Y DY 3
M45
F53
AD13 NV_DQ5/NV_IO5 AV6
BB3
GND AD14 NV_DQ6/NV_IO6
M40 BA4 NV_CLE Set to Vss when low.
SRN8K2J-2-GP-U 74LVC1G08GW -1-GP AD15 NV_DQ7/NV_IO7
NVRAM
M43 AD16 NV_DQ8/NV_IO8 BE4 Set to Vcc when high.
SB-1022 J36 AD17 NV_DQ9/NV_IO9 BB6 Low = Default
1 2 K48 BD6
+3.3V_RUN DY U2101; POP R2104 R2104 0R2J-2-GP F40
AD18 NV_DQ10/NV_IO10
BB7
AD19 NV_DQ11/NV_IO11
C42 AD20 NV_DQ12/NV_IO12 BC8 unused NV_SLE strap
1 8 DGPU_PW M_SELECT# K46 BJ8
EDID_SELECT_R# AD21 NV_DQ13/NV_IO13
2 7 M51 AD22 NV_DQ14/NV_IO14 BJ6
3 6 PCH_GPIO4 J52 BG6
INT_PIRQE# AD23 NV_DQ15/NV_IO15
4 5 K51 AD24
L34 BD3 TP_NV_ALE 1 TP2124 TPAD14-GP
AD25 NV_ALE TP_NV_CLE TP2125 TPAD14-GP
F42 AD26 NV_CLE AY6 1
RN2103 J40
SRN10KJ-7GP AD27
G46 AD28
F44 AU2 TP_NV_RCOMP1 TP2130 TPAD14-GP
AD29 NV_RCOMP
M47 AD30
PCI
H36 AD31 NV_RB# AV7
+3.3V_RUN
SB-1022 J50 C/BE0# NV_WR#0_RE# AY8
G42 AY5
DY U2102; POP R2105 H47
C/BE1# NV_WR#1_RE#
C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
NV_WE#_CK1 BF5
U2102 INT_PIRQA# G38 PIRQA# Port 0 for debug port
1 INT_PIRQB# H51
C B INT_PIRQC# PIRQB# C
5 VCC B37 PIRQC# USBP0N H18 USB_PN0 [63]
2 EDID_SELECT_R# INT_PIRQD# A44 J18
A PIRQD# USBP0P USB_PP0 [63]
[54,55] EDID_SELECT# 4 Y DY USBP1N A18 USB_PN1 [63] USB
3 PCI_REQ0# F51 C18
GND REQ0# USBP1P USB_PP1 [63]
PCI_REQ1# A46 REQ1#/GPIO50 USBP2N N20 USB_PN2 [76] Pair Device
74LVC1G08GW -1-GP [37,54,74] DGPU_SELECT# DGPU_SELECT# B45 P20
REQ2#/GPIO52 USBP2P USB_PP2 [76]
PCI_REQ3# M53 REQ3#/GPIO54 USBP3N J20 TP_USB_PN3
TP2122 0 USB1
1 2 L20 TP_USB_PP3
USBP3P TP2123
R2105 0R2J-2-GP TPAD14-GP TP2116
TPAD14-GPTP2116 1 PCI_GNT0# F48 GNT0# USBP4N F20 USB_PN4 [64] 1 USB for ESATA
1
K45 GNT1#/GPIO51 USBP4P G20 USB_PP4 [64]

DY C2112 [54] DGPU_PW M_SELECT# DGPU_PW M_SELECT# F36 GNT2#/GPIO53 USBP5N A20 USB_PN5 [76] 2 USB2
SC220P50V2KX-3GP R2121 PCI_GNT3# H53 C20 USB_PP5 [76]
2
GNT3#/GPIO55 USBP5P
0R2J-2-GP
USBP6N M22 TP_USB_PN6
TP2118 3 RESERVE
[40] HDD_FALL_INT1 1 2 INT_PIRQE# B41 PIRQE#/GPIO2 USBP6P N22 TP_USB_PP6
TP2119
[76] W W AN_RF_EN W W AN_RF_EN K53 PIRQF#/GPIO3 USBP7N B21 TP_USB_PN7
TP2120 4 WLAN
PCH_GPIO4 A36 D21 TP_USB_PP7
PIRQG#/GPIO4 USBP7P TP2121
EDID_SELECT_R# A48 PIRQH#/GPIO5 USBP8N H22 USB_PN8 [73] 5 WWAN
BOOT BIOS Strap USBP8P J22 USB_PP8 [73]
USB
TPAD14-GP TP2108
TPAD14-GPTP2108 1 PCIRST# K6 PCIRST# USBP9N E22 USB_PN9 [32] 6 RESERVED
PCI_GNT#0 PCI_GNT#1 BOOT BIOS Location F22 USB_PP9 [32]
USBP9P
PCI_SERR# E44 SERR# USBP10N A22 USB_PN10 [78] 7 RESERVED
0 0 LPC PCI_PERR# E50 PERR# USBP10P C22 USB_PP10 [78]
USBP11N G24 USB_PN11 [73] 8 BlUETOOTH
0 1 Reserved USBP11P H24 USB_PP11 [73]
PCI_IRDY# A42 IRDY# USBP12N L24 USB_PN12 [34] 9 Card Reader
1 0 PCI H44 PAR USBP12P M24 USB_PP12 [34]
PCI_DEVSEL# F46 DEVSEL# USBP13N A24 TP_USB_PN13
TP2128 10 Biometric
1 1 SPI(Default) PCI_FRAME# C46 FRAME# USBP13P C24 TP_USB_PP13
TP2129
B
11 CAMERA B
PCI_PLOCK# D49 PLOCK#
USBRBIAS# B25 USB_RBIAS_PN 1 2 12 New Card
PCI_STOP# D41 STOP#
PCI_TRDY# C48 TRDY# USBRBIAS D25 R2106 13 RESERVED
22D6R2F-L1-GP
TPAD14-GP TP2115
TPAD14-GPTP2115 1 PCH_PME# M7 PME# USB_OC#0_1
OC0#/GPIO59 N16 USB_OC#0_1 [22,63]
PLTRST#_PCH D5 J16 USB_OC#2_3 USB_OC#2_3 [76]
PLTRST# OC1#/GPIO40 USB_OC#4_5
OC2#/GPIO41 F16
[70] PCLK_FW H R2110 1 DY 2 22R2J-2-GP PCLK_FW H_R N52 L16 USB_OC#6_7
R2108 1 22R2J-2-GP CLK_PCI_FB_R CLKOUT_PCI0 OC3#/GPIO42 USB_OC#8_9
[23] CLK_PCI_FB 2 P53 CLKOUT_PCI1 OC4#/GPIO43 E14 Pull up in page 22
[37] PCLK_KBC R2111 1 2 22R2J-2-GP PCLK_KBC_R P46 G16 USB_OC#10_11
R2112 1 22R2J-2-GP PCLK_TPM_R CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13 for layout convenience
[36] PCLK_TPM DY 2 P51 CLKOUT_PCI3 OC6#/GPIO10 F12
PCH_OC7#
USB_OC#12_13 [23]
P48 CLKOUT_PCI4 OC7#/GPIO14 T15 SB
swap net for layout
IBEXPEAK-M-GP-NF
Calpella Platform Design Guide
A16 swap override Strap/Top-Block Pull up in page 23 for layout convenience
Swap Override jumper Revision 1.6
Table 111. Overcurrent Pin Example Configuration Page 233
PCI_GNT#3 Low = A16 swap
override/Top-Block These OC7# pins are not used for USB overcurrent protection and should be configured as GPIOs.
Swap Override enabled The unused USB ports can be left as no connect.
High = Default
A RP2101 1st Samsung A

PCH_OC7# 1 10 +3.3V_ALW
USB_OC#2_3 2 9 PM_RI# PM_RI# [22]
USB_OC#6_7 USB_OC#8_9
R2109 USB_OC#4_5
3
4
8
7 PEG_B_CLKRQ# PEG_B_CLKRQ# [23]
Wistron Corporation
PCI_GNT3# USB_OC#10_11 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1
DY 2 +3.3V_ALW 5 6
4K7R2J-2-GP SRN10KJ-L3-GP
Title
SB PCH (PCI/USB/NVRAM)
swap net for layout Size Document Number Rev
5 4
www.vinafix.vn 3 2
Date:
Winery13 MB DIS
W ednesday, January 13, 2010 Sheet
1
21 of 88
A00
5 4 3 2 1
SSID = PCH U2001C 3 OF 10

FDI_RXN0 BA18 FDI_TXN0 FDI_TXN0 [8]
BC24 BH17 FDI_TXN1 +3.3V_ALW
[8] DMI_CTX_PRXN0 DMI0RXN FDI_RXN1 FDI_TXN1 [8]
[8] DMI_CTX_PRXN1 BJ22 BD16 FDI_TXN2 FDI_TXN2 [8]
DMI1RXN FDI_RXN2 FDI_TXN3 RN2201
[8] DMI_CTX_PRXN2 AW20 DMI2RXN FDI_RXN3 BJ16 FDI_TXN3 [8]
[8] DMI_CTX_PRXN3 BJ20 BA16 FDI_TXN4 FDI_TXN4 [8] [21,63] USB_OC#0_1 USB_OC#0_1 3 2
DMI3RXN FDI_RXN4 FDI_TXN5 SUS_PW R_ACK
FDI_RXN5 BE14 FDI_TXN5 [8] 4 1
[8] DMI_CTX_PRXP0 BD24 BA14 FDI_TXN6 FDI_TXN6 [8]
DMI0RXP FDI_RXN6 FDI_TXN7 SRN10KJ-5-GP
[8] DMI_CTX_PRXP1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_TXN7 [8]
D [8] DMI_CTX_PRXP2 BA20 DMI2RXP D
[8] DMI_CTX_PRXP3 BG20 BB18 FDI_TXP0 FDI_TXP0 [8] PM_BATLOW #_R 1 2
DMI3RXP FDI_RXP0 FDI_TXP1 R2201 10KR2J-3-GP
FDI_RXP1 BF17 FDI_TXP1 [8]
[8] DMI_PTX_CRXN0 BE22 BC16 FDI_TXP2 FDI_TXP2 [8] PCIE_W AKE# 1 2
DMI0TXN FDI_RXP2 FDI_TXP3 R2202 1KR2J-1-GP
[8] DMI_PTX_CRXN1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_TXP3 [8]
[8] DMI_PTX_CRXN2 BD20 AW16 FDI_TXP4 FDI_TXP4 [8] AC_PRESENT_EC 1 2
DMI2TXN FDI_RXP4 FDI_TXP5 R2217 10KR2J-3-GP
[8] DMI_PTX_CRXN3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_TXP5 [8]
BB14 FDI_TXP6 FDI_TXP6 [8]
FDI_RXP6
[8] DMI_PTX_CRXP0 BD22 DMI0TXP FDI_RXP7 BD12 FDI_TXP7 FDI_TXP7 [8] Option to " Disable " clkrun.
[8] DMI_PTX_CRXP1 BH21
BC20
DMI1TXP Pulling it down will keep the clks running.
[8] DMI_PTX_CRXP2 DMI2TXP
[8] DMI_PTX_CRXP3 BD18 BJ14 FDI_INT FDI_INT [8]
DMI3TXP FDI_INT +3.3V_RUN
DMI
FDI
+1.05V_VTT BF13 FDI_FSYNC0
FDI_FSYNC0 FDI_FSYNC0 [8]
BH25 DMI_ZCOMP
R2204 BH13 FDI_FSYNC1 FDI_FSYNC1 [8]
FDI_FSYNC1
2
1 2 DMI_IRCOMP_R BF25 DMI_IRCOMP FDI_LSYNC0 R2214
FDI_LSYNC0 BJ12 FDI_LSYNC0 [8]
49D9R2F-GP 10KR2J-3-GP
+3.3V_RUN BG14 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 [8]
1
1
PM_CLKRUN#
R2205
Remove XDP 10KR2J-3-GP
1
pull-up ? R2215
[9] XDP_DBRESET# 2 XDP_DBRESET# T6 J12 PCIE_W AKE# [34,76] 10KR2J-3-GP
DY
SYS_RESET# WAKE#
C C
2
M6 Y1 PM_CLKRUN#
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# [37]
A00-0104-1
System Power Management

[37] PM_PW ROK R2207 1 2 0R0402-PAD-2-GP PM_PW RGD B17 PWROK
R2208 1 2 10KR2J-3-GP
TP_SUS_STAT# 1
K5 MEPWROK SUS_STAT#/GPIO61 P8
TP2205TPAD14-GP
Close to PCH
R2209 1 2 10KR2J-3-GP LAN_RST#1 A10 F3 PCH_SUSCLK 1 2 PCH_SUSCLK_2102 [39]
LAN_RST# SUSCLK/GPIO62 R2219 0R0402-PAD-2-GP
A00-0104-1
[9] PM_DRAM_PW RGD PM_DRAM_PW RGD D9 E4 PCH_SLP_S5# 1 1 2 PCH_SUSCLK_KBC [37]
DRAMPWROK SLP_S5#/GPIO63 TP2202TPAD14-GP R2220 0R0402-PAD-2-GP
[37] RSMRST#_KBC 1 2 PM_RSMRST#_R C16 H7 PM_SLP_S4#_R 1 2 PM_SLP_S4# [34,37,50]

R2210 0R2J-2-GP RSMRST# SLP_S4# R2211 0R0402-PAD-2-GP
A00-0104-1
[37] SUS_PW R_DN_ACK 1 2 SUS_PW R_ACK M1 P12 PM_SLP_S3#_R 1 2 PM_SLP_S3# [34,37,42,50,51,86]
R2218 0R0402-PAD-2-GP SUS_PWR_DN_ACK/GPIO30 SLP_S3# R2212 0R0402-PAD-2-GP
A00-0104-1
[37] PM_PW RBTN# 1 2 PM_PW RBTN#_R P5 K8 SIO_SLP_M#_R 1
R2213 0R0402-PAD-2-GP PWRBTN# SLP_M# TP2203TPAD14-GP
[37] AC_PRESENT_EC AC_PRESENT_EC 1 2 AC_PRESENT P7 N2 PM_SLP_DSW # 1

R2216 0R0402-PAD-2-GP ACPRESENT/GPIO31 TP23 TP2204TPAD14-GP
PM_BATLOW #_R A6 BJ10 H_PM_SYNC

B BATLOW#/GPIO72 PMSYNCH H_PM_SYNC [9] B
[21] PM_RI# PM_RI# F14 F6

RI# SLP_LAN#/GPIO29
IBEXPEAK-M-GP-NF
Pull up in page 23 for layout convenience
KBC_PW R
2
R2221
SB-31
DY10KR2J-3-GP
1
U2213
4 3 PM_RSMRST#_R
U2213_56
5 2
DY 3V_5V_POK [37,46]
6 1
DMN66D0LDW -7-GP
A 1st Samsung A
R2203 Wistron Corporation

PM_RSMRST#_R 1 2 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
10KR2J-3-GP
Title
PCH (DM I/FDI/PM)

5 4
www.vinafix.vn 3 2
Date:
Winery13 MB DIS
W ednesday, January 13, 2010 Sheet
1
22 of 88
A00
5 4 3 2 1
+3.3V_ALW
RN2301
SML0ALERT# 1 4
SML1ALERT# 2 3 SB-1020
SSID = PCH SRN10KJ-5-GP
+3.3V_ALW
+3.3V_ALW
U2001B 2 OF 10
2
1
BG30 B9 SMBALERT# 2 1 +3.3V_ALW
PERN1 SMBALERT#/GPIO11
1
2
BJ30 R2301 10KR2J-3-GP RN2302
PERP1 PCH_SMB_CLK RN2313 SRN2K2J-1-GP
BF29 PETN1 SMBCLK H14 PCH_SMB_CLK [34]
BH29 PETP1 SRN2K2J-1-GP
C8 PCH_SMB_DATA
SMBDATA PCH_SMB_DATA [34]
D [64] PCIE_IRXN2_MTXN2 AW30 D
3
4
PERN2
[64] PCIE_IRXP2_MTXP2 BA30
4
3
C2318 PCIE_ITXN2_MRXN2_C BC30 PERP2 SML0ALERT#
[64] PCIE_ITXN2_MRXN2 2 1 SCD1U10V2KX-5GP PETN2 WLAN SML0ALERT#/GPIO60 J14
[64] PCIE_ITXP2_MRXP2 C2310 2 1 SCD1U10V2KX-5GP PCIE_ITXP2_MRXP2_C BD30 PCH_SMB_CLK
PETP2 SML0_CLK
AU30
SML0CLK C6 Remove XDP PCH_SMB_DATA
SMBus
[76] PCIE_IRXN3_LRTXN3 PERN3
[76] PCIE_IRXP3_LRTXP3
C2303
AT30
PCIE_ITXN3_LRXN3_C AU32 PERP3 SML0DATA G8 SML0_DATA pull-up
[76] PCIE_ITXN3_LRXN3 2 1 SCD1U10V2KX-5GP PETN3 LAN
[76] PCIE_ITXP3_LRXP3 C2309 2 1 SCD1U10V2KX-5GP PCIE_ITXP3_LRXP3_C AV32
PETP3 SML1ALERT#
SML1ALERT#/GPIO74 M14
[76] PCIE_IRXN4_MTXN4 BA32 PERN4 KBC_SCL1
[76] PCIE_IRXP4_MTXP4
C2302 1 SCD1U10V2KX-5GP
BB32
PCIE_ITXN4_MRXN4_C BD32 PERP4 SML1CLK/GPIO58 E10 KBC_SCL1 [37] SB-1020
[76] PCIE_ITXN4_MRXN4
C2311
2
2 1 SCD1U10V2KX-5GP PCIE_ITXP4_MRXP4_C BE32 PETN4 WWAN G12 KBC_SDA1 +3.3V_RUN
[76] PCIE_ITXP4_MRXP4 PETP4 SML1DATA/GPIO75 KBC_SDA1 [37]
PCI-E*
[34] PCIE_IRXN5_NTXN5 BF33 PERN5 CL_CLK +3.3V_ALW RN2303
[34] PCIE_IRXP5_NTXP5
C2308 1 SCD1U10V2KX-5GP
BH33
PCIE_ITXN5_NRXN5_C BG32 PERP5 New CL_CLK1 T13 1
TP2301 TPAD14-GP
Controller
[34] PCIE_ITXN5_NRXN5 2 PETN5 2 3
1
[34] PCIE_ITXP5_NRXP5 C2304 2 1 SCD1U10V2KX-5GP PCIE_ITXP5_NRXP5_C BJ32
PETP5 Card CL_DATA1 T11 CL_DATA 1
TP2302 TPAD14-GP R2304
1 4
Link
BA34 T9 CL_RST# 1 10KR2J-3-GP SRN2K2J-1-GP
PERN6 CL_RST1# TP2303 TPAD14-GP
AW34 PERP6
BC34
2
PETN6
BD34 PETP6
H1 PEG_CLKREQ# PCH_SMB_DATA 6 1
PEG_A_CLKRQ#/GPIO47 PCH_SMBDATA [7,18,19,40,64,76]
RN
AT34 PERN7
AU34 PERP7 A00-0104-1 5 2
AU36 AD43 CLK_PCIE_VGA1# RN2327 1 4 CLK_PCIE_VGA# [80] 1ST: 84.DMN66.03F
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA1 0R4P2R-PAD
AV36 PETP7 CLKOUT_PEG_A_P AD45 2 3 CLK_PCIE_VGA [80] 4 3 2ND: 84.27002.F3F
BG34 AN4 CLK_EXP_N CLK_EXP_N [9]
PERN8 CLKOUT_DMI_N
PEG
C BJ34 AN2 CLK_EXP_P CLK_EXP_P [9] Q2301 C
PERP8 CLKOUT_DMI_P DMN66D0LDW -7-GP
BG36 PETN8 PCH_SMBCLK [7,18,19,40,64,76]
BJ36 PETP8
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. AT1 PCH_SMB_CLK
CLKOUT_DP_N/CLKOUT_BCLK1_N
PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN CLKOUT_DP_P/CLKOUT_BCLK1_P AT3
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
From CLK BUFFER

AW24 CLKIN_DMI# CLKIN_DMI# [7] PEG_CLKREQ#
CLKIN_DMI_N CLKIN_DMI
A00-0104-1 P9 PCIECLKRQ0#/GPIO73 CLKIN_DMI_P BA24 CLKIN_DMI [7]
RN
D
[34] CLK_PCIE_NEW # RN2311 1 4 CLK_PCIE_NEW 1# AM43 AP3 CLK_CPU_BCLK# CLK_CPU_BCLK# [7]
0R4P2R-PAD CLK_PCIE_NEW 1 CLKOUT_PCIE1N CLKIN_BCLK_N CLK_CPU_BCLK
[34] CLK_PCIE_NEW 2 3 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_CPU_BCLK [7]
Q2305
[34] NEW CARD_CLKREQ# NEW CARD_CLKREQ# U4 [25,51] DGPU_1D8V_PGOOD G 2N7002A-7-GP
PCIECLKRQ1#/GPIO18
RN
F18 DREFCLK# DREFCLK# [7]

CLKIN_DOT_96N DREFCLK
CLKIN_DOT_96P E18 DREFCLK [7] 1ST: 84.2N702.E31
RN2305 1 4 CLK_PCIE_MINI1_1# AM47
[64] CLK_PCIE_MINI1# 2ND: 84.2N702.D31
S
0R4P2R-PAD CLK_PCIE_MINI1_1 CLKOUT_PCIE2N
[64] CLK_PCIE_MINI1 2 3 AM48 CLKOUT_PCIE2P
AH13 CLK_PCIE_SATA# CLK_PCIE_SATA# [7]
MINI1_CLKREQ# CLKIN_SATA_N/CKSSCD_N CLK_PCIE_SATA
[64] MINI1_CLKREQ# N4 PCIECLKRQ2#/GPIO20 CLKIN_SATA_P/CKSSCD_P AH12 CLK_PCIE_SATA [7]
RN
[76] CLK_PCIE_LAN# RN2304 1 4 CLK_PCIE_LAN1# AH42 P41 CLK_PCH_14M CLK_PCH_14M [7] un-stuff 25M X'tal without HDMI/eDP/DP
0R4P2R-PAD CLK_PCIE_LAN1 CLKOUT_PCIE3N REFCLK14IN
[76] CLK_PCIE_LAN 2 3 AH41 CLKOUT_PCIE3P
[76] CLKREQ#_LAN CLKREQ#_LAN A8 J42 CLK_PCI_FB CLK_PCI_FB [21] SC-1125-1

PCIECLKRQ3#/GPIO25 CLKIN_PCILOOPBACK
C2313 pop 0 ohm if no use 25MHz XTAL
RN2309 2 3 CLK_PCIE_MINI2_1# AM51 AH51 XTAL25_IN +1.05V_VTT
[76] CLK_PCIE_MINI2# CLKOUT_PCIE4N XTAL25_IN
[76] CLK_PCIE_MINI2 0R4P2R-PAD 1 4 CLK_PCIE_MINI2_1 AM53 AH53 XTAL25_OUT C2313
CLKOUT_PCIE4P XTAL25_OUT XTAL25_IN
B 2 1 B
MINI2_CLKREQ# XCLK_RCOMP
XTAL-25MHZ-67GP
M9 PCIECLKRQ4#/GPIO26 XCLK_RCOMP AF38 1 2
1
RN
R2306 90D9R2F-1-GP 0R2J-2-GP
1MR2J-1-GP
1
R2380
TP2307 DY
X2301
AJ50 T45 TP_CLK_OUTFLEX0 1 DY
CLKOUT_PCIE5N CLKOUTFLEX0/GPIO64 TPAD14-GP
AJ52 CLKOUT_PCIE5P
2
PCIECLKRQ5# H6 P43 TP_CLK_PCI_LPC 1 TP2305
Clock Flex
PCIECLKRQ5#/GPIO44 CLKOUTFLEX1/GPIO65 TPAD14-GP XTAL25_OUT 2 DY1

AK53 T42 TP_CLK_PCH_REF14 1 TP2306 SB-1104
CLKOUT_PEG_B_N CLKOUTFLEX2/GPIO66 TPAD14-GP C2307
AK51 CLKOUT_PEG_B_P pop for 25MHz
SC18P50V2JN-1-GP
[21] PEG_B_CLKRQ# PEG_B_CLKRQ# P13 N50 CLK48M/EDID_SEL 1 2 CLK_PCH_48M [32]
PEG_B_CLKRQ#/GPIO56 CLKOUTFLEX3/GPIO67 R2307 0R0402-PAD-2-GP
A00-0104-1
IBEXPEAK-M-GP-NF
Pull up in page 21 for layout convenience

SB-1020
+3.3V_RUN move EDID_SELECT# from GPIO66 to GPIO5
+3.3V_ALW SB
1
R2333 RN2307 swap net for layout

10KR2J-3-GP 8 1 PCIECLKRQ5#
7 2 USB_OC#12_13 USB_OC#12_13 [21]
6 3 CLKREQ#_LAN
2
Q2306_1 5 4 MINI2_CLKREQ#
1ST: 84.03904.H11
1
Q2306 SRN10KJ-7GP
A 2ND: 84.03904.L06 MMBT3904-7-F-GP
A
+3.3V_RUN 1st Samsung

[76] MINI2_CLKREQ_R# 2 3 MINI2_CLKREQ# SB-1026
RN2308 swap net for layout
R2309 1
DY 2 0R2J-2-GP 8 1 NEW CARD_CLKREQ# Wistron Corporation
7 2 KB_DET_R# 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
KB_DET_R# [25]
6 3 GPO_DSM Taipei Hsien 221, Taiwan, R.O.C.
GPO_DSM [24,76]
5 4 MINI1_CLKREQ#
Title
SRN10KJ-6-GP SB-1023 PCH (PCI-E/SMBUS/CLOCK/CL)
RN2308 change to 2*1 size
www.vinafix.vn
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2 +RTC_CELL
R2401 R2402
10MR2J-L-GP 20KR2J-L2-GP
1 2
SSID = PCH
X2401 INTVRMEN- Integrated SUS
1.1V VRM Enable
1
1 4 C2401
High - Enable internal VRs
SC1U6D3V3KX-2GP
2
1
1
C2402 2 3 C2403
D SC12P50V2JN-3GP SC12P50V2JN-3GP U2001A 1 OF 10 LPC_LAD[0..3] D
LPC_LAD[0..3] [36,37,70]
2
2
X-32D768KHZ-46GP PCH_RTCX1 B13 D33 LPC_LAD0
+RTC_CELL PCH_RTCX2 RTCX1 FWH0/LAD0 LPC_LAD1
SB-18 D13 RTCX2 FWH1/LAD1 B33
R2403 C32 LPC_LAD2
20KR2J-L2-GP FWH2/LAD2 LPC_LAD3
FWH3/LAD3 A32
1 2 PCH_RTCRST# C14 RTCRST#
FWH4/LFRAME# C34 LPC_LFRAME# [36,37,70]
2
1st: EPSON 82.30001.861 SRTCRST# D17 SRTCRST#
1
C2404 G2401 A34
RTC
LPC
2nd: QUARTECH 82.30001.A81 SC1U6D3V3KX-2GP GAP-OPEN 1 2 SM_INTRUDER# A16
LDRQ0#
F34
INTRUDER# LDRQ1#/GPIO23
DW 3rd: KDS 82.30001.691 R2406 1MR2J-1-GP
2
+RTC_CELL 1 2 PCH_INTVRMEN A14 AB9 INT_SERIRQ [25,36,37]
1
07/23 Added R2404 330KR2F-L-GP INTVRMEN SERIRQ
1.Added "ME in Manufacturing Mode" strap
2.Added CardReader_Wake# to sent Card detect signal for PCH . ( Only For JMB380 )
[30] PCH_AZ_CODEC_BITCLK
R2405 1 2 33R2J-2-GP ACZ_BIT_CLK A30 HDA_BCLK
HDD
Flash Descriptor Security SATA0RXN AK7 SATA_IRXN0_HTXN0_C [59]
R2407 1 2 33R2J-2-GP ACZ_SYNC_R D29 AK6
Override/ ME Debug Mode [30] PCH_AZ_CODEC_SYNC HDA_SYNC SATA0RXP SATA_ITXN0_HRXN0_C C2405 1
SATA_IRXP0_HTXP0_C [59]
SATA0TXN AK11 2 SCD01U25V2KX-3GP SATA_ITXN0_HRXN0 [59]
P1 AK9 SATA_ITXP0_HRXP0_C C2406 1 2 SCD01U25V2KX-3GP SATA_ITXP0_HRXP0 [59]
[30] SB_SPKR SPKR SATA0TXP
ME_UNLOCK# [30] PCH_AZ_CODEC_RST#
R2408 1 2 33R2J-2-GP ACZ_RST#_R C30 HDA_RST#
ODD
This strap should only be asserted low via SATA1RXN AH6 SATA_IRXN1_OTXN1_C [59]
external pull down in manufacturing/debug SATA1RXP AH5 SATA_IRXP1_OTXP1_C [59]
[30] PCH_SDIN_CODEC G30 AH9 SATA_ITXN1_ORXN1_C C2407 1 2 SCD01U25V2KX-3GP SATA_ITXN1_ORXN1 [59]
environments ONLY. HDA_SDIN0 SATA1TXN
AH8 SATA_ITXP1_ORXP1_C C2408 1 2 SCD01U25V2KX-3GP
SATA1TXP SATA_ITXP1_ORXP1 [59]
F30 HDA_SDIN1
SATA2RXN AF11
C E32 AF9 C
IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
1 2 ME_UNLOCK_R# F32 AF6
DY
R2419 1KR2J-1-GP HDA_SDIN3 SATA2TXP
SATA3RXN AH3
R2409 1 2 33R2J-2-GP ACZ_SDATAOUT_R B29 AH1
[30] PCH_SDOUT_CODEC HDA_SDO SATA3RXP
SATA3TXN AF3
R2417 1 2 ME_UNLOCK_R# H32

SATA3TXP AF1
ESATA
SATA
[37] ME_UNLOCK# 0R0402-PAD-2-GP HDA_DOCK_EN#/GPIO33
SATA4RXN AD9 ESATA_IRX_DTX_N4_C [63]
A00-0104-1 J30 HDA_DOCK_RST#/GPIO13 SATA4RXP AD8 ESATA_IRX_DTX_P4_C [63]
SATA4TXN AD6 ESATA_ITX_DRX_N4 [63]
SATA4TXP AD5 ESATA_ITX_DRX_P4 [63]
TP2404 1 PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
NO REBOOT STRAP TP2405 1 PCH_JTAG_TMS K3 AB3
+3.3V_RUN JTAG_TMS SATA5TXN
SATA5TXP AB1
No Reboot Strap R23 TP2406 1 PCH_JTAG_TDI K1 JTAG_TDI
JTAG
2 SB_SPKR Low = Default TP2407 PCH_JTAG_TDO
1
R2410 DY 1KR2J-1-GP HDA_SPKR High = No Reboot
1 J2 JTAG_TDO SATAICOMPO AF16
+1.05V_VTT
TP2408 1 PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI R2412 37D4R2F-GP
[62] PCH_SPI_CLK R2413 1 2 0R2J-2-GP SPI_CLK_R BA2 SPI_CLK
[62] PCH_SPI_CS0# R2414 1 2 0R2J-2-GP SPI_CS#0_R AV3

B SPI_CS0# B
SB-1026 AY3 SPI_CS1# SATALED# T3 SATA_LED# [66]

1. remove R2411 pull high INT_SERIRQ to RN2501.1
[62] PCH_SPI_DO R2415 1 2 0R2J-2-GP SPI_MOSI_R AY1 Y9 GPO_DSM GPO_DSM [23,76]
SPI_MOSI SATA0GP/GPIO21
SPI
PCH_GPIO19
DW [62] PCH_SPI_DI AV1 SPI_MISO SATA1GP/GPIO19 V1 PCH_GPIO19 [25]
07/02 Change SC-1208-1
1.Change R2410 to dummy IBEXPEAK-M-GP-NF
change R2413,R2414,R2415 from 15ohm to 0 ohm
DW
07/10 assign GPIO
1.assign GPIO GPIO_DSM,Felic_DETECT#
A 1st Samsung A
Wistron Corporation
Title
PCH (SPI/RTC/LPC/SATA/IHDA)
Winery13 MB DIS A00
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_GPU +3.3V_RUN_GPU +3.3V_RUN
1
SSID = PCH
2
R2555 R2503
R2552 2K2R2J-2-GP 10KR2J-3-GP
10KR2J-3-GP U2001F 6 OF 10
Q2515_1
1 2
2
DEEP_IDLE# Y3 AH45
1
BMBUSY#/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
Q2515 [37] ECSCI# ECSCI# C38 TACH1/GPIO1
[81] DEEPIDLE_W AKE_INT_R# 3 2
MMBT3904-7-F-GP [78] BIO_DET# BIO_DET# D37 TACH2/GPIO6
D SB-32 CLKOUT_PCIE7N AF48 D
MISC
ECSW I# J32 AF47
[37] ECSW I# TACH3/GPIO7 CLKOUT_PCIE7P
ECSMI# F10
[37] ECSMI# GPIO8
1
C2501
SC47P50V2JN-3GP DY K9 LAN_PHY_PWR_CTRL/GPIO12 A20GATE U2 KA20GATE [37]
2
PCH_GPIO15 T7 GPIO15
A00-0104-1 [80] DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3 BCLK_CPU_N [9] +1.05V_VTT
SATA4GP/GPIO16 CLKOUT_BCLK0_N/CLKOUT_PCIE8N
[86] GFX_CORE_PGOOD 1 2
[23,51] DGPU_1D8V_PGOOD R2505
1 2 0R0402-PAD-2-GP DGPU_PW ROK F38 AM1 BCLK_CPU_P [9]
TACH0/GPIO17 CLKOUT_BCLK0_P/CLKOUT_PCIE8P
2
R2506 0R0402-PAD-2-GP
[54] LCD_CBL_DET# 1 2 LCD_CBL_DET_R# Y7 BG10 R2509
SCLOCK/GPIO22 PECI H_PECI [9]
GPIO
R3749 100R2J-2-GP 56R2J-4-GP
H10 GPIO24 RCIN# T1 KBRCIN# [37]
+3.3V_RUN
1
PCH_GPIO27 AB12 BE10 H_PW RGOOD [9,42]
GPIO27 PROCPWRGD
CPU
DW TPAD14-GP TP2508 1 PCH_GPIO28 V13 BD10 PCH_THERMTRIP_R 1 2
07/02 Change GPIO28 THRMTRIP# H_THRMTRIP# [9,37,42]
R2507 R2511
10KR2J-3-GP 1.Change CLK_SATA_OE# to pull-down STP_PCI# 56R2J-4-GP
M11 STP_PCI#/GPIO34
1 2DGPU_PW ROK Placed Within 2" from PCH
PCH_GPIO35 V6 SATACLKREQ#/GPIO35
[37] DGPU_PW R_EN# DGPU_PW R_EN# AB7 BA22

SATA2GP/GPIO36 TP1
2
DGPU_PRSNT# AB13 AW22

R2525 SATA3GP/GPIO37 TP2
C R2526 10KR2J-3-GP PCH_GPIO38 V3 BB22 C
10KR2J-3-GP SLOAD/GPIO38 TP3
1
2 PCH_GPIO27 R2548 2100R2J-2-GP KB_DET_R#

1
DY [68] KB_DET# 1 P3 SDATAOUT0/GPIO39 TP4 AY45
[23] KB_DET_R# PCIECLKRQ6# H3 AY46

PCIECLKRQ6#/GPIO45 TP5
[9] DDR_RST_GATE# DDR_RST_GATE# F1 AV43

PCIECLKRQ7#/GPIO46 TP6
[40] FFS_INT2_R FFS_INT2_R AB6 AV45

SDATAOUT1/GPIO48 TP7
[37] TURBO_BOOST_ALERT# TURBO_BOOST_ALERT# AA4 AF13
SATA5GP/GPIO49 TP8
PCH_GPIO57 F8 M18
GPIO57 TP9
07/10 Added N18
1.Changed PCH GPIO DDR_RST_GATE from GPIO57 to GPIO46 , Bason on design guide TP10
07/23 Added
1.Added Finger Printer Detect Pin, control by PCH For layout request A4
A49
VSS_NCTF_1 TP11 AJ24
2.Change KB_DET signal from EC to PCH control
NCTF
VSS_NCTF_2
RSVD
3.Change LCD_CBL_DET signal from EC to PCH control A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
+3.3V_ALW B2 M32
VSS_NCTF_7 TP14
B4 VSS_NCTF_8
PCH_GPIO28 1 2 B52 N32
R2530 10KR2J-3-GP VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
TPAD14-GP TP2511 1 PCH_NCTF_2 BF1 N30
B VSS_NCTF_13 TP17 B
BF53 VSS_NCTF_14
PCH_GPIO15 1 2 BH1 H12
R2532 1KR2J-1-GP VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
PCIECLKRQ6# 1 2 BH53
R2521 10KR2J-3-GP VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
TPAD14-GP TP2512 1 PCH_NCTF_3 BJ49 VSS_NCTF_22
SB- BJ5 VSS_NCTF_23 NC_3 AB42
BJ50
swap net for layout +3.3V_ALW BJ52
VSS_NCTF_24
AB41
RN2504 VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
ECSMI# 1 4 D1 T39
PCH_GPIO57 VSS_NCTF_27 NC_5
2 3 D2 VSS_NCTF_28
D53 VSS_NCTF_29
SRN10KJ-5-GP +3.3V_RUN TPAD14-GP TP2510 1 PCH_NCTF_1 E1 P6 INIT3_3V# 1 TP2506TPAD14-GP
TPAD14-GP TP2509 PCH_NCTF_4 VSS_NCTF_30 INIT3_3V#
1 E53 VSS_NCTF_31
SB-1023 TP24 C10
IBEXPEAK-M-GP-NF
LCD_CBL_DET_R# R2520 2 1 10KR2J-3-GP
DGPU_HOLD_RST# R2516 1 2 10KR2J-3-GP +3.3V_RUN

DY
STP_PCI# R2517 1 2 10KR2J-3-GP +3.3V_RUN
1
SRN10KJ-5-GP
ECSW I#
A ECSCI#
2
1
3
4
DYR2527
10KR2J-3-GP 1st Samsung A
+3.3V_RUN RN2502
2
SRN10KJ-5-GP +3.3V_RUN DGPU_PRSNT#

[24] PCH_GPIO19 PCH_GPIO19 2 3 Wistron Corporation
1
PCH_GPIO38 1 4 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

R2528 Taipei Hsien 221, Taiwan, R.O.C.
RN2503 RN2501 10KR2J-3-GP
SB-1026 INT_SERIRQ 1 8 Title
[24,36,37] INT_SERIRQ
FFS_INT2_R
swap net for layout 2 7
PCH (GPIO/CPU)
2
DGPU_PW R_EN# 3 6
BIO_DET# 4 5 Size Document Number Rev
www.vinafix.vn
[78] BIO_DET#
SB-1023 Winery13 MB DIS A00
SRN10KJ-6-GP
RN2501 change to 2*1 size Date: W ednesday, January 13, 2010 Sheet 25 of 88
5 4 3 2 1
5 4 3 2 1
SSID = PCH
+1.05V_VTT +3.3V_CRT_LDO
69mA
U2001G POWER 7 OF 10 L2603
1.432A AB24
AB26
VCCCORE VCCADAC AE50 +VCCA_DAC_1_2 1 2
BLM18PG181SN1D-GP
1 R2602 2
0R0402-PAD-2-GP
+3.3V_RUN
VCCCORE
1
C2601 AB28 AE52 C2604 C2605 C2603
VCCCORE VCCADAC
SCD01U16V2KX-3GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP C2602 SC10U6D3V5MX-3GP A00-0104-1
DY SC1U6D3V2KX-GP
AD26 VCCCORE
CRT
D AD28 1.432A AF53 D
2
VCCCORE VSSA_DAC
AF26 VCCCORE
VCC CORE
AF28 VCCCORE VSSA_DAC AF51
AF30 VCCCORE
AF31 VCCCORE
AH26 VCCCORE
AH28 +3VS_VCCA_LVD +3.3V_RUN
VCCCORE R2609
AH30
AH31
AJ30
VCCCORE
VCCCORE <1mA VCCALVDS AH38
C2623
2 1 <1mA
0R0603-PAD-2-GP
VCCCORE
AJ31 VCCCORE VSSA_LVDS AH39 1
DY2 A00-0104-1
+1.8V_RUN
SCD1U10V2KX-5GP
+1.05V_VTT
VCCTX_LVDS AP43 +1.8VS_VCCTX_LVDS 1 2 59mA
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
AP45 L2604
VCCTX_LVDS
1
59mA VCCTX_LVDS AT46 C2625 C2624 C2626 IND-D1UH-21-GP
LVDS
SC10U6D3V5MX-3GP
AK24 VCCIO VCCTX_LVDS AT45
DY
2
TP2602 1 TPAD14-GP VCCAPLLEXP BJ24 +3.3V_CRT_LDO +5V_RUN
VCCAPLLEXP
VCC3_3 AB34
U2601
SB-21 +3.3V_RUN
AN20 VCCIO 357mA VCC3_3 AB35
AN22 5 1
357mA
HVCMOS
VCCIO OUT IN
AN23 VCCIO VCC3_3 AD35
AN24 VCCIO DY GND 2
1
C2607 C2628
+1.05V_VTT
AN26 VCCIO
3.062A SCD1U10V2KX-5GP SC10U6D3V5MX-3GP C2629 DY
AN28
BJ26
VCCIO DY 4 NC#4 SHDN# 3
SC1U10V3KX-3GP
3.062A
2
C VCCIO C
BJ28 VCCIO
AT26 MAX8511EXK33-T-GP
VCCIO
1
1
C2608 C2609 C2610 C2611 C2612 AT28 +VCC_VRM
VCCIO
AU26 VCCIO
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC10U6D3V5KX-1GP
AU28
2
2
VCCIO
AV26
AV28
AW26
VCCIO
VCCIO VCCVRM AT24 35mA +1.05VS_VCC_DMI +1.05V_VTT
VCCIO
AW28 VCCIO
58mA
DMI
BA26 VCCIO VCCDMI AT16 1 R2601 2
BA28 0R0402-PAD-2-GP
VCCIO
1
BB26 AU16 C2613 A00-0104-1
VCCIO VCCDMI SC1U10V3KX-3GP
BB28 VCCIO
BC26
2
VCCIO
PCI E*
BC28 VCCIO
BD26 +3.3V_RUN
+3.3V_RUN VCCIO
BD28 VCCIO
BE26 VCCIO VCCPNAND AM16
BE28 AK16
BG26
VCCIO
VCCIO
VCCPNAND
VCCPNAND AK20 156mA
1
C2614 BG28 156mA AK19

VCCIO VCCPNAND
1
SCD1U10V2KX-4GP BH27 AK15 C2615
VCCIO VCCPNAND SCD1U10V2KX-5GP
AK13
2
VCCPNAND
AN30 AM12
2
VCCIO VCCPNAND
NAND / SPI
AN31 VCCIO VCCPNAND AM13
VCCPNAND AM15
+1.8V_RUN
A00-0104-1 357mA AN35 VCC3_3
B R2606 B
2 1 +VCC_VRM AT22 VCCVRM[1]

0R0402-PAD-2-GP
+1.05V_VTT TP2601 1
TPAD14-GP
VCCFDIPLL BJ18 VCCFDIPLL VCCME3_3 AM8
AM9
85mA A00-0104-1
+3.3V_RUN
VCCME3_3
FDI
AM23 85mA AP11 R2605

VCCIO VCCME3_3 PCH_VCCME3_3
VCCME3_3 AP9 2 1
0R0402-PAD-2-GP
1
SB-20 C2622
SCD1U10V2KX-5GP
IBEXPEAK-M-GP-NF
A 1st Samsung A
Wistron Corporation
Title
PCH (POWER1)
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
26 of 88
A00
5 4 3 2 1
U2001J POWER 10 OF 10 +1.05V_VTT
TP2701 VCCACLK
SB-15 1
TPAD14-GP
AP51 VCCACLK VCCIO V24
52mA V26
SSID = PCH VCCIO
1
AP53 Y24 C2706
VCCACLK VCCIO
VCCIO Y26
DYSC1U10V2KX-1GP
2
AF23 VCCLAN VCCSUS3_3 V28
+3.3V_ALW
320mA VCCSUS3_3 U28
AF24 VCCLAN VCCSUS3_3 U26
D
VCCSUS3_3 U24 D
VCCSUS3_3 P28
1
DCPSUSBYP Y20 P26
DCPSUSBYP VCCSUS3_3 C2703
VCCSUS3_3 N28
1
C2707 N26 SCD1U10V2KX-4GP
2
SCD1U10V2KX-4GP VCCSUS3_3
AD38 VCCME VCCSUS3_3 M28
M26
2
VCCSUS3_3
AD39 L28
USB
VCCME VCCSUS3_3
VCCSUS3_3 L26
+1.05V_VTT AD41 J28
VCCME VCCSUS3_3
J26
1.849A AF43 VCCME
VCCSUS3_3
VCCSUS3_3 H28
163mA VCCSUS3_3 H26
AF41 VCCME 1.849A VCCSUS3_3 G28
1
C2705 C2708 G26
SC10U6D3V5KX-1GP SC1U6D3V2KX-GP VCCSUS3_3 +3.3V_ALW
DY AF42 VCCME VCCSUS3_3 F28
F26 DW
2
VCCSUS3_3 +3.3V_ALW
V39 VCCME VCCSUS3_3 E28
E26 07/10 Change resistor Value
Clock and Miscellaneous

VCCSUS3_3
2
1.R2701,R2702 value corrected to 100 Ohms following PDG doc
V41 VCCME VCCSUS3_3 C28
C26 D2701
VCCSUS3_3
1
V42 B27 CH751H-40PT-GP +5V_ALW
VCCME VCCSUS3_3
1
C2704 C2710 C2709
SB-17 SC10U6D3V5KX-1GP SC1U6D3V2KX-GP VCCSUS3_3 A28
SCD1U10V2KX-4GP
DY Y39 A26
1
VCCME VCCSUS3_3 +3.3V_RUN
2
+1.05V_VTT Y41 U23 +1.05V_VTT 1 2
L2702 VCCME VCCSUS3_3
1 2 +1.05VS_VCCA_A_DPL Y42 V23 R2701
VCCME VCCIO
2
IND-10UH-218-GP 100R2J-2-GP
1
1
C C2711 +5VALW _PCH_VCC5REFSUS D2702 +5V_RUN C
C2734 SC1U6D3V2KX-GP
<1mA V5REF_SUS F24
C2712 CH751H-40PT-GP
SC10U6D3V5MX-3GP +VCCRTCEXT SC1U6D3V2KX-GP
DY V9
2
2
DCPRTC
1
1
C2713 +VCC_VRM
SCD1U10V2KX-4GP <1mA K49 +5VS_PCH_VCC5REF 1 2
L2703 V5REF
AU24
2
VCCVRM
PCI/GPIO/LPC
1 2 +1.05VS_VCCA_B_DPL R2702
1
IND-10UH-218-GP J38 +3.3V_RUN 100R2J-2-GP
VCC3_3
1
C2714 BB51 C2715

C2735
DY SC1U6D3V2KX-GP 68mA +1.05VS_VCCA_A_DPL BB53
VCCADPLLA
68mA L38 SC1U6D3V2KX-GP
2
SC10U6D3V5MX-3GP VCCADPLLA VCC3_3
2
1
M36
69mA +1.05VS_VCCA_B_DPL BD51 VCCADPLLB
VCC3_3 C2716
SCD1U10V2KX-4GP
+3.3V_RUN
BD53 69mA N36
2
VCCADPLLB VCC3_3
+1.05V_VTT AH23 P36
VCCIO VCC3_3
1
AJ35 VCCIO
AH35 U35 C2717
VCCIO VCC3_3
SCD1U10V2KX-4GP
2
1
C2718 C2719 C2720 AF34

SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP VCCIO
VCC3_3 AD13
AH34
2
VCCIO
AF32 VCCIO VCCSATAPLL TP2702
+VCCSST V12
VCCSATAPLL AK3
AK1 TPAD14-GP
1 SB-16
DCPSST VCCSATAPLL
1
B +1.05V_VTT B
C2723 +1.05VALW _INT_VCCSUS Y22
SCD1U10V2KX-4GP DCPSUS
AH22
2
VCCIO
1
C2724 +VCC_VRM
1
SCD1U10V2KX-4GP C2725
P18 196mA AT20 SC1U6D3V2KX-GP
2
VCCSUS3_3 VCCVRM
2
+3.3V_ALW U19
SATA
VCCSUS3_3
PCI/GPIO/LPC
AH19
163mA U20 VCCSUS3_3
VCCIO
AD20
VCCIO
1
U22 VCCSUS3_3
C2726 AF22
SCD1U10V2KX-4GP +3.3V_RUN VCCIO
2
VCCIO AD19
V15 VCC3_3 VCCIO AF20
VCCIO AF19
1
V16 VCC3_3 VCCIO AH20

C2727
SCD1U10V2KX-4GP Y16 AB19
2
VCC3_3 VCCIO
VCCIO AB20
+1.05V_VTT AB22
VCCIO +1.05V_VTT
AD22
<1mA AT18 V_CPU_IO
VCCIO
AA34
CPU
VCCME
1
C2728 C2729 C2730 <1mA Y34

SC10U6D3V5KX-1GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP VCCME
AU18 V_CPU_IO VCCME Y35
AA35
2
VCCME
A R2707 A00-0104-1 1st Samsung A
+RTC_CELL 6mA
RTC
A12 VCCRTC 2mA 6mA VCCSUSHDA L30 1 2 +3.3V_ALW

HDA
0R0402-PAD-2-GP
2mA Wistron Corporation
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
IBEXPEAK-M-GP-NF C2731 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

1
C2732 C2733 SC1U6D3V2KX-GP Taipei Hsien 221, Taiwan, R.O.C.

2
Title
2
+3VS_+1.5VS_HDA_IO PCH (POWER2)

5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
27 of 88
A00
5 4 3 2 1
U2001I 9 OF 10
AY7 VSS VSS H49
B11 H5
SSID = PCH B15
B19
VSS
VSS
VSS
VSS
VSS
VSS
J24
K11
B23 VSS VSS K43
B31 VSS VSS K47
B35 VSS VSS K7
B39 VSS VSS L14
B43 VSS VSS L18
B47 VSS VSS L2
D B7 VSS VSS L22 D
U2001H 8 OF 10 BG12 L32
VSS VSS
AB16 VSS BB12 VSS VSS L36
BB16 VSS VSS L40
AA19 VSS VSS AK30 BB20 VSS VSS L52
AA20 VSS VSS AK31 BB24 VSS VSS M12
AM19 VSS VSS AK34 BB34 VSS VSS M20
AA24 VSS VSS AK35 BB38 VSS VSS N38
AA31 VSS VSS AK49 BC10 VSS VSS M46
AA32 VSS VSS AK5 BC14 VSS VSS M49
AB11 VSS VSS AK8 BC18 VSS VSS M5
AB15 VSS VSS AL2 BC2 VSS VSS M8
AB23 VSS VSS AL52 BC22 VSS VSS N24
AB30 VSS VSS AM11 BC32 VSS VSS P11
AB31 VSS VSS BB44 BC36 VSS VSS AD15
AB32 VSS VSS AD24 BC40 VSS VSS P22
AB47 VSS VSS AM24 BH9 VSS VSS P34
AB5 VSS VSS AM26 BD48 VSS VSS P42
AB8 VSS VSS AM28 BD49 VSS VSS P45
AC2 VSS VSS BA42 BD5 VSS VSS P47
AC52 VSS VSS AM30 BE12 VSS VSS R2
AD11 VSS VSS AM31 BE16 VSS VSS R52
AD12 VSS VSS AM32 BE20 VSS VSS T12
C AD16 AM34 BE24 T41 C
VSS VSS VSS VSS
AD34 VSS VSS AU20 BE46 VSS VSS U30
AU22 VSS VSS AM46 BE48 VSS VSS U31
AD42 VSS VSS AV22 BE50 VSS VSS U32
AD46 VSS VSS AM49 BE6 VSS VSS U34
AD49 VSS VSS AM7 BE8 VSS VSS P38
AD7 VSS VSS AA50 BF3 VSS VSS V11
AE2 VSS VSS BB10 BF49 VSS VSS P16
AE4 VSS VSS AN32 BF51 VSS VSS V19
AF12 VSS VSS AN50 BG18 VSS VSS V20
Y13 VSS VSS AN52 BG24 VSS VSS V22
AH49 VSS VSS AP12 BG4 VSS VSS V30
AU4 VSS VSS AP42 BG50 VSS VSS V31
AF35 VSS VSS AP46 BH11 VSS VSS V32
AP13 VSS VSS AP49 BH15 VSS VSS V34
AN34 VSS VSS AP5 BH19 VSS VSS V35
AF45 VSS VSS AP8 BH23 VSS VSS V38
AF46 VSS VSS AR2 BH31 VSS VSS V43
AF49 VSS VSS AR52 BH35 VSS VSS V45
AF5 VSS VSS AT11 BH39 VSS VSS V46
AF8 VSS VSS BA12 BH43 VSS VSS V47
AG2 VSS VSS AH48 BH47 VSS VSS V49
AG52 VSS VSS AT32 BH7 VSS VSS V5
AH11 VSS VSS AT36 C12 VSS VSS V7
AH15 VSS VSS AT41 C50 VSS VSS V8
B B
AH16 VSS VSS AT47 D51 VSS VSS W2
AH24 VSS VSS AT7 E12 VSS VSS W52
AH32 VSS VSS AV12 E16 VSS VSS Y11
AV18 VSS VSS AV16 E20 VSS VSS Y12
AJ19 VSS VSS AV34 E38 VSS VSS Y28
AJ28 VSS VSS AV8 F49 VSS VSS Y46
AJ32 VSS VSS AW14 F5 VSS VSS P49
AJ34 VSS VSS AW18 G10 VSS VSS Y5
AT5 VSS VSS AW2 G14 VSS VSS Y6
AJ4 VSS VSS BF9 G18 VSS VSS Y8
AK12 VSS VSS AW32 G2 VSS VSS P24
AM41 VSS VSS AW36 G22 VSS VSS T43
AN19 VSS VSS AW40 G32 VSS VSS AD51
AK26 VSS VSS AW52 G36 VSS VSS AT8
AK22 VSS VSS AY11 G40 VSS VSS AD47
AK23 VSS VSS AY43 G44 VSS VSS Y47
AK28 VSS VSS AY47 G52 VSS VSS AT12
AF39 VSS VSS AM6
IBEXPEAK-M-GP-NF H16 AT13
VSS VSS
H20 VSS VSS AM5
A H30 VSS VSS AK45 1st Samsung A
H34 VSS VSS AK39
H38 VSS VSS AV14
H42 VSS Wistron Corporation
IBEXPEAK-M-GP-NF Title
PCH (VSS)
5 4
www.vinafix.vn 3 2
Winery13 MB DIS
Sheet
1
28 of 88
A00
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
A00-0104-1
+AVDD +5V_RUN
SSID = AUDIO L3004
1 2
0R0805-PAD-2-GP
+3.3V_RUN +3.3V_RUN
1
C3015 C3022
SCD1U10V2KX-4GP SC1U10V3KX-3GP
2
A00-0104-1 Close to codec Close to codec
2
0R0402-PAD-2-GP AUD_DVDDCORE
D
R3011 D
1
1
C3009 C3019 C3016 +PVDD A00-0104-1 +5V_RUN
SC1U6D3V2KX-GP SCD1U10V2KX-4GP SC10U6D3V5MX-3GP
U3001 L3005
2
2
1 2
C3027 1 27 0R0805-PAD-2-GP
SCD1U10V2KX-4GP DVDD_CORE AVDD
38
1
AVDD
9 DVDD
1
39 C3014 C3017 C3011 L3003
DVDDIO PVDD SCD1U10V2KX-4GP SC1U10V3KX-3GP SC10U6D3V5MX-3GP
3 DVDD_IO PVDD 45 1 2
0R0805-PAD-2-GP
2
13 AUD_SENSE_A
PCH_AZ_CODEC_BITCLK SENSE_A
PCH_AZ_CODEC_BITCLK 6 14 AUD_SENSE_B
[24] PCH_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
R3013 1 2 33R2J-2-GP PCH_SDIN_CODEC_C0 8
[24] PCH_SDIN_CODEC HDA_SDI AUD_EXT_MIC_L
1
HP0_PORT_A_L 28 AUD_EXT_MIC_L [60]

PCH_SDOUT_CODEC 5 29 AUD_EXT_MIC_R
C3012 [24] PCH_SDOUT_CODEC HDA_SDO HP0_PORT_A_R AUD_EXT_MIC_R [60]
DY SC4D7P50V2CN-1GP VREFOUT_A_OR_F 23 AUD_VREFOUT_B AUD_VREFOUT_B [60]
PCH_AZ_CODEC_SYNC
2
[24] PCH_AZ_CODEC_SYNC 10 HDA_SYNC

31 AUD_HP1_JACK_L_C R3023 1 2 60D4R2F-GP AUD_HP1_JACK_L
PCH_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R_C R3019 AUD_HP1_JACK_L [60]
[24] PCH_AZ_CODEC_RST# 11 HDA_RST# HP1_PORT_B_R 32 1 2 60D4R2F-GP AUD_HP1_JACK_R
AUD_HP1_JACK_R [60]
PORT_C_L 19
PORT_C_R 20
+3.3V_RUN VREFOUT_C 24
AUD_DMIC_CLK 2
AUD_DMIC_IN0 DMIC_CLK/GPIO1 AUD_SPK_L+
[73] AUD_DMIC_IN0 4 DMIC0/GPIO2 SPKR_PORT_D_L+ 40 AUD_SPK_L+ [60]
41 AUD_SPK_L-
C SPKR_PORT_D_L- AUD_SPK_L- [60] C
1
46 DMIC1/GPIO0/SPDIF_OUT_1
R3020 SPKR_PORT_D_R- 43
48 SPDIF_OUT_0 SPKR_PORT_D_R+ 44
10KR2J-3-GP SC-1204-5
AMP_MUTE# 47 15 connect U3001 pin17, pin18 to pin12 net and change R3016 to 120K for vendor request
[37] AMP_MUTE# EAPD PORT_E_L
2
PORT_E_R 16
AMP_MUTE# R3016 From SB
PUMP_CAPN 17 C3010
PORT_F_L SB_SPKR_R
35 CAP- PORT_F_R 18 2 1 1 2 SB_SPKR [24]
1
SCD1U10V2KX-4GP 120KR2F-L-GP
C3024 12 AUD_PC_BEEP 2 1 KBC_BEEP_R 1 2 KBC_BEEP [37]
SC2D2U25V5KX-1GP PC_BEEP SCD1U10V2KX-4GP
Internal pull up 60K 2 PUMP_CAPP
36 CAP+
25
AUD_PC_BEEP C3018
R3024
From EC
MONO_OUT 499KR2F-1-GP
check external pull up?? Trace width>15 mils
7 DVSS
+3.3V_RUN 33 22 AUD_CAP2
U3002 AVSS CAP2
30 AVSS
5 1 26 21 AUD_VREFFLT
VCC OE# AVSS VREFFILT
AUD_DMIC_CLK_Y 4
DY A 2
3 42 34 AUD_V_B
Y GND PVSS V-
74LVC1G125DC-GP 49 37 AUD_VREG
GND VREG
1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
0R2J-2-GP 92HD79B1A5NLGXTAX-GP
C3023
C3013
DY
1
R3017
C3025
C3021
2
R3014
2
B B
[73] AUD_DMIC_CLK_G 1 2 33R2J-2-GP AUD_DMIC_CLK
1
EC3001
SC22P50V2JN-4GP DY
2
Close to codec
+AVDD
Azalia I/F EMI
Place this block
1
PCH_SDOUT_CODEC
R3018 close to Audio Codec Pin13 +AVDD
2K49R2F-GP
1
1
R3012
2
47R2J-2-GP AUD_SENSE_A R3015

DY 100KR2J-1-GP
1
2
C3026
2
PCH_AZ_CODEC_SDOUT1 SC1KP50V2KX-1GP AUD_SENSE_B
2
1
C3020
A
DY SCD1U10V2KX-4GP R3022 R3021 1st Samsung A
2
20KR2F-L-GP 39K2R2F-L-GP
Wistron Corporation
2

EXT_MIC_JD# [60] Close to Pin14
Title
AUD_HP1_JD# [60] AUDIO CODEC_92HD81
Revised HP/MIC detect circuit
www.vinafix.vn
A3
Winery13 MB DIS A00
2009/06/03 Date: W ednesday, January 13, 2010 Sheet 30 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D
SSID = SDIO D
+3.3V_RUN_CARD
[23] CLK_PCH_48M +3.3V_RUN_CARD trace = 40mil

SD_D2 SD_D2 [33]
PCH GPIO67(48M) confirm with SW SD_D3
1
SD_D3 [33]
C3206 C3207
SCD1U10V2KX-4GP SC10U6D3V5MX-3GP
2
RREF trace =15mils
C3201
1 DY2 RREF
U3201
Close to chip
24
23
22
21
20
19
+3.3V_RUN SC100P50V2JN-3GP RTS5138-GR-GP
090721-1
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
1 R3201 2
6K2R2F-GP 1 18 SD_CMD SD_CMD [33]
RREF SP10
090721-1 [21] USB_PN9 2 DM GPIO0 17
[21] USB_PP9 3 DP SP9 16
4 15 SD_CLK SD_CLK [33]
3V3_IN SP8
+3.3V_RUN_CARD 5 CARD_3V3 SP7 14
V18 6 13 SD_CD# SD_CD# [33]
V18 SP6
2
XD_CD#
1
C C3203 DY C3204 C3202 C
SP1
SP2
SP3
SP4
SP5
SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP SC1U10V2KX-1GP 25
1
GND
7
8
9
10
11
12
V18 trace =15mils
SD_D0 SD_D0 [33]

SD_D1 SD_D1 [33]
SD_W P SD_W P [33]
B B
A 1st Samsung A
Wistron Corporation
Title
CardReader/RTS5138
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = SDIO SD/MMC/MMC+ Card Reader

D D
+3.3V_RUN_CARD +3.3V_RUN_CARD
CARD1
Close to +3.3V_RUN_CARD
4 VDD CD 10 SD_CD# [32]
1 SD_D3_R
CD/DAT3
1
11 C3301 C3302 C3303 C3304 C3305
SD_D0_R CD/WP/GND
SD_D1_R
7 DAT0 WP 12
SD_CLK_R
SD_W P [32] DY SCD1U16V2KX-3GP DY SCD1U16V2KX-3GP SCD01U16V2KX-3GP SC2D2U10V3KX-1GP SC10U6D3V5MX-3GP
8 5
2
SD_D2_R DAT1 CLK SD_CMD_R
9 DAT2 CMD 2
EMPTY 14
VSS1 3
NP1 NP1 VSS2 6
NP2 NP2 GND 13
1ST: 20.I0045.001 CARD-PUSH-9P-1-GP-U

2ND:
C C
Close to CARD1
[32] SD_D0 SD_D0 R3301 1 2 33R2J-2-GP SD_D0_R

SD_W P
[32] SD_CLK SD_CLK R3305 1 2 33R2J-2-GP SD_CLK_R
SD_CD#
[32] SD_CMD SD_CMD R3306 1 2 SD_CMD_R
33R2J-2-GP
1
EC3301 EC3302 EC3303 EC3304 EC3305 EC3306 EC3307 EC3308
SC6D8P50V2CN-GP SC6D8P50V2CN-GP SC6D8P50V2CN-GP DY SC220P50V2KX-3GP SC6D8P50V2CN-GP SC6D8P50V2CN-GP SC6D8P50V2CN-GP SC6D8P50V2CN-GP
2
SC-1207-1
pop EC3301,EC3302,EC3303,EC3305,EC3306,EC3307,EC3308 and change from 100p to 6.8p for EMI
SSID = 1394
B B
Remove 1394
A 1st Samsung A
Wistron Corporation
Title
CARD READER CONN

www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D
SSID = ExpressCard +1.5V_CARD Max. 650mA, Average 500mA. D
+3.3V_CARD Max. 1300mA, Average 1000mA

+3.3V_CARDAUX Max. 275mA
SB-26
NEW 1
27
USB12_N 2
USB12_P 3
NEW CARD_OC# CPUSB# 4
TP3401
PM_SLP_S3# [22,37,42,50,51,86] 5
6
PCH_SMB_CLK 7
[23] PCH_SMB_CLK
PCH_SMB_DATA
21
19
18 [23] PCH_SMB_DATA 8
7
U3401 1 +1.5V_CARD 9
10
OC#
STBY#
GND
THERMAL_PAD
RCLKEN
[22,76] PCIE_W AKE# PCIE_W AKE# 11

+3.3V_CARDAUX 12
For 2nd Source 74.05538.073 PERST# 13
+3.3V_CARD 14
C 16 20 15 C
NC#16 SHDN# PM_SLP_S4# [22,37,50]
14 8 PERST# RN3401 [23] NEW CARD_CLKREQ# NEW CARD_CLKREQ# 16
+1.5V_RUN NC#14 PERST#
13 9 CPUSB# 4 1 CPPE# 17
+1.5V_CARD NC#13 CPUSB# +3.3V_ALW
CPPE# CLK_PCIE_NEW #
+3.3V_CARD 5
4
NC#5 CPPE# 10
6 NRST
3
DY 2 [23] CLK_PCIE_NEW #
[23] CLK_PCIE_NEW CLK_PCIE_NEW
18
19
+3.3V_RUN NC#4 SYSRST# SRN100KJ-6-GP 20
[23] PCIE_IRXN5_NTXN5 PCIE_IRXN5_NTXN5 21
AUXOUT
1.5VOUT
3.3VOUT
R3401 2 1 0R2J-2-GP PLT_RST# [9,21,36,37,64,70,76,80] [23] PCIE_IRXP5_NTXP5 PCIE_IRXP5_NTXP5 22

AUXIN
1.5VIN
3.3VIN
23
C3410 2 1 SC22P50V2JN-4GP PCIE_ITXN5_NRXN5
DY [23] PCIE_ITXN5_NRXN5
[23] PCIE_ITXP5_NRXP5 PCIE_ITXP5_NRXP5
24
25
TPS2231RGP-GP-U 26
15
17
11
12
3
2
1ST: 74.02231.073 28
+3.3V_CARDAUX +3.3V_RUN 2ND: 74.09716.073 SB-1021
PTW O-CON26-6-GP
+3.3V_ALW +3.3V_CARD pop and change L3401 to 120 ohm;
+1.5V_CARD +1.5V_RUN
DY R3402, R3403 for EMI
+1.5V_CARD Max. 650mA, Average 500mA.
+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA 1ST: 20.K0370.026
2ND: 20.K0315.026
A00-0107-1
remove R3402, R3403 for no co-lay after XB
[21] USB_PN12 USB12_N
B B
Lay out close to Chip
2
+3.3V_ALW +1.5V_RUN +3.3V_CARD +3.3V_CARDAUX L3401
DLW 21HN121SQ2L-1GP
1ST: 68.00201.201
1
C3401 C3402 C3405 C3406 C3409

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SC10U6D3V5MX-3GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2ND:
2
3
[21] USB_PP12 USB12_P
+3.3V_RUN +1.5V_CARD
0715 Add commom choke

1
C3403 C3404 C3407 C3408

SCD1U10V2KX-5GP SC4D7U6D3V5KX-3GP SC10U6D3V5MX-3GP SCD1U10V2KX-5GP
2
A 1st Samsung A
Wistron Corporation
Title
ExpressCard
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
A3 A00
Winery13 MB DIS
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
TPM board CONN
TPM1
+3.3V_RUN 11
1
LPC_LAD0 2
[24,37,70] LPC_LAD0
SB-1022 LPC_LAD1 3
[24,37,70] LPC_LAD1
C
LPC_LAD2 4 C
Add R3601 [24,37,70] LPC_LAD2
LPC_LAD3 5
[24,37,70]
[24,37,70]
LPC_LAD3
LPC_LFRAME# LPC_LFRAME# 6
DY
PLT_RST# R3601 1 2 PLT_RST#_TPM 7
[9,21,34,37,64,70,76,80] PLT_RST# 0R2J-2-GP DY [24,25,37] INT_SERIRQ INT_SERIRQ 8
PCLK_TPM 9
[21] PCLK_TPM
10
12
ACES-CON10-4-GP
SC-1125-1
remove TPM AFTP
B B
A A
1st Samsung
Wistron Corporation
Title
TPM
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 SC-1118-1 SB-1020
1
+3.3V_RUN_GPU +3.3V_RUN_GPU KBC_PWR A00-0104-1 KBC_PWR
change power rail to KBC_PWR
SSID = KBC R3746
R3745
1
1 2 KBC_PWRBTN_EC# 2 DY 1
R3748 0R0402-PAD-2-GP
2K2R2J-2-GP 100KR2J-1-GP +3.3V_RTC_LDO
1
+3.3V_RTC_LDO
2
+3.3V_RTC_LDO R3721 Q3714_1 R3722 KBC_PWRBTN# 3 DY
[78] KBC_PWRBTN#
2
10KR2J-3-GP Q3714 10KR2J-3-GP D3704
1
MMBT3904-7-F-GP BAT54C-U-GP R3744
DY 10KR2J-3-GP
2
1
2 3 THERMTRIP_VGA_R#
S
R3747 [81] THERMTRIP_VGA# KBC_PWR
A00-0104-1 A00-0104-1
1
0R0805-PAD-2-GP 1ST: 84.03904.H11 R3754 KBC_ON# G +3.3V_RUN
R3755
2ND: 84.03904.L06 1 DY 2 DY SI2301CDS-T1-GE3-GP
1 2
2
Q3704
D DW 10KR2J-3-GP
AC_IN_L#
0R0402-PAD-2-GP
U3702 D
KBC_PWR
D
L3701 07/10 Added +3.3V_RUN KBC_PWR KBC_SDA1
BLM18AG601SN-3GP Put 0.1uf close to VCC-GND pin pair. 1.Added circuit , D3705 [39,78] THERM_SDA 4 3
1
KBC_PWR For prevent electric leakage KBC_PWR BAT54C-U-GP 5 2
1 2 VBAT
1ST: 68.00084.881 DY 3 AC_IN# [45] KBC_SCL1 6 1 THERM_SCL [39,78]
2
2ND: C3703 C3714
DY
G
DMN66D0LDW-7-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SC4D7U10V3KX-GP
2
C3702
C3706
1
1
C3712
C3711
C3713
C3708
C3701
C3715
EC_PWR_SHDN# KBC_ON# +3.3V_RUN
DY S DY D
2
115
102
88
76
46
19
80
4
U3701A 1 OF 2 SB-22
BAT_IN# [44] Q3706
E51_RxD 1 DY 2 DW
GPIO41
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
2N7002A-7-GP R3725 10KR2J-3-GP
07/07 Change
AGND +3.3V_ALW 1.Change Power rail
R3720
104 124 CAP_LOCK_LED# CAP_LOCK_LED# [66] A00-0104-1 RN3702
VREF GPIO10/LPCPD# PLT_RST1#_1 PLT_RST1#_1 KBC_SCL1
7 1 2 3 2
AD_IA_KBC LRESET# 0R0402-PAD-2-GP PLT_RST# [9,21,34,36,64,70,76,80] KBC_SDA1
[45] AD_IA_KBC
1.8_GFX_ON
97
98
GPI90/AD0 A/D LCLK
2
3
PCLK_KBC [21] 4 1
[51] 1.8_GFX_ON GPI91/AD1 LFRAME# LPC_LFRAME# [24,36,70]
1
THERMTRIP_VGA_R# 99 126 LPC_LAD0 SRN4K7J-8-GP
GPI92/AD2 LAD0 LPC_LAD1 C3717
WD [43] PS_ID_EC 100
TURBO_BOOST_ALERT#108 GPI93/AD3 LAD1
127
128 LPC_LAD2
LPC_LAD[0..3] [24,36,70] DY
SC470P50V2KX-3GP KBC_PWR
[25] TURBO_BOOST_ALERT#
2
07/23 KBC_THERMTRIP# GPIO05 LAD2 LPC_LAD3 RN3701
1. Added R3712 100 Ohm damping resistor
96
GPIO04 LPC LAD3
1
125 BAT_SDA 3 2
2. Added R3713 100 Ohm damping resistor SERIRQ INT_SERIRQ [24,25,36]
BAT_SCL
SCD1U16V2KX-3GP
8 PM_CLKRUN# [22] 4 1
3. Added R3751 100 Ohm damping resistor GPIO11/CLKRUN#
KBRST# 122 KBRCIN# [25]
EC3701
[22] SUS_PWR_DN_ACK SUS_PWR_DN_ACK 101 121 KA20GATE [25] SC-1125-2 SRN4K7J-8-GP
R3712 1 100R2J-2-GP KB_BL_DET_R#105 GPI94 GA20 ECSCI#_KBC
[68] KB_BL_DET#
DGPU_PWR_EN#
2 GPI95 ECSCI#/GPIO54 29
PANEL_BKEN
add U3703 mux for panel backlight enable signal select
KBC_THERMTRIP#
DY
[25] DGPU_PWR_EN# 106 D/A 9 1 2
2
KBC_PWR CAPA2_INT_R# GPI96 GPIO65/SMI# ECSWI#_KBC R3709 100KR2J-1-GP
107 123 D3712
GPI97 GPIO67/PWUREQ#
Pull High : Discrete
internal Pull Low for UMA 2 PANEL_BKEN_GPU [81]
1
C DIS R3716
2K2R2J-2-GP SB-22
[22,34,42,50,51,86] PM_SLP_S3#
KBC_PWRBTN_EC#
64
GPIO01/TB2 GPIO74/SDA2
68 KBC_SDA1
KBC_SCL1
KBC_SDA1 [23] SB-1020 PANEL_BKEN 3 DY +3.3V_RTC_LDO
C
AC_IN_L# R3751 1 100R2J-2-GP
2 AC_IN_R#
95
93
GPIO03 SMB GPIO73/SCL2
67
69
KBC_SCL1 [23]
1 KBC_PWRBTN# 1 2
GPIO06 GPIO22/SDA1 BAT_SDA [44,45] PANEL_BKEN_PCH [20]
[69] LID_CLOSE# LID_CLOSE# 94 70 R3734 100KR2J-1-GP
BAT_SCL [44,45]
2
PCB_VER0 GPIO07 GPIO17/SCL1

119 GPIO23 BAT54C-7-F-GP
SW_UMA_ID 6
1D5V_VGA_ON GPIO24
[87] 1D5V_VGA_ON 109 GPIO30
PCB_VER1 BATT_WHITE_LED +3.3V_RUN
120
GPIO31 SP GPIO66/G_PWM
81 BATT_WHITE_LED [66]
1
PWRLED# 65 +3.3V_RUN
[66] PWRLED# GPIO32/D_PWM
UMA R3729 [66] PWR_BTN_LED# PWR_BTN_LED# 66 U3703
2K2R2J-2-GP KB_BL_CTRL GPIO33/H_PWM TURBO_BOOST_ALERT#1
[68] KB_BL_CTRL 16 GPIO40/F_PWM 2
[43] AD_OFF AD_OFF 17 84 ECSMI#_KBC 4 3 PANEL_BKEN_GPU [81] R3752 10KR2J-3-GP
RSMRST#_KBC GPIO42/TCK GPIO77 A B0 WIRELESS_ON#/OFF 1
[22] RSMRST#_KBC 20 SPI 83 BLUETOOTH_EN [73] 5 2 2
2
PM_SLP_S4# GPIO43/TMS GPIO76/SHBM VCC GND R3740 100KR2J-1-GP

[22,34,50] PM_SLP_S4#
NUM_LOCK_LED#
21
22
GPIO44/TDI GPIO GPIO75
82
91
WIFI_RF_EN [64] [21,54,74] DGPU_SELECT#
6
S B1
1 PANEL_BKEN_PCH [20]
KB_BL_DET# 1 2
[66] NUM_LOCK_LED# GPIO45/E_PWM GPIO81 WIRELESS_ON#/OFF [64]
[22,46] 3V_5V_POK 3V_5V_POK 23 R3750 10KR2J-3-GP
R3706 1 PM_PWROK_R GPIO46/TRST# NC7SB3157P6X-1GP KA20GATE
[22] PM_PWROK 2 24
GPIO47 1ST: 73.03157.C0H 1 2
Remove 0R0402-PAD-2-GP EC_SPI_WP#_R 25 R3743 10KR2J-3-GP
[62] EC_SPI_WP#_R
EC_PWR_SHDN# GPIO50/TDO E51_TxD 2ND: 73.03157.E0J KBRCIN#
HDD_FALL_INT1 26 111 E51_TxD [64] 1 2
BLON_OUT GPIO51 GPO83/SOUT_CR/BADDR1 E51_RxD R3742 10KR2J-3-GP
[54] BLON_OUT 27 113 E51_RxD [64]
R3719 1 IMVP_VR_ON_R GPIO52/RDY# GPIO87/SIN_CR
[47] IMVP_VR_ON 2 28 112 AC_PRESENT_EC [22]
0R0402-PAD-2-GP PSID_DISABLE# GPIO53 GPO84/BADDR0 D3702
[43] PSID_DISABLE# 73
GFX_CORE_EN GPIO70 ECSWI#_KBC S5_ENABLE
[86] GFX_CORE_EN 74 GPIO71 GPIO16 114 PM_LAN_ENABLE [76] K A ECSWI# [25] 1 2
[24] ME_UNLOCK# ME_UNLOCK# 75 14 VTT_PWRGD_G34 1 2 VTT_PWRGD [9,49,52] R3728 10KR2J-3-GP
USB_PWR_EN# GPIO72 GPIO34 BAS16XV2T1G-GP-U KCOL0
[63,76] USB_PWR_EN# 110 GPO82/TRIS# GPIO36 15 S5_ENABLE [42] 1 DY 2
R3714 10KR2J-3-GP
A00-0104-1
SER/IR R3723 A00-0104-1 D3703 SHBM_LCDTST_EN
0R0402-PAD-2-GP ECSCI#_KBC R3717
1 DY 2
10KR2J-3-GP
1ST: 83.01621.01F K A ECSCI# [25]
KBC_VCORF BLUETOOTH_EN
DW VCORF
44 2ND: BAS16XV2T1G-GP-U R3731
1 2
10KR2J-3-GP
07/10 assign GPIO PANEL_BKEN 1 2
1
AGND
1.assign GPIO TUCHPANEL_STP# D3701 R3739 100KR2J-1-GP

GND
GND
GND
GND
GND
GND
C3710 ECSMI#_KBC K A ECSMI# [25]

+3.3V_RUN SC1U10V3KX-3GP
2
NPCE781BA0DX-GP C3710 need place near pin 44. BAS16XV2T1G-GP-U
116
89
78
45
18
5
1AGND 103
R3741
10R2J-2-GP
B B
1
10KR2J-3-GP
A00-0104-1 1 2 U3701B 2 OF 2
KBC_PWR [22] PCH_SUSCLK_KBC
KCOL[0..16] [68]
R3732
R3701 R3730
MB VERSION
2
10KR2J-3-GP 0R0402-PAD-2-GP KBC_XI 77 53 KCOL0
R3733 32KX1/32KCLKIN KBSOUT0/JENK# KCOL1
52
2
KBSOUT1/TCK
ID VER1 VER0 DY 2K2R2J-2-GP 51 KCOL2
2
PCB_VER0 KBSOUT2/TMS KCOL3

SB-34 KBSOUT3/TDI
50
PCB_VER1 Pull High : Switch Board SW_UNSW_ID 79 49 KCOL4
SA 0 0
2 1
SW_UNSW_ID AMP_MUTE# 32KX2 KBSOUT4/JEN0# KCOL5
Pull Low : UnSwitch Board [30] AMP_MUTE# 30 48
GPIO55/CLKOUT KBSOUT5/TDO KCOL6
47
SB 0 1 KBSOUT6/RDY#
1
R3756 [47] IMVP_VR_PWRGD 63 43 KCOL7

GPIO14/TB1 KBSOUT7
10KR2J-3-GP
KCOL8
SC 1 0 2K2R2J-2-GP [22] PM_PWRBTN# 117 GPIO20/TA2 KBC KBSOUT8 42
R3711
R3708 DY DY [54] SHBM_LCDTST_EN SHBM_LCDTST_EN31 41 KCOL9

10KR2J-3-GP GPIO56/TA1 KBSOUT9 KCOL10
[30] KBC_BEEP 32 40
-1 1 1
1
GPIO15/A_PWM KBSOUT10 KCOL11
SB-34 [66] BATT_ORANGE_LED 118 39
2
+3.3V_RUN GPIO21/B_PWM KBSOUT11 KCOL12

[54] LBKLT_CTL_EC 62 38
KBC_PWR GPIO13/C_PWM KBSOUT12/GPIO64 KCOL13
37
KBSOUT13/GPIO63 KCOL14
36
KBSOUT14/GPIO62
1
35 KCOL15
R3738 3.3V_RUN_GPU_EN KBSOUT15/GPIO61/XOR_OUT KCOL16
[87] 3.3V_RUN_GPU_EN 13 34
GPIO12/PSDAT3 GPIO60/KBSOUT16
2
2K2R2J-2-GP [87] 1.05V_GFX_ON 1.05V_GFX_ON 12 33 TP_KCOL171 TP3701

R3727 SCR_LOCK_LED# GPIO25/PSCLK3 GPIO57/KBSOUT17
[66] SCR_LOCK_LED# 11 KROW[0..7] [68]
R3707 2 LCD_TST_R GPIO27/PSDAT2
4K7R2J-2-GP [54] LCD_TST 1 10
KBC CLK
2
0R0402-PAD-2-GP TPDATA GPIO26/PSCLK2 KROW0

[68] TPDATA 71 GPIO35/PSDAT1 KBSIN0 54
Q3709 Q3709_1 TPCLK KROW1
DW [68] TPCLK 72 PS/2 55
1
GPIO37/PSCLK1 KBSIN1
EMI
1
PCLK_KBC MMBT3904-7-F-GP 56 KROW2

KBSIN2
2
07/07 Dummy A00-0104-1 57 KROW3

1.Dummy R3736 CAPA2_INT_R# KBSIN3 KROW4
[78] CAPA_INT# 2 3 58
R3726 EC_SPI_DI KBSIN4 KROW5
DY [62] EC_SPI_DI
EC_SPI_DO
86
F_SDI KBSIN5
59
KROW6
0R2J-2-GP [62] SPI_DIO R3753 1 2 0R2J-2-GP 87 60
EC_SPI_CS# F_SDO KBSIN6 KROW7
[62] EC_SPI_CS# 90 FIU 61
1
EC_SPI_CLK R3735 1 EC_SPI_CLK_C 92 F_CS0# KBSIN7

2 0R2J-2-GP
PCLK_KBC_RC
1ST: 84.03904.H11 [62] EC_SPI_CLK F_SCK

E51_TxD
2ND: 84.03904.L06 ECRST#
85
VCC_POR#
2
+1.05V_VTT KBC_PWR
DY R3736
A 4K7R2J-2-GP
U3704
NPCE781BA0DX-GP A
1
1
DY
1
GND
2
R3737 3 1 2ECRST#
C3704 2K2R2J-2-GP VCC
DY 2
RESET# R3724
1st Samsung
SC4D7P50V2CN-1GP
1
10KR2J-3-GP
C3716
2
G690L293T73UF-GP Wistron Corporation
1
THERMTRIP_GATE 2 1
E
C3707 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY
B
ECRST#_CB SC1U10V3KX-3GP Taipei Hsien 221, Taiwan, R.O.C.

[39,42] PURE_HW_SHUTDOWN# 1 2
2
SCD1U10V2KX-5GP
Title
www.vinafix.vn
E C KBC_THERMTRIP# R3702 Q3702
KBC Nuvoton NPCE781BA0DX
C
[9,25,42] H_THRMTRIP# 0R2J-2-GP CH3906PT-GP
A00-0105-1
Q3701 1ST: 84.03904.P11
CH3904PT-GP
Add reset IC U3704 to prevent SPI ROM data lost Size Document Number Rev
2ND: 84.03904.T11 1ST: 84.03906.H11 Custom
2ND: 84.03906.R11 Winery13 MB DIS A00
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN
SSID = Thermal 25mil
1
1
1
C3910 C3909 R3907
SC4D7U6D3V5KX-3GP SCD1U10V2KX-5GP 10KR2J-3-GP SB-1023
2
EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 [58]
D D
EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE [58]

25mil
RN3901
3 2 +3.3V_RUN
4 1
SRN4K7J-8-GP
DW
07/10 Del THERM_SCL [37,78]
1. Not reserve S5 power source rail for EMC2102 ?? THERM_SDA [37,78]
1. WWAN
1ST: 84.03904.P11 2 1 EMC2102_VDD_3D3
29
28
27
26
25
24
23
22
+3.3V_RUN
2ND: 84.03904.T11 Q3905 must be near WWAN R3908 U3901
49D9R2F-GP
GND
TACH
VDD_5Va
FANa
FANb
VDD_5Vb
SMCLK
SMDATA
2
C3912 must be near Q3905
C3905
SCD1U16V2KX-3GP
E
1
1
C3912
CH3904PT-GP SC470P50V2JN-GP C3914
Q3905
B DY
SC470P50V2JN-GP 1 21
2
VDD_3V NC#21
C3914 must be
C
near EMC2102 EMC2102_DN1 2 20

DN1 GND
EMC2102_DP1 3 19 TP_ALERT# 1 TP3903 TPAD14-GP
DP1 ALERT#
Layout notice: EMC2102
VGA_THERMDC 4 18 CLK_32K
C H_THERMDA, H_THERMDC routing together, DN2 CLK_IN R3906 +3.3V_RUN
GND = Internal Oscillator Selected
C
Trace width / Spacing = 10 / 10 mil VGA_THERMDA 5 17 EMC2102_CLK_SEL 1 2

DP2 CLK_SEL +3.3V = External 32.768kHz Clock Selected
2. GPU Sensor T8_THERMDC 6 16 TP_EM2102_RESET# 1 10KR2J-3-GP
DN3 RESET#
T8_THERMDA 7 15 TP3904 TPAD14-GP
DP3 NC#15
THERMTRIP#
POWER_OK#
SYS_SHDN#
FAN_MODE
[81] VGA_THERMDC
SHDN_SEL
TRIP_SET
1
C3906
SC470P50V2JN-GP
NC#8
1ST: 74.02102.A73
2
GND = Channel 1 2ND: 74.07922.0B3

EMC2102-DZK-GP
OPEN = Channel 3
10
11
12
13
14
[81] VGA_THERMDA
+3.3V = Disabled RN3902
EMC2102_PWROK 3 2 +3.3V_RUN
C3906 must be R3903 EMC2102_THERMTRIP# 4 1
near EMC2102 2 DY 1 EMC2102_SHDN
+3.3V_RUN SRN10KJ-5-GP
DW 10KR2J-3-GP KBC_PWR
07/23 Removed
1
1.Removed SYSTEM Sensor Critical +3.3V_RUN
R3916 R3910
EMC2102_FAN_mode 10KR2J-3-GP +3.3V_RUN
2 DY 1
3. CPU Sensor
1
SYS_SHDN#
SHDN#_G
Layout notice : 0R2J-2-GP
R3917
2
Both VGA_THERMDA and THERMDC routing 10KR2J-3-GP
B 10 mil trace width and 10 mil spacing. R3914 B
1
2
1 2
1
C3901 must be near Q3901 C3902 R3902
G
10KR2J-3-GP Q3903 SCD1U10V2KX-5GP 10KR2F-2-GP
2N7002A-7-GP
2
E
2
2
CH3904PT-GP
S D PURE_HW_SHUTDOWN# [37,42] TRIP_SET Pin Voltage
B DY C3901 C3903 GND = Fan is OFF
Q3901 SC470P50V2JN-GP SC470P50V2JN-GP V_DEGREE V_DEGREE=(((Degree-75)/21)
OPEN = Fan is at 60% full-scale
1
1ST: 84.03904.P11 C3903 must be 1ST: 84.2N702.E31 T8 shutdown is set 86 deg-C.

C
2ND: 84.03904.T11 near EMC2102 +3.3V = Fan is at 75% full-scale 2ND: 84.2N702.D31
1
SC-1204-1
1
3.HW T8 sensor ( CPU ) C3904 R3904
SCD1U10V2KX-5GP 2K37R2F-GP
2
Layout notice :
2
Both DN3 and DP3 routing 10 mil
trace width and 10 mil spacing.
1ST: 84.2N702.E31
DW
32K suspend clock output 07/28 Removed
2ND: 84.2N702.D31 1. Removed U3902 AND gate.
Q3902
2N7002A-7-GP
R3913
A D S CLK_32K_R 1 2 CLK_32K A
[22] PCH_SUSCLK_2102 1st Samsung
10R2J-2-GP
1
DY C3911 Wistron Corporation

G
SC4D7P50V2CN-1GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2
Title
RUN_POWER_ON [42,52]
Thermal/Fan Controllor EMC2102
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
Free Fall Sensor

Note
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
+3.3V_RUN - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
- mount the sensor near the center of mass of the NB as possible as you can
1
C4001 C4002
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP
2
+3.3V_RUN
C C
SA
1
U4001
1
R4004 06/25 Check
1.HDD_FALL_INT1 [ GPIO Table ]??
DY 100KR2J-1-GP
VDD
VDD_IO
2
14 8 HDD_FALL_INT1
+3.3V_RUN [7,18,19,23,64,76] PCH_SMBCLK SCL/SPC INT1 HDD_FALL_INT1 [21]
13 9 FFS_INT2_R +3.3V_RUN +5V_RUN
[7,18,19,23,64,76] PCH_SMBDATA SDA/SDI/SDO INT2
1 2 HDD_FALL_SDO
DY 0R2J-2-GP 12 SDO
R4001
7 CS
1
GND 2
4 R4008
GND
3 RESERVED#3 GND 5 100KR2J-1-GP
11 RESERVED#11 GND 10
1ST: 84.2N702.E31
2
2ND: 84.2N702.D31
D4001
DE351DLTR8-GP S D FFS_INT2_L K A FFS_INT2 [59]
SDM20U30-7-GP
09/0422 Q4001
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild 2N7002A-7-GP
1ST: 83.R2003.08M
2ND:
(#2) FAE/ DY is ok, chip internal pull-up resistors
B B
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b FFS_INT2_R [25]
SB-1023
Pull GND SAD is 0011100b
A A
1st Samsung
Note
(1) Keep all signals are the same trace width. (included VDD, GND). Wistron Corporation
(2) No VIA under IC bottom. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Free Fall Sensor
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
Remove +3.3V_DELAY power rail 2009/05/25
D H_THRMTRIP# [9,25,37] D
E
R4214
1 DY 2 H_PWRGD_R B
[9,25] H_PWRGOOD Q4201
DY
1
1KR2J-1-GP C4208 CHT2222APT-GP
C
DY SCD1U10V2KX-4GP
2
1ST: 83.01621.01F
2ND:
D4201
[46] 3V_5V_EN A K PURE_HW_SHUTDOWN# [37,39]
BAS16XV2T1G-GP-U
1
1 2 S5_ENABLE [37]
R4203 1KR2J-1-GP
DY R4209
200KR2J-L1-GP
2
C C
+3.3V_RTC_LDO
Peak current:5.3A
1
R4201
Design current: 3.7A
100KR2J-1-GP +5V_RUN +5V_ALW
U4201
2
1 S D 8
2 S D 7
R4205 3 S D 6
PS_S3CNTRL RUN_POWER_ON 1 2 10KR2J-3-GP RUN_ON_5V 4 G D 5
[52] PS_S3CNTRL
+15V_ALW AO4468-GP 1ST: 84.04468.037
1
11.6A 2ND: 84.08884.037
C4204
SC6800P25V2KX-1GP Rds=14m ohm
2
3
B Q4202 B
DMN66D0LDW-7-GP R4206
100KR2J-1-GP
Peak current: 8191mA
4
Design current: 5734.6mA

+3.3V_RUN +3.3V_ALW
U4202
1 S D 8
2 S D 7
[22,34,37,50,51,86] PM_SLP_S3# RUN_POWER_ON [39,52]
R4211 3 S D 6
1 2 10KR2J-3-GP RUN_ON_3D3V 4 G D 5
AO4468-GP 1ST: 84.04468.037
1
11.6A 2ND: 84.08884.037
C4203
SCD01U25V2KX-3GP Rds=14m ohm
2
SB-1023
Design current: 1155mA
+1.5V_RUN +1.5V_SUS
U4204
1 S D 8
2 S D 7
R4213 3 S D 6
A G D A
1 214K7R2F-L-GP RUN_ON_1D5VR 4 5 1st Samsung
AO4468-GP
1
C4206
11.6A Wistron Corporation
SCD01U25V2KX-3GP
2
Rds=14m ohm 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1ST: 84.04468.037
Title
2ND: 84.08884.037
Power Plane Enable
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
+5V_ALW
SSID = DCIN
1
PR4306
1
15KR2J-1-GP DY
PR4303
E
10KR2J-3-GP PD4302
1
D PSID_PRO PQ4304 BAV99-4-GP +3.3V_ALW +3.3V_ALW D
B
3
CH3904PT-GP
2
2
PR4301
1
PR4309 PSID_DISABLE#_R 1 DY 2 PSID_DISABLE# [37]
100KR2J-1-GP PR4304
0R2J-2-GP 2K2R2J-2-GP
G
1
PQ4303 PD4301
2
FDV301N-NL-GP BAV99-4-GP
3
PR4302
D S PS_ID 1 2
D
PS_ID_EC [37]
33R2J-2-GP
PR4310
PS_ID_R2 1 DY 2
[76] PS_ID_R2
33R2J-2-GP
SC-1130-1
+DC_IN +DC_IN_SS
pop PC4303 for RF
PU4301
1 S D 8
2 S D 7
1
PC4303 3 S D 6
C C
1
This cap should be used SC1P50V2CN-1GP PC4302 PR4308 4 G D 5 PC4304 PC4305 PC4306 PC4301
only as last resort for 2 SC1U25V5KX-1GP 240KR3-GP SCD01U25V2KX-3GP SCD01U25V2KX-3GP SCD01U25V2KX-3GP SC10U25V6KX-1GP
AO4407A-GP
EMI suppression.
2
2
Id=-12A
PQ4302
PQ4301
R2 Qg=-25nC
DY E
DY 3 OUT AD_OFF_L B R1 Rdson=10~38mohm
1 R1 C AD_OFF_R
[37] AD_OFF
IN 2 GND
R2 PDTA124EU-1-GP
2
DDTC124EUA-7F-GP PR4307
47KR3J-L-GP
1
B B
A A
1st Samsung
Wistron Corporation
Title
DCIN
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = BATT
D
Batt Connecter D
BATT1
GND 11
GND 10
9 1 PR4401
GND2 AFTP4406
GND1 8 2 1 KBC_PW R
7 PBAT_ALARM# 1
BAT_ALERT AFTP4403
6 PRN4401 470KR2J-2-GP
SYS_PRES# PBAT_PRES1# PR4402 1
BATT_PRS# 5 2 100R2J-2-GP SRN100J-3-GP
BAT_IN# [37]
4 PBAT_SMBDAT1 4 1
DAT_SMB PBAT_SMBCLK1 BAT_SDA [37,45]
CLK_SMB 3 3 2 BAT_SCL [37,45]
BATT2+ 2
BATT1+ 1 +PBATT
1
PC4402 PC4401 2 1 BATT_SENSE [45]
FOX-CON9-5-GP SCD1U50V3KX-GP SC2200P50V2KX-2GP
PG4401
2
GAP-CLOSE-PW R-3-GP
1ST: 20.80962.009
2ND: 20.81283.009
C C
PBAT_PRES1# 1 AFTP4401
PBAT_SMBDAT1 1 AFTP4402
PBAT_SMBCLK1 1 AFTP4404
+PBATT 1 AFTP4405
BAT_IN# BAT_SDA BAT_SCL
3
3
PD4401 PD4403 PD4402
BAV99-4-GP BAV99-4-GP BAV99-4-GP
1
2
+3.3V_RTC_LDO
B B
A 1st Samsung A
Wistron Corporation
Title
Batt Connecter
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Charger
+SDC_IN +PWR_SRC
PU4501 PU4502 +PBATT
+DC_IN_SS 8 D S 1 AO4407A-GP
7 D S 2 1 2 1 S D 8
1
6 D S 3 PR4508 2 S D 7
PR4512
D G D01R2512F-4-GP S D
100KR2J-1-GP
5 4 3 6
1
+DC_IN_SS 4 G D 5
AO4407A-GP PG4509 PG4501
2
Id=-12A
10KR2J-3-GP
D GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP D
2
PR4527
PR4513_03
Qg=-25nC
1
Id=-12A
2
Rdson=10~38mohm PR4514
10KR2F-2-GP
+DC_IN_SS Qg=-25nC
PG4503
PG4510
PG4506
PG4512
PR4513
PR4533_02
470KR2J-2-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
1
DY Rdson=10~38mohm
2 1
2
PQ4502_03
1
PR4538
PQ4502_05
0R2J-2-GP PR4524_03
PQ4502
316KR3F-2-GP
1
3 4 PR4524
1
PR4533
0R0402-PAD-2-GP 0R0402-PAD-2-GP
PR4520
BQ24745_ACOK 2 5
2
1 6 CHAGER_SRC
SCD1U50V3KX-GP
A00-0104-1
2
DMN66D0LDW-7-GP 1 2
SC2200P50V2KX-2GP
PC4519
PR4522
PC4545
SCD1U50V3KX-GP
SCD1U25V2ZY-1GP
2
2 1 CHAGER_SRC
SC1U6D3V2KX-GP
0R0402-PAD-2-GP
EC4502
EC4501
CHG_AGND
PC4521
1
PC4520
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
DY
ICREF
SCD1U50V3KX-GP
1
PR4503
PC4528
PC4532
PC4512
PC4546
BQ24745_DCIN BQ24745_CSSP1
33R3J-2-GP
22 28 2
DY DY
2
DCIN CSSP
5
6
7
8
2
SI4800BDY-T1-GP
BQ24745_ACIN 2 SCD1U50V3KX-GP
D
D
D
D
DY DY
PR4502 48K7R3F-1-GP
BQ24745_REF ACIN BQ24745_CSSN CHG_AGND

SCD1U10V2KX-4GP
+3.3V_RTC_LDO 27
2
BQ24745_LDO CSSN
PU4503
BQ24745_ICOUT
2 10KR2F-2-GP
11 26
2
VDDSMB ICOUT
10KR2F-2-GP
PR4534 PD4501
1
1
PR4511
PC4513
CHG_AGND
SCD01U50V2KX-1GP
1
0R0603-PAD-2-GP
C BQ24745_BOOT_1 2BQ24745_BST1 K C
PR4515 25 1 A 1 2
Charger Current=1.4~3.6A
G
S
S
S
BOOT
1
PC4548
PR4528
21 BQ24745_LDO PC4531
DY 0R0402-PAD-2-GP
SB-1103
2
4
3
2
1
BQ24745_ACOK VDDP SD103AWS-1-GP SCD1U50V3KX-GP
1 2 13 ACOK
1. change PL4501 to 68.5R610.201
2
ACAV_IN CHG_AGND BQ24745_CHARGER_UGATE

2
UGATE 24
1
2 1 BAT_SCL_1 10 1 2 PC4517 +VCHGR1 +PBATT
[37,44] BAT_SCL SCL PR4536 PL4501
PG4505 GAP-CLOSE-PWR-3-GP PC4522 SC3300P50V3KX-1GP PR4519
0R0603-PAD-2-GP DY
1
SCD1U50V3KX-GP BQ24745_LX1
15K8R3F-GP
23 1 2 1 2 1 2
2009/08/04
2
PHASE D01R2512F-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2 1 BAT_SDA_1 9 BQ24745_PHASE_GND 1 2
DY [37,44] BAT_SDA SDA DY L-5D6UH-GP
1SMA18AT3G-GP
PR4504
CHG_AGND PG4508 GAP-CLOSE-PWR-3-GP BQ24745_LGATE_1 PC4536
SCD1U50V3KX-GP
20
K
LGATE
5
6
7
8
PC4511
PC4524
PC4530
PC4533
PC4523
SC220P50V2JN-3GP
2
SI4800BDY-T1-GP
1
PG4502
PG4507
PD4502
2009/06/24
D
D
D
D
PR4530
1 2 14 19
[37] AD_IA_KBC NC#14 PGND DY
PU4505
SCD1U50V3KX-GP
0R0402-PAD-2-GP
2
18 BQ24745_CSOP_1
A
CSOP
PC4514
CHG_AGND
2
17
G
S
S
S
BQ24745_VICM CSON
8
SB-1103
4K7R2J-2-GP
4
3
2
1
BQ24745_FBO VICM BQ24745_PR4505
SC220P50V2JN-3GP
1
1
PR4537
PR4539
200KR2F-L-GP
8K45R2F-2-GP
SCD1U50V3KX-GP
1
1 2
PR4506
6 CHG_AGND 1 2 BQ24745_CSOP
FBO PR4505
PC4516
BQ24745_EAI
1BQ24745_FBO1
5 16 0R0402-PAD-2-GP
2
EAI NC#16 PR4532
2
PC4540 BQ24745_EAO 4
PR4526 EAO 0R0402-PAD-2-GP
1
PC4541
1 2SC2200P50V2KX-2GP BQ24745_REF 3 VREF
1
1PR4526_01
2 7K5R2F-1-GP 2 BQ24745_CE 7
2
2 1 1
1
PC4518 PR4510 CE BQ24745_CSON
12 15
DY
GND
GND VFB PR4531

SC150P50V2JN-3GP
SCD1U50V3KX-GP
SCD1U10V2KX-4GP
1 2 0R0402-PAD-2-GP 0R0402-PAD-2-GP
2
2
B B
PC4543
BAT_SENSE 1 2
DY DY BATT_SENSE [44]
2
PC4525 PU4504
DY
29
1
PC4526
SC56P50V2JN-2GP BQ24745RHDR-GP
DY PR4509
2
1
1K8R6J-GP
DY
SCD1U25V2ZY-1GP
2
PC4544
PR4521
1 2
PC4515 PC4537 PC4529 PC4534 0R0402-PAD-2-GP DY DY
SCD1U50V3KX-GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SC1U6D3V2KX-GP
2
2
CHG_AGND
CHG_AGND
CHG_AGND CHG_AGND
This Resistor
must be 1%
tolerance.
+3.3V_RTC_LDO
1
PR4523
100KR2J-1-GP
2
[37] AC_IN#
SCD1U25V3KX-GP
PC4527
1
A PQ4504 A
1st Samsung
2N7002A-7-GP
2
G ACAV_IN
Wistron Corporation
S
2009/6/9 Title
CHARGER BQ24745
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
A B C D E
+3.3V_ALW_2
51125_VCLK
1
PC4602 PC4604
SSID = PWR.Plane.Regulator_3V/5V
SC1KP50V2KX-1GP
PC4603
PR4601 SCD1U25V3KX-GP SCD1U25V3KX-GP
100KR2J-1-GP
2
PD3903_1
PD3904_1
2
51125_ENTRIP
4 4
PQ4601
D
+PWR_SRC +PWR_SRC_3D3V 2N7002A-7-GP 51125_ENTIP1
3
1
1
PG4603
1 2 [42] 3V_5V_EN G PC4605 DY PR4602 PD4603 PD4604
SC18P50V2JN-1-GP
180KR2F-GP BAT54S-5-GP BAT54S-5-GP
2
GAP-CLOSE-PWR
4
PG4605
1
PQ4602 +15V_ALW +5V_PWR
1 2 2009/08/18 PG4610
DMN66D0LDW-7-GP
PD3903_04
GAP-CLOSE-PWR GAP-CLOSE-PWR-3-GP
+3.3V_ALW +3D3V_PWR PG4607
3
PG4602 1 2 1 2 PD3903_2
2 1
GAP-CLOSE-PWR 51125_ENTIP2
1
GAP-CLOSE-PWR PG4609 PC4609
1
SC18P50V2JN-1-GP
PG4604 1 2 SC1U25V3KX-1-GP PC4607
1
2 1 TPS51125 RT8205B PR4603 SCD1U25V3KX-GP
2
1
PC4608
GAP-CLOSE-PWR DY 180KR2F-GP
GAP-CLOSE-PWR PG4635 PR4622 DY ASM PC4606
2
PG4606 1 2 SCD1U25V3KX-GP
2
2 1
GAP-CLOSE-PWR
2009/08/18
2009/10/21 X01
GAP-CLOSE-PWR
2
PG4608
1
2009/08/04
+PWR_SRC_3D3V +PWR_SRC
GAP-CLOSE-PWR PR4622 +PWR_SRC_5V
PG4611 51125_EN 1 2
2 1 DIS(Auburndale) 2009/10/21 X01 820KR2F-GP PC4612 PC4613 2009/10/21 X01
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
Design Current =8.08A
1
GAP-CLOSE-PWR PC4610 PC4627 PC4611 TPS51125:0R3J/63.00000.00L DY TPS51125:0R3J/63.00000.00L
1
1
SCD01U50V2KX-1GP
+5V_PWR +5V_ALW
PG4613 12.69A<OCP<15A RT8205B :4R7/64.4R705.55L RT8205B :4R7/64.4R705.55L
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2 1 DY DIS(Auburndale) PG4614
2
D D PC4614 PC4615 PC4616 1 2
2

8
7
6
5
5
6
7
8
1
GAP-CLOSE-PWR 2009/08/24
D
D
D
D
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
PU4601 PU4602 DY +PWR_SRC +PWR_SRC_5V GAP-CLOSE-PWR
PG4627 10.34A<OCP< 12.22A
16
2 1 SIS412DN-T1-GE3-GP SIS412DN-T1-GE3-GP PG4615
2
3 PU4603 1 2 3
GAP-CLOSE-PWR 2009/08/24 PG4612
VIN
PG4626 PC4617 PR4604 PR4605 1 2 GAP-CLOSE-PWR
G
S
S
S
2 1 SCD1U25V3KX-GP 4D7R3F-L-GP 4D7R3F-L-GP SCD1U25V3KX-GP
S
S
S
G
PG4616
PC4618 G S A00-1218-1 GAP-CLOSE-PWR 1 2
1
2
3
4
4
3
2
1
GAP-CLOSE-PWR S G 2 1 51125_VBST2_1 1 251125_VBST2 9 22 51125_VBST1 1 2 51125_VBST1_1 1 2 PG4624
BOOT2 BOOT1 changePL4602 from 2.2U to 3.3U by power GAP-CLOSE-PWR
PG4630
+3D3V_PWR 2009/08/04 51125_DRVH2 51125_DRVH1 +5V_PWR
1 2
2 1 SB-1103 PL4601 10
UGATE2 UGATE1
21 PL4602 SB-1103 PG4617
+5V_ALW GAP-CLOSE-PWR 1 2
GAP-CLOSE-PWR 1 2 51125_LL2 11 20 51125_LL1 1 2 PG4625
IND-3D3UH-115-GP PHASE2 PHASE1 IND-3D3UH-57GP GAP-CLOSE-PWR
PG4634 1 2
1
2 1 PC4619 PTC4603 PTC4601 D 51125_DRVL2 12 19 51125_DRVL1 PG4619

LGATE2 LGATE1
1
1
DY DY D GAP-CLOSE-PWR 1 2
8
7
6
5
5
6
7
8
ST100U6D3VBM-5GP
ST220U6D3VDM-15GP
GAP-CLOSE-PWR PG4618 PR4606 PG4628

DY DYPR4607
D
D
D
D
SCD1U10V2KX-4GP
D
D
D
D
51125_VO2 51125_VO1
151125_LL2_R
2D2R5F-2-GP PU4604 7 24 PU4605 PG4620 PTC4602 PTC4604 PC4601 1 2 GAP-CLOSE-PWR

2
VOUT2 VOUT1
1
1
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
151125_LL1_R
2009/08/04 2D2R5F-2-GP PG4601
DY DY
2
SI7716ADN-T1-GE3-GP
SI7716ADN-T1-GE3-GP
GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-15GP
ST100U6D3VBM-5GP
51125_FB2 5 2 51125_FB1 GAP-CLOSE-PWR 1 2
2
FB2 FB1
PG4629
2
1 2 GAP-CLOSE-PWR
2
2
G
S
S
S
2 51125_EN 3V_5V_POK
S
S
S
G
1 13 23 PG4621
PR4608 DY820KR2F-GP EN PGOOD
G S GAP-CLOSE-PWR 1 2
1
2
3
4
4
3
2
1
PC4620 S G 51125_ENTIP2 6 1 51125_ENTIP1 PG4631
SC330P50V3KX-GP 51125_VREF ENTRIP2 ENTRIP1 PC4621 GAP-CLOSE-PWR
1 2
DY DY
2
3 15 SC560P50V-GP PG4622
2
REF PGND GAP-CLOSE-PWR 1 2
1
SCD22U10V2KX-1GP
PC4622
51125_TONSEL 4 25 PG4633
TONSEL GND GAP-CLOSE-PWR
1 2
1
PR4611 PG4632
2
1
14 18 51125_VCLK 0R2J-2-GP SC-1130-1 GAP-CLOSE-PWR 1 2

SKIPSEL LG1_CP
1
PR4610 2009/10/21 X01 51125_SKIPSEL DY change PC4601 pull up to +5V_ALW for layout.
PR4609 DY 0R2J-2-GP PR4612 GAP-CLOSE-PWR
VREG3
VREG5
6K65R2F-GP TPS51125:DY RT8205BGQW-GP 33KR2F-GP
1 2
RT8205B :ASM 51125_FB1_R
2
1 2
51125_FB2_R
2
PC4624 PC4623 DY
3D3V_AUX_S5_5_51125 8
17
+3.3V_RTC_LDO
DYSC18P50V2JN-1-GP +5V_ALW2 SC18P50V2JN-1-GP
2
+3.3V_ALW_2
2
PG4623
1
PR4616 1 2
1
2
0R0402-PAD-2-GP PR4614 PR4615 2
PR4613 1 2 GAP-CLOSE-PWR-3-GP 100KR2J-1-GP 21K5R2F-GP
51125_VREF
10KR2F-2-GP
PR4617 Close to VFB Pin (pin2)
2
+3.3V_ALW_2 2 DY 1 2009/10/21 X01 3V_5V_POK [22,37]
2
SC22U6D3V5MX-2GP
0R2J-2-GP
PC4625
PC4628
51125_VREF 2 DY PR4618
1
1
0R2J-2-GP TPS51125:ASM PC4626

PR4619
SC4D7U10V5KX-4GP
Close to VFB Pin (pin5) 0R0402-PAD-2-GP RT8205B :DY

SC10U10V5KX-2GP
+3.3V_ALW_2 1 2
2
2 DY PR4621
1
0R2J-2-GP I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
A00-1218-1
Inductor: 2.2uH PCMC063T-2R2MN Cyntec 20 mohm Isat =14Arms 68.2R210.20B
pop PR4619; dummy PR4618 by power to improve +15V_Pump Power on issue
+3.3V_ALW_2 +3.3V_RTC_LDO O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
PR4620 O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
0R0402-PAD-2-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L 1 2 H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
Inductor: 3.3UH PCMB104T-3R3MS Cyntec 11.8mohm Isat =16Arms 68.3R310.20C L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: SiS412DN 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S: Si7716ADN 13.5mOhm/16.5mOhm@4.5Vgs/ 84.06690.E37
TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND
GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
Mode PWM only
VREF 245kHz 305kHz
VREG3 300kHz 375kHz
VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND
1
Operating 1
Mode enable both enable both LDOs, disable all
LDOs, VCLK on VCLK off and circuit
and ready to ready to turn on
turn on switcher channels
switcher 1st Samsung
channels
Wistron Corporation
Title

RT8205B_5V/3D3V Rev
Custom Winery13 MB DIS A00
A B C D E
www.vinafix.vn
5 4 3 2 1
SSID = PWR.Plane.Regulator_CPU Core

PM_DPRSLPVR [12] +5V_ALW
[7] VR_CLKEN#
IMVP_VR_ON [37]
PR4736
0R0402-PAD-2-GP +PWR_SRC
CPU_VID[6..0] [12] 1 2
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
2
SC1U10V2KX-1GP
+3.3V_RUN
PC4735
PC4737 PC4738 PC4733 PC4734
1
BOOT3 1 2 6208_PHASE3
6208_FCCM
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
+PWR_SRC PR4735
D 2D2R3J-2-GP D
2
2
5
6
7
8
PU4702
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
0R0402-PAD-2-GP
D
D
D
D
5
1
PC4736
SIS406DN-T1-GE3-GP
SCD22U16V3KX-1-GP
BOOT
VCC
1
1
TC4702
DY
2
SE100U25VM-10GP
2 7 PHASE3
2
PW M PHASE
S
S
S
UGATE3
6208_PWM
G
UGATE 8
PR4747 4 LGATE3
4
3
2
1
1K91R2F-1-GP LGATE
6 FCCM
GND
GND
1
62883_DPRSLPVR 1
1
PR4744
PR4745
PR4737
PR4738
PR4746
PR4739
PR4740
PR4741
PR4742
PR4743
UGATE3
L4701
2
+VCC_CORE
62883_CLK_EN#
SC-1204-4 PU4705 ISL6208CRZ-TGP-U
9
3
62883_VR_ON
remove TC4701 for layout PHASE3 1 2
62883_VID6
62883_VID5
62883_VID4
62883_VID3
62883_VID2
62883_VID1
62883_VID0
ST330U2VDM-4-GP
ST330U2VDM-4-GP
1
DY IND-D36UH-24-GP-U
1
PTC4701
PTC4702
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
5
6
7
8
PU4703 PR4701
D
D
D
D
+3.3V_RUN 2D2R5F-2-GP
2
1
1
SIS402DN-T1-GE3-GP
SNUBBER32
1
PG4713
PG4714
40
39
38
37
36
35
34
33
32
31
1
PU4701 PR4750
PR4749 0R0402-PAD-2-GP
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
2
+1.05V_VTT 1K91R2F-1-GP
S
S
S
G
+5V_ALW
4
3
2
1
PR4753 2009/07/29
2
1
1
2 62883_PGOOD 1 BOOT2 0R2J-2-GP
+VCC_CORE_PHASE3
1 PGOOD BOOT2 30 BOOT2 [48]
PR4751 [37] IMVP_VR_PWRGD PR4748 0R0402-PAD-2-GP LGATE3 PC4701
2 1 DY
PHASE3_R
68R2-GP 1 2 62883_PSI# 2 29 UGATE2 SC560P50V-GP
[12] PSI# UGATE2 [48]
2
PSI# UGATE2
1
PR4752 0R0402-PAD-2-GP
C 62883_AGND 1 2 62883_RBIAS 3 28 PHASE2
PHASE2 [48] PR4755 DY C
2
RBIAS PHASE2 0R3J-0-U-GP

NTC 470K close to H/S MOSFET of Phase1 PR4754 147KR2F-GP
4 27 ISEN3 1 2
[9] H_PROCHOT# VR_TT# VSSP2 PR4756 51KR2F-L-GP
2
6266A_NTC_R 2009/07/29 62883_NTC LGATE2 VSUM+ 2009/07/29
62883_AGND
1
PR4757 DY 2 1 DY 2PR4758
NTC-470K-8-GP
5 NTC LGATE2 26 LGATE2 [48] 1
PR4759
2
3K65R3F-GP
4K02R2F-GP 1 62883_VW 62883_VCCP VSUM-
62883_AGND DYSCD01U25V2KX-3GP
2 6 VW VCCP 25 1
PR4760
2
1R2F-GP
PC4739 1 2 62883_COMP 7 24 62883_PWM3 PC4741 PC4742 ISEN1 1 2
COMP PW M3/LGATE1#
1
SC1U10V2KX-1GP
PR4761 PR4762 51KR2F-L-GP
SC1U10V2KX-1GP
8K06R2F-GP 62883_FB 8 23 LGATE1 ISEN2 1 2
FB LGATE1 LGATE1 [48]
PR4763 51KR2F-L-GP
2
1 2 ISEN3 9 22
PC4740 ISEN3/FB2 VSSP1
SC1000P50V3JN-GP-U ISEN2 10 21 PHASE1 PHASE1 [48]
PC4743 ISEN2 PHASE1
UGATE1
SCD22U25V3KX-GP
1 1 PC4745
BOOT1
ISUM+
ISEN1
ISUM-
SCD22U25V3KX-GP
VSEN
IMON
41
VDD
RTN
GND
VIN
2 2
1 DY 2 1 2
2
62883_AGND PR4764 PC4744
0R2J-2-GP SC33P50V2JN-3GP ISL62883HRTZ-T-GP PC4746
11
12
13
62883_ISUM- 14
15
16
17
18
19
20
VSUM-
VSUM-
62883_AGND SCD22U16V3KX-1-GP 2009/07/29
1
UGATE1
UGATE1 [48]
ISEN3 262883_COMP_R 1 ISEN1
1 DY 2 1 2
62883_VDD
Intel support POC (power on current).

62883_VIN
VSUM+
PC4747 PC4748 PR4766 62883_BOOT1 1 PR4767 2 BOOT1_PHASE1

SC22P50V2JN-4GP SC150P50V2JN-3GP 324KR2F-GP 2009/07/29 PC4749 1 IMVP_IMON 2D2R3J-2-GP
+PWR_SRC
IMVP_IMON [12]
SCD22U25V3KX-GP2
SCD22U25V3KX-GP 2 1 2 PR4794 +1.05V_VTT
VSUM-
PR4768 0R0402-PAD-2-GP 1 DY 2 +1.05V_VTT

62883_FB_VSEN +5V_ALW 100KR2F-L1-GP
1
PR4781
1 2 PC4750
B PC4751 1R2F-GP SCD22U10V2KX-1GP B
1
6K65R2F-GP
1 2 1 2 PC4752 PC4753 PR4769 PR4770 PR4771 PR4772 PR4773 PR4774 PR4775 PR4776 PR4777 PR4778
1
SC1U10V2KX-1GP
SCD22U25V3KX-GP
PR4779 PR4797
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
562R2F-GP SC390P50V2KX-GP 0R0402-PAD-2-GP
2
2
1 2 VCC_SENSE_L 1 2 2009/07/29 DY DY DY DY
PR4780 1K91R2F-1-GP VSS_SENSE [12]
2009/07/29
2
62883_AGND 62883_AGND
CPU_VID0
VSUM+ [48]
CPU_VID1
1
1
PC4756 PC4757 CPU_VID2
ISEN1 PC4754 PR4782 PR4783 SB-1103 CPU_VID3
[48] ISEN1
2
SC330P50V2KX-3GP 82D5R2F-1-GP 1K5R2F-2-GP CPU_VID4

1. change PR4783 to 64.15015.6DL
2
SCD1U16V3KX-3GP
SCD047U16V2KX-1-GP
ISEN2 CPU_VID5
11KR2F-L-GP
[48] ISEN2
1
2. change PR4796 to 64.20515.6DL

PR4784
CPU_VID6
1VSUM_RR
VSUM_RC 2
[48] ISEN3
ISEN3 3. change PC4756 to 78.10421.2BL PM_DPRSLPVR
62883_AGND PSI#
[12] VCC_SENSE
4. change PC4757 to 78.47321.2FL
PR4785 PR4786 PR4787 PR4788 PR4789 PR4790 PR4791 PR4792 PR4793
2
1
1
PC4759
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
1KR2J-1-GP
SC330P50V2KX-3GP PR4795
2
PC4758 NTC-10K-26-GP
DY DY DY DY DY
2
[12] VSS_SENSE SCD01U25V2KX-3GP

1
2
1 2 VSUM-
VSUM- [48]
1
PC4760 PR4796 2K05R2F-GP NTC 10K close to Choke of Phase1

SC1000P50V3JN-GP-U
1
PC4762
2
SCD1U25V3KX-GP
SC-1130-1 62883_AGND
2
A 62883_AGND change PC4762 to 0603 size A

1st Samsung
62883_AGND
PR4798
GAP-CLOSE-PWR-3-GP Wistron Corporation
1 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
62883_AGND ISL62883_CPU_CORE_1/2
Custom
Winery13 MB DIS A00
www.vinafix.vn
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_CPU Core

+PW R_SRC
PC4863 PC4864 PC4865 PC4866
1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
2
2
D D
5
6
7
8
PU4801
D
D
D
D
SIS406DN-T1-GE3-GP
DIS(Auburndale)
Design Current = 34A
Peak Current=48A
S
S
S
G
57.6A<OCP< 67.2A
4
3
2
1
L4801
UGATE2 +VCC_CORE
[47] UGATE2
PHASE2 1 2
[47] PHASE2
ST330U2VDM-4-GP
IND-D36UH-24-GP-U
1
PTC4802
PTC4801
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
5
6
7
8
BOOT2 1 2B00T2_R 1 2 PU4803
[47] BOOT2 DYPR4815
D
D
D
D
ST330U2VDM-4-GP
PR4812 PC4867
2
1
1
SIS402DN-T1-GE3-GP
2D2R3J-2-GP SCD22U16V3KX-1-GP 2D2R5F-2-GP
1SNUBBER2
PG4801
PG4802
2
2
S
S
S
4 G
3
2
1
2009/07/28
PC4802
LGATE2 SC560P50V-GP
PHASE2_R
DY
+VCC_CORE_PHASE2
2
[47] LGATE2
C C
ISEN2 1 2
[47] ISEN2 PR4801 51KR2F-L-GP
VSUM+ 1 2 2009/07/28
[47] VSUM+ PR4802 3K65R3F-GP
VSUM- 1 2
[47] VSUM- PR4803 1R2F-GP
ISEN1 1 2
ISEN3 1 2
+PW R_SRC
1
1
PC4868 PC4869 PC4870 PC4871
SCD1U50V3KX-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
2
5
6
7
8
PU4802
D
D
D
D
SIS406DN-T1-GE3-GP
S
S
S
G
B B
4
3
2
1
L4802
UGATE1 +VCC_CORE
[47] UGATE1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
PHASE1 1 2
[47] PHASE1 Inductor: 0.36UH ETQP4LR36WFC PANASONIC 1.1mohm/ 68.R3610.20A
O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L
IND-D36UH-24-GP-U
1
1
PTC4803 PTC4804 O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L
DYPR4816 H/S: SiR474DP/ POWERPAK-8/ 10mOhm/12mOhm @4.5Vgs/ 84.00474.037
5
6
7
8
ST330U2VDM-4-GP
SE220U2VDM-12GP
PU4804
2
2
D
D
D
D
2D2R5F-2-GP L/S: Si7170DP/ POWERPAK-8/ 3.6mOhm/4.3mohm@4.5Vgs/ 84.07170.037

GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
SIS402DN-T1-GE3-GP
1SNUBBER1
Freq=300KHz@PER PHASE
2
1
PG4803
PG4804
S
S
S
LGATE1
G
[47] LGATE1
2009/07/28
4
3
2
1
PC4803
SC560P50V-GP
DY
2
+VCC_CORE_PHASE1
PHASE1_R
2009/07/28
ISEN1 1 2
VSUM+ 1 2 2009/07/28
[47] VSUM+ PR4808 3K65R3F-GP
A A
VSUM- 1 2 1st Samsung
[47] VSUM- PR4809 1R2F-GP
ISEN2 1 2
[47] ISEN3
ISEN3 1 2 Wistron Corporation
PR4811 51KR2F-L-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
ISL62883_CPU_CORE_2/2
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D05V_VTT
D
+PWR_SRC +PWR_SRC_1D05V TPS51218 for +1.05V_VTT D
PG4902
1 2
GAP-CLOSE-PWR
PG4903
1 2
+PWR_SRC_1D05V
GAP-CLOSE-PWR
PG4904
1 2
GAP-CLOSE-PWR +1.05V_VTT_P +1.05V_VTT +1.05V_VTT_P +1.05V_VTT
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PG4905
1 2 PG4908 PG4909
2
DIS(Arrandale 1.05V_VTT) 1 2 1 2
PC4924
PC4909
PC4903
PC4904
PC4902
PC4905
GAP-CLOSE-PWR
PG4906 Design Current = 22.75A GAP-CLOSE-PWR GAP-CLOSE-PWR
1
5
6
7
8
5
6
7
8
1 2 PU4902 PU4905 31.28A<OCP<36.96A PG4910 PG4901
D
D
D
D
D
D
D
D
1 2 1 2
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
GAP-CLOSE-PWR
2009/08/24 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR
PG4911 PG4912
1 2 1 2
S
S
S
S
S
S
2009/08/18 SB-24
G
[9,37,52] VTT_PWRGD
PU4901 PC4906 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
4
3
2
1
4
3
2
1
PR4901 SCD1U25V3KX-GP PG4913 PG4914
PR4902 1 11 2D2R3J-2-GP 1 2 1 2
51218_VTT_TRIP PGOOD GND 51218_VBST_VTT 1
1 2 2 TRIP VBST 10 251218_VBST_VTT1 2 1 PL4901
80K6R2F-GP 51218_VTT_EN 3 9 51218_DRVH_VTT +1.05V_VTT_P GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
51218_VTT_VFB EN DRVH 51218_SW_VTT PG4915 PG4916
C 4 VFB SW 8 1 2 C
PR4921 1 2 51218_VTT_CCM 5 7 +5V_ALW IND-D56UH-12-GP 1 2 1 2
[50,51] RUNPWROK CCM V5IN
SC4D7U6D3V5KX-3GP
SCD1U10V2KX-4GP
0R0402-PAD-2-GP 6 51218_DRVL_VTT PC4901 PC4910 PTC4902 PTC4901 PTC4903
DRVL
1
1
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
PC4908 PR4904
DY 2D2R5J-1-GP DY PG4917 PG4918
1
1
PC4907
PR4903 TPS51218DSCR-GP-U1 SC1U10V2KX-1GP PG4921

SC1KP50V2KX-1GP
1 2 1 2
2
470KR2F-GP
5
6
7
8
5
6
7
8
PU4903 PU4904 2009/08/05 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
2
151218_SW_GND_VTT 2
D
D
D
D
D
D
D
D
SB-24 PG4919 PG4920
1+1.05V_VTT_VOUT 2
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
1 2 1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
PG4925 PG4927
1
DY 2 VTT_SENSE [12]
S
S
S
S
S
S
G
G
1 2 1 2
PR4912
SC330P50V2KX-3GP
4
3
2
1
4
3
2
1
10R2J-2-GP GAP-CLOSE-PWR GAP-CLOSE-PWR
PG4926 PG4928
+3.3V_RUN 1 2 1 2
PC4911
PR4905 GAP-CLOSE-PWR GAP-CLOSE-PWR
DY 10KR2F-2-GP R1 PG4933 PG4923
2
+3.3V_ALW
Vout=0.704V*(R1+R2)/R2 1 2 1 2
2
GAP-CLOSE-PWR GAP-CLOSE-PWR
1
PG4934 PG4944
1
PR4908 1 2 1 2
PR4907 100KR2J-1-GP
10KR2J-3-GP 51218_VTT_VFB GAP-CLOSE-PWR GAP-CLOSE-PWR
PG4939 PG4930
PQ4901
2
1 2 1 2
2
1 6
B GAP-CLOSE-PWR GAP-CLOSE-PWR B
1
VTT_PWRGD 2 5 H_VTTPWRGD_R
+1.05V_VTT PR4906
19K6R2F-GP
R2
3 4
1
PC4912
1
SCD1U25V3KX-GP
DY
2
DMN66D0LDW-7-GP PR4909
2
1KR2J-1-GP SB-1104
2
H_VTTPWRGD
H_VTTPWRGD [9]
SB-04
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
Frequency setting O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
470K -->290KHz L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
200K -->340KHz
100K -->380KHz
A
39K -->430KHz A
1st Samsung
Wistron Corporation
Title
TPS51218_+1.05V_VTT
Custom
Winery13 MB DIS A00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
SB-1020-1
DY PR5012
SSID = PWR.Plane.Regulator_1D5V/0D75V
+5V_ALW PR5012 1 2 0R2J-2-GP 0D75V_EN
[22,34,37,42,51,86] PM_SLP_S3# DY 0D75V_EN [52]
PR5006
1
5D1R3J-GP
SB-1103 +5V_ALW
D D
2
PR5007 1 TPS51116_VDD
2 DW
1
+5V_ALW
SC1U10V3KX-3GP
13KR2F-GP
07/08 Del PC5001
DY
1
1. Not reserve 1.5V_RUN_EN ??
PC5019
2009/08/05 1 2 SCD1U10V2KX-4GP
2
1
SC1U10V3KX-3GP
1
PC5003 PC5018
2
+3.3V_ALW SC1KP50V2KX-1GP PD5001
+PWR_SRC_1D5V
DY
CH551H-30PT-GP
2009/08/05
2
TPS51116_VDD_R
2
16
14
15
PR5004 PU5002 +PWR_SRC +PWR_SRC_1D5V
20KR2F-L-GP PG5002
VDDP
VDDP
ILIM
PR5003
2 1 PR5014 1 2 1D5V_EN
[22,34,37] PM_SLP_S4#
22 TPS51116_VBST 1 2 TPS51116_VBST1 0R0402-PAD-2-GP
1
BST GAP-CLOSE-PWR
[49,51] RUNPWROK 13
PGD
1
0R3J-0-U-GP PG5004
PR5011 1 DY 2 620KR2F-GP TPS51116_NC#12 12 21 TPS51116_UGT 2 1 PC5022
NC#12 DH DY SCD1U10V2KX-4GP
2
1D5V_EN 11 GAP-CLOSE-PWR
EN/PSV PG5006
0D75V_EN 10 20 TPS51116_PHS 2 1 +1.5V_SUS_P +1.5V_SUS
RT: Non_ASM VTTEN LX PG5001
TI: ASM 23 GAP-CLOSE-PWR 1 2
+1.5V_SUS_P VTTIN PG5008
1
19 TPS51116_LGT 2 1 GAP-CLOSE-PWR
PC5002 DL PG5003
7
C +5V_ALW SC1U10V3KX-3GP NC#7 GAP-CLOSE-PWR C
1 2
2
PR50011 2 1M1R2J-GP TPS51116RGER-GP-U

DY 1 18 GAP-CLOSE-PWR
+1.5V_SUS_P PGND2 PGND1 PG5005
PGND1 17
PR5002 1 0R0402-PAD-2-GP
2 TPS51116_TON 4 1 2
TON TPS51116_VDDQSNS
VDDQS 8
2
2009/08/05 GAP-CLOSE-PWR
PC5017 24 9 TPS51116_VDDQSET PG5007
SC1KP50V2KX-1GP DY VTT FB
1 2
1
+0D75V_DDR_P 2 +5V_ALW PR5005

VTTS +PWR_SRC_1D5V GAP-CLOSE-PWR
6 1 2
VCCA DY
VSSA
PG5009
GND
REF
0R2J-2-GP 1 2
1
DIS(Auburndale)
DY PC5020 GAP-CLOSE-PWR
25
+V_DDR_REF SC1U10V3KX-3GP Design Current = 11.82A PG5011
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
PC5007
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
18.57A<OCP<21.95A 1 2
1TPS51116_REF
PC5035
PC5004
PC5005
PC5006
1 PR5013 2
1
0R0603-PAD GAP-CLOSE-PWR
PG5012
5
6
7
8
5
6
7
8
PU5003 PU5009 1 2
2
D
D
D
D
D
D
D
D
Design Current = 0.7A
SIS406DN-T1-GE3-GP
SIS406DN-T1-GE3-GP
GAP-CLOSE-PWR
PG5013
PC5021 DY 1 2
+0D75V_DDR_P SCD033U16V3KX-GP
2
S
S
S
S
S
S
GAP-CLOSE-PWR
G
PG5019
4
3
2
1
4
3
2
1
1 2
B +0D75V_DDR_P +0.75V_DDR_VTT +1.5V_SUS_P B
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
PC5008
PC5009
PC5010
PC5011
SCD1U10V2KX-4GP
PG5014 TPS51116_UGT GAP-CLOSE-PWR

PL5001
1
1 2 PG5020
TPS51116_VBST1 1 2 TPS51116_PHS 1 2 1 2
GAP-CLOSE-PWR
2
PG5015 PC5012 IND-1D5UH-34-GP GAP-CLOSE-PWR
SC4D7U6D3V5KX-3GP
1
SCD1U10V2KX-4GP
1 2 SCD1U25V3KX-GP PG5021
PC5013
PC5014
PTC5001 PTC5002 1 2
5
6
7
8
5
6
7
8
1
GAP-CLOSE-PWR PU5001 PU5008 PR5008
DY DY
D
D
D
D
D
D
D
D
SE220U2VDM-8GP
SE220U2VDM-8GP
PG5016
2D2R5F-2-GP GAP-CLOSE-PWR
SIS402DN-T1-GE3-GP
SIS402DN-T1-GE3-GP
PG5022
GAP-CLOSE-PWR-3-GP
2
2
1 2
DY
1
TPS51116_LGT TPS51116_PHS_SET 2009/08/18 GAP-CLOSE-PWR
1
S
S
S
S
S
S
State S3 S5 VDDR VTTREF VTT
G
DY PC5015
4
3
2
1
4
3
2
1
S0 Hi Hi On On On SC330P50V3KX-GP
2
TPS51116_VDDQSNS
S3 Lo Hi On On Off(Hi-Z)
SB-1104
1
S4/S5 Lo Lo Off Off Off
1
PR5009
30K9R2F-GP DY PC5016
SC18P50V2JN-1-GP
2
2
TPS51116_VDDQSET
1
VDDQSET VDDQ (V) VTTREF and VTT NOTE
A 1st Samsung A
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PR5010
GND 2.5 VVDDQSNS/2 DDR 30KR2F-GP
Wistron Corporation
2
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L0 Close to VFB Pin (pin5)
V5IN 1.8 VVDDQSNS/2 DDR2 H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
FB Resistors Adjustable VVDDQSNS/2 1.5 V < VVDDQ < 3 V Switching freq-->400KHz Title
TPS51116_+1.5V_SUS
Custom
Winery13 MB DIS A00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D8V
APL5930 for +1.8V_RUN +3.3V_ALW
D PG5102 D
2 1
+5V_ALW GAP-CLOSE-PW R
PG5103
2 1
SC1U10V3KX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
1
PC5102
PC5104
PC5103
GAP-CLOSE-PW R
DY DIS(Arrandale) +1.8V_RUN_P +1.8V_RUN
2
PG5104
1 2
6
PU5102
GAP-CLOSE-PW R
VCNTL
1D8V_VIN PG5105
[49,50] RUNPW ROK 7 POK VIN#5 5
9 +1.8V_RUN_P
2009/07/29 1 2
R5102 VIN#9
[22,34,37,42,50,86] PM_SLP_S3# 1 21D8V_RUN_EN 8 EN VOUT#3 3 GAP-CLOSE-PW R
SC22U6D3V5MX-2GP
0R0402-PAD-2-GP 4
VOUT#4
SC68P50V2JN-1GP
PC5106
PC5107
SC22U6D3V5MX-2GP
1
1
PR5104
15KR2F-GP
PC5108
2
DY
GND
FB
2
5912_1.8V_RUN_FB
APL5930KAI-TRG-GP
2
SO-8-P
1
C C
PC5105
10KR2J-3-GP
2
Vout=0.8V*(R1+R2)/R2
1
PR5105
12KR2F-L-GP
A00-0107-3
change R5102 to short pad, PC5105 to 10K for power's suggestion
2
To prevent PM_SLP_S3# signal rebound 2009/07/29
RT9025 for +1.8V_RUN_GPU +3.3V_ALW
PG5109
1 2
GAP-CLOSE-PW R
PG5106
+3D3V_1D8_LDO 1 2
DIS:
1
DY GAP-CLOSE-PW R
B PC5111
SC10U10V5KX-2GP
PC5109
SC10U10V5KX-2GP
Peak current:300mA B
2
Design current:210mA
+1.8V_PW R +1.8V_RUN_GPU
PG5108
PU5103 1 2
DGPU_1D8V_PGOOD 1 8 GAP-CLOSE-PW R
[23,25] DGPU_1D8V_PGOOD PGOOD GND
1 2 RT9025_EN 2 7 PG5107
[37] 1.8_GFX_ON PR5106 EN ADJ
3 VIN VOUT 6 1 2
0R0402-PAD-2-GP 4 5
GND
VDD NC#5
1
1
PC5113 PC5114 PC5110 GAP-CLOSE-PW R
PC5115 PR5107
DY
SC100P50V2JN-3GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SCD1U10V2KX-4GP RT9025-25PSP-GP 15KR2F-GP
2
2
2
RT9025_FB
1
+5V_ALW
PR5108
12KR2F-L-GP
1
PC5112
SC1U16V3KX-2GP 2
Vo=0.8*(1+(R1/R2))
2
A A
1st Samsung
Wistron Corporation
Title
APL5930/RT9205
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Switch_1D5V CPU
SB-1020-1 +0.75V_DDR_VTT
D D
DY R5215, R5222, R5223; POP R5221, C5210, R5226, R5210, Q5203, R5211.
1
R5211
22R2J-2-GP
Q5204_D 2
R5210
1 2 0D75V_EN
[9,37,49] VTT_PWRGD 0D75V_EN [50]
100KR2J-1-GP
D
Q5203 Q5204
2N7002A-7-GP
PS_S3CNTRLG PS_S3CNTRL G
[42] PS_S3CNTRL 2N7002A-7-GP
1ST: 84.2N702.E31 1ST: 84.2N702.E31
S
2ND: 84.2N702.D31 2ND: 84.2N702.D31
C C
Calpella Platform S3 Power Reduction Platform
S3 Power Reduction CRB Implementation
Design Details
Revision 0.1
MAX Current 3000 mA

DW
07/07 Added +1.5V_CPU
Design Current 2100 mA 1.Added discharge circuit
+1.5V_CPU: +1.5V_SUS +1.5V_CPU
1
R5226
221R2F-2-GP
A00-1223-1
Q5202_D 2
remove R5215, R5222, R5223 for cost down
D
Rds(on) = 4.7 mOhm (Max) Q5202
2N7002A-7-GP
PS_S3CNTRL G
Q5205
8 D S 1
B 7 D S 2 1ST: 84.2N702.E31 B
S
6 D S 3 A00-1223-1
D
2ND: 84.2N702.D31
5 G 4 change Q5205 from 84.03420.031 to 84.00460.037
1
SIR460DP-T1-GE3-GP
C5210
SC10U6D3V5KX-1GP
2
1ST: 84.00460.037
R5221
2ND:
10KR2J-3-GP
RUN_POWER_ON 1 2 1.5V_CPU_ENABLE
[39,42] RUN_POWER_ON
1
C5209
A00-1223-1 SCD01U50V2KX-1GP
2
change R5221 to 10K; remove R5225 for cost down
DW
07/20 corrected
1. Removed C5288
2. RemovedQ5207,R5225,R5220 to save more part counts
A A
1st Samsung
Wistron Corporation
Title
DC to DC 1D5V
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = CPU.GFX.Regulator
D SC-1208-1 D
+PWR_SRC +PWR_SRC_CPU_GFXCORE change PR5311 from 4D7K to 470R +5V_ALW
PG5302 PR5302 1 2 0R0402-PAD-2-GP 3211_VID6

[13] GFX_VID6
1 2
PR5303 1 2 0R0402-PAD-2-GP 3211_VID5
[13] GFX_VID5
GAP-CLOSE-PWR
PG5303 PR5304 1 2 0R0402-PAD-2-GP 3211_VID4
[13] GFX_VID4
1 2
1
PR5305 1 2 0R0402-PAD-2-GP 3211_VID3
[13] GFX_VID3
GAP-CLOSE-PWR
PG5305 PR5307 1 2 0R0402-PAD-2-GP 3211_VID2 PR5306
[13] GFX_VID2 10R3J-3-GP
1 2
PR5308 1 2 0R0402-PAD-2-GP 3211_VID1
[13] GFX_VID1
2
GAP-CLOSE-PWR
PG5307 PR5309 1 2 0R0402-PAD-2-GP 3211_VID0
[13] GFX_VID0 +PWR_SRC_CPU_GFXCORE
1 2
PR5301 1 2 10KR2J-3-GP
GAP-CLOSE-PWR
+1.05V_VTT DY
PG5309 PR5310 1 2 0R0402-PAD-2-GP 3211_GFX_VR_EN
[13] GFX_VR_EN
1 2
SC1U10V2KX-1GP
1
GAP-CLOSE-PWR +1.05V_VTT PR5311
1
470R2J-2-GP PC5305 PC5303 PC5304 PC5306
5
6
7
8
1
PC5301
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD01U25V2KX-3GP
PU5302
2
PR5312 SI7686DP-T1-GP
2
DY 10KR2J-3-GP +3.3V_ALW
GND_3211_I UMA
GND_3211_I
Thermal Design Current = 12A
G
S
S
S
32
31
30
29
28
27
26
25
[13] GFX_IMON PR5313 PU5301 Max. Current = 22A
4
3
2
1
1
10KR2J-3-GP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
PR5314 24.2A<OCP<28.6A
6K2R2F-GP
2009/08/28
PC5307 PC5308
C C
1
SCD068U10V2KX-1GP SCD22U16V3KX-2-GP
A00-1218-1 3211_PWRGD 1 24 3211_VCC +CPU_GFXCORE
2
PWRGD VCC 3211_BST PR53151
change PR5314 from 5.9K to 6.2K by power 1 2 2 23 2 1R3J-L1-GP 3211_BST_1 1 2 PL5301
IMON BST 3211_DRVH 3211_DRVH
3 22
3211_FBRTN CLKEN# DRVH 3211_SW
4 21 1 2
3211_FB FBRTN SW IND-D56UH-12-GP
5 20 +5V_ALW
3211_COMP FB PVCC 3211_DRVL
6 19
COMP DRVL
7 18
SC3D3U10V5KX-2GP
SC47P50V2JN-3GP
+5V_ALW GPU PGND
1
1 23211_ILIM 8 17 PR5317
2D2R3J-2-GP
SC220P50V2JN-3GP
ILIM GND
5
6
7
8
33 PU5303
CSCOMP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GND
1
1
D
D
D
D
SIR460DP-T1-GE3-GP
PR5316 9K09R2F-GP PC5310 PTC5302 PTC5301 PC5312 PC5313
DY
CSREF
RAMP
LLINE
SE330U2VDM-L-GP
SE330U2VDM-L-GP
CSFB
PC5309 PC5311 PG5323 PG5324
IREF
RPM
1
2009/08/05
RT
SCD01U25V2KX-3GP
2
13211_SW_GND 2
SC1U10V2KX-1GP
PR5318 PC5314 20KR2F-L-GP 3211_CSCOMP GND_3211_I
9
10
11
12
13
14
15
16
S
S
S
23211_PC53141 ADP3211MNR2G-GP
G
1 2 1 2
2
4
3
2
1
1KR2F-3-GP PR5319 1 2 3211_IREF
SC470P50V2KX-3GP
SC470P50V2KX-3GP PR5320 80K6R2F-GP
3211_CSCOMP
1 2 3211_RPM
3211_CSREF
3211_RAMP
3211_LLINE
3211_CSFB
PR5322 237KR2F-GP 3211_DRVL PC5315
3211_RT
PR5323
1 2
340KR2F-1-GP
DY
2009/08/05
2
GND_3211_I
SC1KP50V2KX-1GP
PC5316
2
+PWR_SRC_CPU_GFXCORE 2 13211_RAMP_1 1 2
PR5325 422KR2F-1-GP
PR5326 PR5327 PR5328
PR5324
1KR2F-3-GP 1 2 3211_CSCOMP_1 1 2 1 2 3211_SW_L
1
60K4R2F-GP
B GND_3211_I PC5317 110KR2F-GP B
SC1000P100V3KX-GP PC5319 178KR3F-GP
SB-1103
2
SC1KP50V2KX-1GP
PC5318
3211_FB_1
PR5330
1
SC470P50V2KX-3GP
NTC-220K-2-GP
20KR2F-L-GP
1
GND_3211_I 1 2
DY
2
2
PR5329
PG5319
2
PR5335
1 23211_VSENSE 1 2 +CPU_GFXCORE SB-1103
1
100R2F-L1-GP-U GAP-CLOSE-PWR-3-GP PR5333

0R0402-PAD-2-GP
2
PR5331 1 2 VCC_AXG_SENSE [13]

0R0402-PAD-2-GP
3211_CSCOMP
PC5320
PR5332 1 2 SC1KP50V2KX-1GP
VSS_AXG_SENSE [13]
0R0402-PAD-2-GP
2
PG5320
PR5336 GND_3211_I
1 23211_VSS_GND1 2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
100R2F-L1-GP-U GAP-CLOSE-PWR-3-GP
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037
A A
1st Samsung
PG5325
1 2
Wistron Corporation
GAP-CLOSE-PWR-3-GP
GND_3211_I Title
2009/08/03 ADP3211 CPU_GFXCORE
Custom Winery13 MB DIS A00
5 4 3 2 1
www.vinafix.vn
+3.3V_RUN +3.3V_RUN_GPU
SSID = VIDEO Close PCH Close GPU
SSID = Inverter
2
1
2
1
RN5404 RN5409
SRN2K2J-1-GP SRN2K2J-1-GP
DW
07/07 Added
1.Added LVDS DDC CLK/DAT Pull Hi
3
4
3
4
[20] L_DDC_DATA [81] LDDC_DATA
[20] L_DDC_CLK [81] LDDC_CLK INVERTER POWER
1ST: 69.50007.A41
UMA/DIS LVDS DDC CLK/DAT select circuit 2ND: 69.50007.A31 +PWR_SRC
+PWR_SRC_LCD
+3.3V_RUN F5401
U5444
POLYSW-1D1A24V-1-GP
2 1
3 4 LDDC_DATA_CON
[81] LDDC_DATA B0 A
1
2 5 EC5403
GND VCC EDID_SELECT# C5401 C5405 SCD1U25V2ZY-1GP
[20] L_DDC_DATA 1 B1 S 6
SC1KP50V2KX-1GP SCD1U25V3KX-GP
2
H=>B1 -iGPU PCH (UMA) 1ST: 73.03157.C0H
NC7SB3157P6X-1GP
L=>B0 -dGPU GPU (DIS) 2ND: 73.03157.E0J
SC-1207-1
pop EC5403 for EMI
LDDC_DATA_CON
[21,55] EDID_SELECT# EDID_SELECT# LDDC_CLK_CON
1
+3.3V_RUN
U5445
DY DY
EV @ LVDS side
2
3 4 LDDC_CLK_CON
[81] LDDC_CLK B0 A
2 GND VCC 5
1 6 EDID_SELECT#
[20] L_DDC_CLK B1 S C5414 C5415
SC22P50V2JN-4GP SC22P50V2JN-4GP
+PWR_SRC_LCD NC7SB3157P6X-1GP 1ST: 73.03157.C0H
2ND: 73.03157.E0J
SSID = VIDEO
LVDS CONNECTOR
2
+LCDVDD
EC5404
SCD1U50V3KX-GP
1
JAE-CON30-5-GP-U
37 32 +LCDVDD
NP2
1
30 +3.3V_RUN C5403 C5406
29 SC10U6D3V5KX-1GP SCD1U10V2KX-4GP
1
C5402
28
LCD POWER
2
1
27 SCD1U10V2KX-4GP
26 DY R5410
2
25 10KR2J-3-GP
36 24
23 +3.3V_EEPROM 1 2 +3.3V_RUN
2
22 LCD_BRIGHTNESS R5404 33R2J-2-GP LCD_BRIGHTNESS SC-1125-2

21 add mux U5446 to select LCDVDD enable signal
20 BLON_OUT_R R5406 1 2 100R2J-2-GP BLON_OUT [37]
19 LCD_TST_L R5413 1 2 100R2J-2-GP LCD_TST [37]
18 LDDC_CLK_CON D5409
17 LDDC_DATA_CON SB-06 BAT54C-7-F-GP +LCDVDD U5403 +3.3V_RUN
16 LCD_DET_G 1 2
35 15 LCD_CBL_DET# ENVDD_M 1 R5409 3 4
LCD_CBL_DET# [25] R5408 0R2J-2-GP OUT IN#4
14 2 GND
1
13 VGA_TXAOUT0- VGA_TXAOUT0- [74] 100R2J-2-GP 3 ENVDD_D 1 2 ENVDD 1 5 C5407
VGA_TXAOUT0+ EN IN#5 SC1U10V3KX-3GP
12 VGA_TXAOUT0+ [74]
1
11 [37] SHBM_LCDTST_EN 2
2
10 VGA_TXAOUT1- VGA_TXAOUT1- [74] G5285T11U-GP
1
9 VGA_TXAOUT1+ VGA_TXAOUT1+ [74] 1ST: 83.00054.X81 R5411 C5408
8 A00-1223-1 49K9R2F-L-GP DY SCD1U16V2KX-3GP
2ND: 83.BAT54.081
34 7 VGA_TXAOUT2- VGA_TXAOUT2- [74] modify LCD power schematic
2
6 VGA_TXAOUT2+ VGA_TXAOUT2+ [74] 1ST: 74.05285.07F
remove D5401 SB-1023
5
4 VGA_TXACLK- VGA_TXACLK- [74]
UMA/DIS LVDS PWM select circuit 2ND:
3 VGA_TXACLK+ VGA_TXACLK+ [74]
2 R5438
0R2J-2-GP
1 [37] LBKLT_CTL_EC 1 DY 2 DGPU_SELECT# :
NP1 +3.3V_RUN
33 31 H=>B1 -iGPU PCH (UMA)
LCD1
U5448 L=>B0 -dGPU GPU (DIS) +3.3V_RUN
U5446
[81] LBKLT_CTL_GPU 3 4 LCD_BRIGHTNESS
B0 A ENVDD_M
2 GND VCC 5 [81] LCDVDD_EN_GPU 3 B0 A 4
[20] LBKLT_CTL_PCH 1 B1 S 6 DGPU_PWM_SELECT# [21] 2 GND VCC 5
[20] LCDVDD_EN_PCH 1 B1 S 6 DGPU_SELECT# [21,37,74]
1ST: 20.F1555.030
NC7SB3157P6X-1GP 1ST: 73.03157.C0H
2ND:
NC7SB3157P6X-1GP 1ST: 73.03157.C0H
2ND: 73.03157.E0J
2ND: 73.03157.E0J
H=>B1 -iGPU PCH (UMA)
L=>B0 -dGPU GPU (DIS)
LCD_BRIGHTNESS
BLON_OUT_R 1st Samsung
LCD_TST
SC33P50V2JN-3GP
SC33P50V2JN-3GP
1
EC5402
EC5401
Wistron Corporation
1
R5407
DY DY 10KR2J-3-GP
2
Title
Size
LCD/Inverter Connector
Document Number Rev
www.vinafix.vn
Custom
For EMI request Winery13 MB DIS A00
5 4 3 2 1
SSID = VIDEO +5V_CRT_RUN

D5504
+5V_RUN
B0530W S-7-F-GP
K A
A00-0104-1
1
A00-1218-1 A00-1218-1 change CRT1 from 20.20431.015 to 20.20401.015
C5510
change R5504, R5505, R5506 from 0R to 33R by EMI change L5501, L5502, L5503 to 0R SCD01U16V2KX-3GP
2
CRT1
R5504 16
[74] M_RED 1 2 M_RED_C 1 2 L5502 CRT_R
D 33R2J-2-GP 0R3J-0-U-GP 6 D
CRT_R 1 11
R5505
[74] M_GREEN 1 2 M_GREEN_C 1 2 L5501 CRT_G 7
33R2J-2-GP 0R3J-0-U-GP CRT_G 2 12 DDC_DATA_CON
8
R5506 +5V_CRT_RUN CRT_B 3 13 JVGA_HS JVGA_HS [74]
[74] M_BLUE 1 2 M_BLUE_C 1 2 L5503 CRT_B 9
33R2J-2-GP 0R3J-0-U-GP 4 14 JVGA_VS JVGA_VS [74]
1
1
10
1
AFTP5502 1 5 15 DDC_CLK_CON
DY DY DY
1
17
2
DY DY
2
2
VIDEO-15-127-GP-U
2
R5502 R5501 R5503 C5508 C5501 C5506
150R2F-1-GP 150R2F-1-GP 150R2F-1-GP SC8P250V2CC-GP SC8P250V2CC-GP SC8P250V2CC-GP
1ST: 20.20401.015 C5502 C5504
Layout Note: 2ND: 20.20479.015
C5509 C5507 C5512
SC8P250V2CC-GP SC8P250V2CC-GP SC8P250V2CC-GP
*Pi-filter & 150 Ohm pull-down AFTP5503 1 +5V_CRT_RUN
DW
AFTP5501 1 DDC_DATA_CON
resistors should be as close AFTP5509 DDC_CLK_CON 07/14 Change
1
as to CRT CONN. AFTP5507 1 CRT_R 1.Change CRT1 CONN PN from
20.20431.015 to 20.20401.015 base on ME emm files.
CRT_R CRT_G CRT_B * RGB signal will hit 75 Ohm AFTP5506 1 CRT_G
3
3
AFTP5508 1 CRT_B
C D5501 D5502 D5503 first, then pi-filter, finally AFTP5504 1 JVGA_HS C
DY BAV99-4-GP DY BAV99-4-GP DY BAV99-4-GP CRT CONN. AFTP5505 1 JVGA_VS
+3.3V_RUN_GPU +3.3V_RUN_GPU +3.3V_RUN_GPU

1
+3.3V_RUN +3.3V_RUN_GPU
DW +5V_CRT_RUN
07/07 Change
Close PCH Close GPU 1.Change CRT DDC CLK/DAT Circuit
2
1
2
1
2
1
RN5510 RN5511 RN5513
SRN2K2J-1-GP SRN2K2J-1-GP SRN2K2J-1-GP
3
4
3
4
3
4
B B
[20] GMCH_DDCDATA [81] CRT_DAT_DDC

DDC_DATA_CON
[20] GMCH_DDCCLK [81] CRT_CLK_DDC
DDC_CLK_CON
UMA/DIS CRT DDC CLK/DAT select circuit
1
C5519 DY C5520
2
+3.3V_RUN
U5542
A00-1218-1
DDC_DATA_CON2
change C5520 from 22p to 10p by EMI
[81] CRT_DAT_DDC 3 B0 A 4
2 GND VCC 5
1 6 EDID_SELECT# 5V @ CRT side
[20] GMCH_DDCDATA B1 S +3.3V_RUN
NC7SB3157P6X-1GP
Q5517
[21,54] EDID_SELECT# EDID_SELECT#
DDC_DATA_CON2 4 3 DDC_DATA_CON
+3.3V_RUN
U5543
5 2
3 4 DDC_CLK_CON2 6 1
[81] CRT_CLK_DDC B0 A
2 GND VCC 5
A 1 6 EDID_SELECT# <Core Design> A
[20] GMCH_DDCCLK B1 S DMN66D0LDW -7-GP
NC7SB3157P6X-1GP DDC_CLK_CON2
DDC_CLK_CON Wistron Corporation
H=>B1 -iGPU PCH (UMA)
Title
L=>B0 -dGPU GPU (DIS)
Size
CRT Connector
Document Number Rev
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
(Blank)
C C
B B
A A
1st Samsung
Wistron Corporation
Title
HDMI Connector
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
SSID = Thermal
C
AFTP5803 1 EMC2102_FAN_TACH_1
Fan Connector C
AFTP5802 1 EMC2102_FAN_DRIVE
FAN1
5
[39] EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 3
2
[39] EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 1

AFTP5801 1 4
*Layout* 25 mil
K
FOX-CON3-6-GP-U
1
C5801 D5801
SC22U6D3V5MX-2GP SDMK0340L-7-F-GP
A
1ST: 20.D0210.103
2ND: 20.F0714.003
B B
A 1st Samsung A
Wistron Corporation
Title

FAN Rev
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
SSID = SATA
SATA HDD Connector SATA HDD Interface comment
******************************
S1:GND
HDD1
S2:RX+
23
S1 S3:RX-
S2 SATA_ITXP0_HRXP0 [24] S4:GND
S3
S5:TX-
[24] SATA_ITXN0_HRXN0
S4 S6:TX+
1 2 SATA_IRXN0_HTXN0 S5
[24] SATA_IRXN0_HTXN0_C
SATA_IRXP0_HTXP0 2
S7:GND
S6 1 SATA_IRXP0_HTXP0_C [24]
C5913 S7 ******************************
SCD01U25V2KX-3GP +3.3V_RUN C5914
+3.3V_RUN
P1------------ 3.3V
SCD01U25V2KX-3GP
P1
P2------------ 3.3V
P2 P3------------ 3.3V
P3 P4:GND
P4
P5 P5:GND / Dell Detected Pin
+5V_RUN +5V_RUN
P6 P6:GND
P7
P8
P7------------ 5V
P9 P8------------ 5V
P10 P9------------ 5V
P11 FFS_INT2 FFS_INT2 [40]
P12 P10--- GND
P13 P11:Dell: FFS_INT for supported HDD
P14
P15 P12:GND
24 P13------------ 12V
SKT-SATA7P+15P-24-GP-U
P14------------ 12V
P15------------ 12V
Close to CONN Close to CONN ******************************
5V power pin 3.3V power pin
1ST: 22.10300.451
2ND:
+5V_RUN +3.3V_RUN
C5903
C5907
C5902
C5901
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
DY DY
2
SSID = SATA
ODD Connector
ODD1
S1 GND
[24] SATA_ITXP1_ORXP1 S2 A+
[24] SATA_ITXN1_ORXN1 S3 A-
S4 GND
[24] SATA_IRXN1_OTXN1_C C5911 2 1 SCD01U25V2KX-3GP SATA_IRXN1_OTXN1 S5
C5912 B-
[24] SATA_IRXP1_OTXP1_C 2 1 SCD01U25V2KX-3GP SATA_IRXP1_OTXP1 S6 B+
S7 GND
P1 DP
SATA_RX- and SATA_RX+ Trace P2 +5V
+5V_RUN P3
Length match within 20 mil P4
+5V
MD
1
C5915 C5908 P5
SC10U6D3V5MX-3GP SCD1U10V2KX-4GP GND
P6 GND
7
2
GND
8 GND
NP1 NP1
NP2 NP2
SKT-SATA7P+6P-38-GP-U
1st Samsung
1ST: 62.10065.531 Wistron Corporation

2ND: 62.10065.D21 Taipei Hsien 221, Taiwan, R.O.C.
Title
HDD/ODD Connector
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
SSID = AUDIO SSID = AUDIO

AFTP6004 1 AUD_SPK_L-_C
AFTP6002 1 AUD_SPK_L+_C MIC IN
Speaker Connector [30] AUD_VREFOUT_B
AUD_VREFOUT_B
1
C6001
D check cable pin define D
1
SC1U6D3V2KX-GP
1ST: 22.10265.301
2
A00-0104-1 SPK1 R6003 R6004 EXT_MIC_JD#
4K7R2J-2-GP 4K7R2J-2-GP [30] EXT_MIC_JD# 2ND:
3
AUD_SPK_L- R6006 1 2 AUD_SPK_L-_C 1
2
[30] AUD_SPK_L- 0R0603-PAD-2-GP LIN1
AUD_SPK_L+ R6007 1 2 AUD_SPK_L+_C 2 6
[30] AUD_SPK_L+ 0R0603-PAD-2-GP MIC_IN_L_2 1 MIC_IN_L_C
4 [30] AUD_EXT_MIC_L 1 2 2 1
C6014 SC1U25V5KX-1GP L6002 BLM18BD601SN1D-GP 2
MLX-CON2-7-GP-U 1 2 MIC_IN_R_2 1 2 MIC_IN_R_C 3
[30] AUD_EXT_MIC_R C6015 SC1U25V5KX-1GP L6003 BLM18BD601SN1D-GP 4
5
MLVG0402220NV05-GP
MLVG0402220NV05-GP
1
1
1ST: 20.F0693.002 600ohm 100MHz
AFTP6005 1 SB-02 AUDIO-JK186-GP
2ND: 20.F1165.002 200mA 0.5ohm DC
EC6003
EC6008
DY DY
1
EC6001 EC6002
2
2
SC-1207-1
pop EC6001 and EC6002 for EMI
C AFTP6009 1 EXT_MIC_JD# C
AFTP6020 1 GND
AFTP6018 1 MIC_IN_L_C
AFTP6019 1 MIC_IN_R_C
Delete Audio De-pop Circuit

2009/07/24
SSID = AUDIO
Head Phone
2009/06/03 1ST: 22.10265.301
AUD_HP1_JD#
2ND:
[30] AUD_HP1_JD#
LOUT1
6
1
AUD_HP1_JACK_L L6004 1 2 AUD_HP_JACK_L_1 2
[30] AUD_HP1_JACK_L
AUD_HP1_JACK_R L6001 1 2 BLM18BD601SN1D-GP AUD_HP_JACK_R_1 3
[30] AUD_HP1_JACK_R
BLM18BD601SN1D-GP 4
B B
600ohm 100MHz 5
200mA 0.5ohm DC AUDIO-JK186-GP
1
C6002 C6003
1
SC1000P50V3JN-GP-U SC1000P50V3JN-GP-U
EC6004 EC6005
2
SCD01U16V2KX-3GP SCD01U16V2KX-3GP
2
SC-1208-1
change EC6004,EC6005 from 0.1U to 0.01U
AFTP6014 1 AUD_HP1_JD#
AFTP6017 1 GND
AFTP6015 1 AUD_HP_JACK_L_1
AFTP6016 1 AUD_HP_JACK_R_1
Added HP circuit 2009/05/26
A 1st Samsung A
Wistron Corporation
Title
SPEAKER/MIC/AUDIO JACK
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM SSID = RBATT
D D
SPI FLASH ROM (2M bits) for KBC

RN6201
SRN100KJ-6-GP
KBC_PW R 4 1 EC_SPI_CS#
3 2 EC_SPI_HOLD# KBC_PW R
RTC Connector
1
DY
2
+3.3V_RTC_LDO A00-0104-1
+3.3V_RTC_LDO C6201 C6203 C6204
C SC4D7U10V3KX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP
change RCT1 from 20.D0210.102 to 20.D0075.102 C
1
+RTC_CELL D6201
R6201 1
100KR2J-1-GP +RTC_VCC
3 RTC1
R6202 3
2
U6203 KBC_PW R 2 RTC_PW R 1 2 1
1
[37] EC_SPI_CS# EC_SPI_CS# 1 8 C6202 BAT54CW -1-GP 1KR2J-1-GP 2
R6205 1 CS# VCC
[37] EC_SPI_DI 2 0R2J-2-GP SPI_DO 2 7 EC_SPI_HOLD# SC1U10V3KX-3GP 4
2
R6204 1 SO HOLD#
[37] EC_SPI_W P#_R 2 0R2J-2-GP EC_SPI_W P# 3 WP# SCK 6 EC_SPI_CLK [37] 1st 83.BAT54.B81 AFTP6202 1
4 5 SPI_DIO FOX-CON2-7-GP
GND SI SPI_DIO [37] 2nd 83.BAT54.A81
Width=20mils
1
1
EC6202 AT25DF021-SSH-T-GP
SC4D7P50V2CN-1GP 1st 20.D0075.102
2
2
2nd 20.F0714.002
EC6201 EC6203
1st 72.25021.001 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
AFTP6201 1 +RTC_VCC
2nd 72.25205.B01
B B
SPI FLASH ROM (32M bits) for PCH

RN6202 +3.3V_RUN
SRN4K7J-8-GP
+3.3V_RUN 1 4 PCH_SPI_W P#
2 3 PCH_SPI_HOLD_0#
1
DY C6206
SCD1U16V2KX-3GP
2
C6205
SC4D7U10V3KX-GP
+3.3V_RUN
1
SC-1208-1 R6207
4K7R2J-2-GP U6202 +3.3V_RUN
change R6206 from 15ohm to 0 ohm
2
[24] PCH_SPI_CS0# 1 CS# VCC 8

[24] PCH_SPI_DI 1 2 PCH_SPI_DI_R 2 7 PCH_SPI_HOLD_0#
PCH_SPI_W P# SO HOLD#
3 WP# SCK 6 PCH_SPI_CLK [24]
R6206 4 5 PCH_SPI_DO [24]
0R2J-2-GP GND SI
A 1st Samsung A
1
AT25DF321-SU-GP
DY DY DY
Wistron Corporation
2

1st 72.25321.001
EC6205 EC6204 EC6206 Title
SC4D7P50V2CN-1GP 2nd 72.25325.A01 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
EEPROM/RTC Connector
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = USB
USB & ESATA Power SW
SB-1021
USB_OC#0_1 [21,22] 1. pop and change TR6304 to 90 ohm for EMI;
DY R6302, R6308
+5V_ALW U6303 +5V_USB1
at least 80 mil 1
GND OC1#
8 at least 80 mil
2 IN OUT1 7
ST100U6D3VBML1GP
3 6
SCD1U10V2KX-4GP
EN1# OUT2
C6305
+5V_USB1
SC1U10V3KX-3GP
100KR2J-1-GP
4 5
[37,76] USB_PWR_EN# EN2# OC2#
TC6303
R6307
C6306
[21] USB_PN0 USB_P0-
1
D C6302 USB1 D
SCD1U50V3KX-GP TPS2062AD-GP 7
2
1ST: 68.00201.141 5
2
2
2ND: 68.02012.201 1
SC-1207-1 1ST: 74.02062.B71 SC-1207-1 USB_P0- 2

change C6302 to D1U for EMI pop R6307 for EMI USB_P0+ 3
2ND: 74.00546.07D
4
DLW21HN900SQ2LGP-U
6
TR6304 8
3
SKT-USB-257-GP-U
[21] USB_PP0 USB_P0+
1ST: 22.10321.001
Remove ESD diode, confirmed with EMI 2ND: 22.10321.181
A00-0106-1
AFTP6317 1 USB_P0-
AFTP6316 1 USB_P0+
AFTP6321 1 +5V_USB1
AFTP6320 1 GND
C C
SSID = ESATA A00
ESATA Power R6301

USB_P1-
[21] USB_PN1 1 2
0R0603-PAD-2-GP
Share one power SW with USB port 1
R6306
[21] USB_PP1 1 2 USB_P1+ Remove ESD diode, confirmed with EMI
0R0603-PAD-2-GP
+5V_USB1
A00-0106-1
ESATA1
remove TR6301 for no co-lay after XB
1
VBUS
4
ESATA_ITX_DRX_PU GND
6 5
ESATA_ITX_DRX_NU A+ GND
7 8 AFTP6306
+3.3V_RUN +3.3V_RUN +3.3V_RUN A- GND
GND 11
ESATA_IRX_DTX_PU 10 12 1
ESATA_IRX_DTX_NU B+ GND
ASM 9
B- GND
GND
13
14
1
C6317
C6318
C6319
USB_P1+
SC1U10V3KX-3GP
3 15
SCD1U10V2KX-4GP
SCD01U50V2KX-1GP
D+ GND
1
R6314 R6315 USB_P1- 2

D-
DY 4K7R2F-GPDY 4K7R2F-GP DY DY DY SKT-USB-ESATA-1-GP
2
ASM
2
B B
D0
D1
1ST: 22.10321.F71
DY
1
R6316 R6317
2ND:
R6304
DY 0R2J-2-GPDY 0R2J-2-GP ESATA_ITX_DRX_PU_C 1 2 ESATA_ITX_DRX_PU
A00-0104-1 0R0603-PAD-2-GP AFTP6308 1 +5V_USB1
2
AFTP6309 1 USB_P1-
R6310 AFTP6302 1 USB_P1+
RN6301 2 3 ESATA_ITX_DRX_NU_C 1 2 ESATA_ITX_DRX_NU
0R4P2R-PAD 1 4 0R0603-PAD-2-GP
R6311
RN
ESATA_IRX_DTX_PU_L 1 2 ESATA_IRX_DTX_PU
2 1 R6313 U6301_REPEATER_EN 0R0603-PAD-2-GP
+3.3V_RUN DY 10R2J-2-GP
U6301 R6312
CAPS CLOSE TO ESATA1 ESATA_IRX_DTX_NU_L 1 2 ESATA_IRX_DTX_NU
6 7 0R0603-PAD-2-GP
VCC EN ESATA_ITX_DRX_PU_L 1 ESATA_ITX_DRX_PU_R1 ESATA_ITX_DRX_PU_C
2R6318 2 C6311
10
20
VCC
15
DY 0R2J-2-GP SCD01U50V2KX-1GP
VCC TX_0P ESATA_ITX_DRX_NU_L 1 ESATA_ITX_DRX_NU_R1 ESATA_ITX_DRX_NU_C
2R6319 2 C6312
16 VCC TX_0N 14
DY 0R2J-2-GP SCD01U50V2KX-1GP A00-0106-1
ESATA_IRX_DTX_P4_C_L C6313
[24] ESATA_ITX_DRX_P4 1
C6309
2
DY
SCD01U50V2KX-1GP ESATA_ITX_DRX_P4_R 1
TX_1P
5
4
1
DY 2
SCD01U16V2KX-3GP
ESATA_IRX_DTX_P4_C [24] remove TR6302, TR6303 for no co-lay after XB
ESATA_ITX_DRX_N4_R RX_0P TX_1N ESATA_IRX_DTX_N4_C_L
[24] ESATA_ITX_DRX_N4 DY
1
C6310
2
SCD01U50V2KX-1GP
2 RX_0N 1
DY 2
C6314
ESATA_IRX_DTX_N4_C [24]
ESATA_IRX_DTX_PU_L C6315 2 1ESATA_IRX_DTX_P4_L ESATA_IRX_DTX_P4 11 DY SCD01U16V2KX-3GP
SCD01U50V2KX-1GP
1
R6320 DY
2
0R2J-2-GP ESATA_IRX_DTX_N4 12 RX_1P GND 3
13
ESATA_IRX_DTX_NU_L C6316 2 RX_1N GND
1ESATA_IRX_DTX_N4_L
SCD01U50V2KX-1GP
1
R6321 DY
2
0R2J-2-GP GND 17
18
D0 GND
9 D0 GND 19
D1 8 21
D1 GND
CAPS CLOSE TO ESATA1
SN75LVCP412RTJR-GP
RN
A A
RN6302 4 1
0R4P2R-PAD 3 2
A00-0104-1 1st Samsung
Wistron Corporation
Title
USB/ESATA Port
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = Wireless
D D
Mini Card Connector(802.11a/b/g/n)
+1.5V_RUN +3.3V_RUN
W LAN1
53
NP1
1 2
+5V_ALW +3.3V_RUN 3 4
[73] W LAN_ACT
[73] BT_ACT 5 6
[23] MINI1_CLKREQ# 7 8
1
C6403 9 10
C C6401 SCD1U10V2KX-5GP C
SCD1U16V2KX-3GP DY [23] CLK_PCIE_MINI1#
[23] CLK_PCIE_MINI1
11
13
12
14
2
15 16
R6404 1 2 0R2J-2-GP E51_RXD_R

+3.3V_RUN +1.5V_RUN
[37] E51_RXD
R6403 1 DY 2 0R2J-2-GP E51_TXD_R
17 18
[37] E51_TXD DY 19
21
20
22 PLT_RST#
W IFI_RF_EN [37] R6406
PLT_RST# [9,21,34,36,37,70,76,80] USB_P4-
23 24 1 2
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
[23] PCIE_IRXN2_MTXN2 +3.3V_RUN USB_PN4 [21]

[23] PCIE_IRXP2_MTXP2 25 26
1
C6406
C6405
C6402
C6404
27 28 0R0603-PAD-2-GP
SCD1U10V2KX-5GP PCH_SMBCLK
DY DY DY [23] PCIE_ITXN2_MRXN2
29
31
30
32 PCH_SMBDATA
PCH_SMBCLK [7,18,19,23,40,76]
PCH_SMBDATA [7,18,19,23,40,76]
2
[23] PCIE_ITXP2_MRXP2 33 34
35 36 USB_P4-
37 38 USB_P4+
+3.3V_RUN 39 40
41 42
43 44 LED_W LAN_W IMAX_OUT# [66,76]
W LAN_ACT 45 46 R6405
47 48
1
R6402 49 50 USB_P4+ 1 2 USB_PP4 [21]

EC6401 +5V_MINI_DEBUG
SC220P50V2KX-3GP
+5V_ALW 1
DY 2 51 52
NP2
2
0R3J-0-U-GP 0R0603-PAD-2-GP
54
SKT-MINI52P-41-GP 1ST: 62.10043.841 A00-0107-1

2ND: 20.F1519.052 remove L6401 for no co-lay after XB
B B
AFTP6402 1 E51_RXD
AFTP6403 1 E51_TXD
SB-09
SB-28
+3.3V_RUN
2
R6407
1KR2J-1-GP
SW 1
NP1 TP6404 1
1 1 TPAD14-GP
1ST: 62.40083.001 R6408
2 W IRELESS_ON#/OFF_R 1 2
2ND: 62.40018.441 W IRELESS_ON#/OFF [37]
3 10R2J-2-GP
NP2
1
C6407
SW -SLIDE67-GP SC1U6D3V2KX-GP
ON OFF
2
1 2 3
A 1st Samsung A
Wistron Corporation
TP6405 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
1 W IRELESS_ON#/OFF_R Taipei Hsien 221, Taiwan, R.O.C.
TPAD14-GP
Title
MINICARD(WLAN)/ITP CONN
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title
WWAN Connector
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = LED
D D
PWR BTN LED

PWR_BTN_LED# 2 1PWR_BTN_LED_R# PWR_BTN_LED_R# [78]
[37] PWR_BTN_LED#
R6628 20KR2J-L2-GP
For LED & Capacity board:
LED Type Color Power rail SCRLK LED
BATTERY LED1 Amber(Multi-color) ALW SCR_LOCK_LED# 2 1 SCRL_LED_R#
[37] SCR_LOCK_LED# SCRL_LED_R# [78]
R6620 20KR2J-L2-GP
SCRL LED White ALW
CAP LED White ALW CAPS LED

CAP_LOCK_LED# 2 1 CAP_LED_R#
[37] CAP_LOCK_LED# CAP_LED_R# [78]
NUM LED White ALW R6621 20KR2J-L2-GP
PWR BTN LED White ALW

NUM LED
SATA ACT LED1 White RUN
NUM_LOCK_LED# 2 1 NUM_LED_R#
[37] NUM_LOCK_LED# NUM_LED_R# [78]
R6622 20KR2J-L2-GP
BT ACT LED White RUN
C C
WLAN/WWAN ACT LED White RUN Bluetooth LED

BT_ACTIVE_K# 2 1 LED_BT_ACT_K_R#
[73] BT_ACTIVE_K# LED_BT_ACT_K_R# [78]
R6623 20KR2J-L2-GP
WWAN LED SB-1024
[64,76] LED_WWAN_OUT#
WLAN WIMAX_LED
LED Location from left to right
+5V_ALW
[64,76] LED_WLAN_WIMAX_OUT# 2 1 WLAN_WIMAX_LED_R# [78] For LED&Capacity board: POWER BATTERY
R6634 20KR2J-L2-GP
LED6601
R6611
BATT_LED_ORANGE 1 2BATT_LED_ORANGE_R 2
B
330R2J-3-GP BATTERY B
Orange A00-0104-1
R6612
1
Q6607 R6617 BATT_LED_WHITE 1 2BATT_LED_WHITE_R 3 Pin1(+) and Pin2(-)= orange

R6630 C BAT_O_LED 1 2 BATT_LED_ORANGE 560R2J-3-GP
1 2 BAT_O_LED_R B R1 Pin1(+) and Pin3(-)= white
[37] BATT_ORANGE_LED
E 0R0402-PAD-2-GP LED-OW-3-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
0R0402-PAD-2-GP R2 1ST: 83.00326.G70
DY DY
EC6609
EC6610
2ND: 83.01222.K70
PDTC124EU-1-GP
2
1ST: 84.00124.H1K
2ND: 84.00124.S1K SB-03
LED6602
White
3
R6608
Q6609 R6629 PWR2_LED 1 2PWR2_LED_R 1A K2 BREATH POWER LED
R6632 C BAT_W_LED 1 2 BATT_LED_WHITE
330R2J-3-GP
BAT_W_LED_R R1
[37] BATT_WHITE_LED 1 2 B
E 0R0402-PAD-2-GP
LED-Y-74-GP white
1
0R0402-PAD-2-GP R2 1ST: 83.00110.J70
PDTC124EU-1-GP EC6607 DY 2ND: 83.01221.R70
1ST: 84.00124.H1K SCD1U10V2KX-4GP
2
2ND: 84.00124.S1K
white +5V_ALW
R6631 Q6608 R2
20KR2J-L2-GP A00-0104-1
1 2 POWER_LED_R# B
E
R6619
Remove HDD LED
[37] PWRLED# R1
C POWER_LED_L 1 2 PWR2_LED
DDTA143ECA-7-F-GP 0R0402-PAD-2-GP
1ST: 84.00143.K11
2ND: SB-01
HD LED white
A +5V_RUN A
Q6606 R2
R6625 E R6626
1 2 SATA_ACT_C# B
[24] SATA_LED# R1
C HDD_LED 1 2 SATA1_ACT_LED
SATA1_ACT_LED [78]
20KR2J-L2-GP
DDTA143ECA-7-F-GP 1st Samsung
0R2J-2-GP
1ST: 84.00143.K11 For LED & Capacity board
2ND:
Wistron Corporation
Title
LED
www.vinafix.vn
A2
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad
Internal KeyBoard Connector

TouchPad Connector
D KB1 AFTP6862 D
1
+5V_RUN +5V_RUN
31
1 KB_DET# KB_DET# [25]
2 KROW7 1 AFTP6837
3 KROW6 1 AFTP6836
2
1
1
4 KROW4 1 AFTP6839 C6805
5 KROW2 1 AFTP6838 SCD1U10V2KX-5GP
6 KROW5 1 AFTP6841
2
7 KROW1 1 AFTP6840 KROW[0..7] [37] RN6802 TPAD1
8 KROW3 1 AFTP6842 SRN10KJ-5-GP 5
9 KROW0 1 AFTP6843
3
4
10 KCOL5 1 AFTP6844 KCOL[0..16] [37] 1
11 KCOL4 1 AFTP6845
12 KCOL7 1 AFTP6847 [37] TPCLK 2
13 KCOL6 1 AFTP6846 [37] TPDATA 3
14 KCOL8 1 AFTP6849 4
1
1
15 KCOL3 1 AFTP6848
16 KCOL1 1 AFTP6851 C6804 C6806 AFTP6835 1 6
17 KCOL2 1 AFTP6850 SC33P50V2JN-3GP SC33P50V2JN-3GP
2
2
18 KCOL0 1 AFTP6853
19 KCOL12 1 AFTP6852 ACES-CON4-10-GP-U
20 KCOL16 1 AFTP6855
24 KCOL9 1 AFTP6859 AFTP6815 1 +5V_RUN 1ST: 20.K0320.004
25 KCOL11 1 AFTP6858 AFTP6816 1 TPCLK
KCOL10 AFTP6860 AFTP6817 TPDATA
2ND: 20.K0382.004
C 26 1 1 C
27
28
29
30
32
+5V_RUN EC6805 1 2SCD1U25V2ZY-1GP
ACES-CON30-3-GP
DY
TPCLK EC6806 1 2SCD1U25V2ZY-1GP
DY
TPDATA EC6807 1 2SCD1U25V2ZY-1GP
DY
1ST: 20.K0421.030
2ND: 20.K0259.030
B
KB Backlight CONN B
+5V_RUN
KBBL1
5
R6815 1 AFTP6833 1 +5V_RUN

1KR2J-1-GP AFTP6832 1 CN7_P2
1 2CN7_P2 2 AFTP6834 1 KB_BL_DET#
[37] KB_BL_DET# KB_BL_DET# 3 AFTP6861 1 KB_BL_CTRL#
KB_BL_CTRL# 4
6
1ST: 20.K0320.004
Q6808 2ND: 20.K0382.004
1 D D 6 ACES-CON4-10-GP-U
2 D D 5
3 G S 4 +5V_RUN +5V_RUN
[37] KB_BL_CTRL
2
AO6402A-GP
SC-1208-1
1
R6803 1ST: 84.06402.B3D change Change Q6808 to 84.06402.B3D C6812

100KR2J-1-GP SCD1U10V2KX-5GP
2ND: 84.03456.D3D DY
1
For EMI
A A
1st Samsung
+5V_RUN EC6801 1 2SCD1U25V2ZY-1GP C6895
DY SC4D7U10V5KX-1GP
CN7_P2 EC6802 1
DY 2SCD1U25V2ZY-1GP
Place near CON5 Wistron Corporation
KB_BL_DET# EC6803 1 2SCD1U25V2ZY-1GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
KB_BL_CTRL# EC6804 1 2SCD1U25V2ZY-1GP
DY Title
Keyboard/Touch Pad
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
Hall Sensor Connector

D D
+3.3V_ALW
DY R6903 2009/05/28
1
+3.3V_ALW C6902
SCD1U10V2KX-5GP
2
1
HALL1
R6903
1
DY 100KR2J-1-GP VDD
2
2
VSS
1ST: 74.06781.07B
[37] LID_CLOSE# LID_CLOSE# 1 2 LID_CLOSE#_1 3 2ND: 74.09132.A7B
OUTPUT
1
R6901 10R2J-2-GP
C6901
SCD047U10V2KX-2GP EM-6781-T30-GP
2
C C
B B
A A
1st Samsung
Wistron Corporation
Title
Hall sensor
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = DEBUG PORT
D D
GOLDEN FINGER FOR DEBUG BOARD

+3.3V_RUN DBT1
1
[24,36,37] LPC_LAD0 2
[24,36,37] LPC_LAD1 3
[24,36,37] LPC_LAD2 4
C G7001 [24,36,37] LPC_LAD3 5 C
6
[9,21,34,36,37,64,76,80] PLT_RST# 1 2 PLT_RST#_GAP
[24,36,37] LPC_LFRAME#
7
DY
8
GAP-OPEN [21] PCLK_FWH 9
10
11
12
SB-1021 MLX-CON10-7-GP
DY DBT1 and add G7001
B B
A A
1st Samsung
Wistron Corporation
Title
Debug port
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
(Reserve)
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
Braidwood
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
For EMI
Camera Connector
D USB_PP11 [21] D
CAMERA1
3
9
1
L7301
CAMERA_USB1+ DLW 21HN900SQ2LGP-U
Camera Power 2
3 CAMERA_USB1-
+3.3V_RUN +3.3V_CAMERA 4 1ST: 68.02012.20G
+3.3V_CAMERA R7300
R7301 5 AUD_DMIC_IN0_R 2 1 33R2J-2-GP AUD_DMIC_IN0 [30] 2ND:
1 2 6
7 AUD_DMIC_CLK_G AUD_DMIC_CLK_G [30]
2
0R3J-0-U-GP 8
1
1
10 USB_PN11 [21]
EC7304 C7305
SCD1U16V2KX-3GP DY SC4D7U6D3V3KX-GP ACES-CON8-3-GP-U
1
AFTP7307
2
1
MLVG0402220NV05-GP
EC7302 EC7303
MLVG0402220NV05-GP
1ST: 20.F0779.008
SC-1208-1
2ND: 20.F1261.008 DY DY pop L7301 for EMI
AFTP7302 1 AUD_DMIC_CLK_G A00-0107-1
2
AFTP7303 1 AUD_DMIC_IN0_R
AFTP7304 +3.3V_CAMERA
1
AFTP7305 1 CAMERA_USB1-
AFTP7306 1 CAMERA_USB1+
C C
For ESD
Bluetooth cable conn.

BT1
15
NP1
BLUETOOTH_DET# 1 2 BT_ACT
W LAN_ACT 3 4 +3.3V_RUN
5 6 USB_PP8
[21] USB_PP8 USB_PP8 BLUETOOTH_EN 7 8 USB_PN8
[21] USB_PN8 USB_PN8 BT_LED 9 10 C7302
1
[64] BT_ACT BT_ACT 11 12 SC2D2U10V3KX-1GP
B BLUETOOTH_EN AFTP6039 B
[37] BLUETOOTH_EN 13 14 1
[64] W LAN_ACT W LAN_ACT NP2
2
16
Assign BT_DET# GPIO ACES-CONN14D-GP
2009/06/09 AFTP6031
AFTP6032
1 BLUETOOTH_DET#
W LAN_ACT
1
SC220P50V2KX-3GP
10KR2J-3-GP
100KR2J-1-GP
1
AFTP6033 1 BLUETOOTH_EN
1
AFTP6034 BT_LED
R7307
R7308
EC7306
1
AFTP6035 BT_ACT 1ST: 20.F1500.014
DY DY AFTP6036
1
1 +3.3V_RUN pin define check
2ND: 20.F0987.014
2
AFTP6037 1 USB_PP8
2
AFTP6038 1 USB_PN8
BT LED control signal 2009/05/26

Close to BT1
+5V_RUN
+3.3V_RUN
1
R7309
100KR2J-1-GP
C7304
C7303
SCD1U10V2KX-4GP
SC2D2U6D3V3KX-GP
1
A 1st Samsung A
2
BT_ACTIVE_K# SB-25
2
[66] BT_ACTIVE_K#
Wistron Corporation
3

Q7302 BT_LED Taipei Hsien 221, Taiwan, R.O.C.
Remove R7301 MMBT3904-7-F-GP
1
2009/06/09 Title
2
1ST: 84.03904.H11
2ND: 84.03904.L06
Camera CONN
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
UMA/DIS LVDS signal select circuit
U7411 +1.8V_RUN
D D
[81] VGA_LVDSA_DAT2 38 ATMDS2+ VDD 2

[81] VGA_LVDSA_DAT2#
37 ATMDS2- VDD 8
1
36 16 C7401 C7403 C7404
[81] VGA_LVDSA_DAT1 ATMDS1+ VDD SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
[81] VGA_LVDSA_DAT1# 35 ATMDS1- VDD 18
34 20
2
[81] VGA_LVDSA_DAT0 ATMDS0+ VDD
[81] VGA_LVDSA_DAT0# 33 ATMDS0- VDD 30
[81] VGA_LVDSA_CLK 32 ATMDSCLK+ VDD 40
[81] VGA_LVDSA_CLK#
31 ATMDSCLK- VDD 42
[20] MCH_LVDSA_DAT2 29 BTMDS2+

[20] MCH_LVDSA_DAT2# 28 BTMDS2- TMDS2+ 3 VGA_TXAOUT2+ [54]
[20] MCH_LVDSA_DAT1 27 BTMDS1+ TMDS2- 4 VGA_TXAOUT2- [54]
[20] MCH_LVDSA_DAT1#
26 BTMDS1- TMDS1+ 6 VGA_TXAOUT1+ [54]
[20] MCH_LVDSA_DAT0
25 BTMDS0+ TMDS1- 7 VGA_TXAOUT1- [54]
[20] MCH_LVDSA_DAT0# 24 BTMDS0- TMDS0+ 11 VGA_TXAOUT0+ [54]
[20] MCH_LVDSA_CLK 23 BTMDSCLK+ TMDS0- 12 VGA_TXAOUT0- [54]
[20] MCH_LVDSA_CLK#
22 BTMDSCLK- TMDSCLK+ 14 VGA_TXACLK+ [54]
TMDSCLK- 15 VGA_TXACLK- [54]
SB-1026
DGPU_1D8V_SEL# 9
modify DGPU SEL circuit SEL
1
VSS
H=>BTMDS -iGPU PCH (UMA) VSS 5
10
L=>ATMDS -dGPU GPU (DIS) VSS
13
VSS
VSS 17
VSS 19
VSS 21
VSS 39
41
GND
C VSS C
TS3DV421RUAR-GP
43
71.03412.B0G
+5V_CRT_RUN
1
C7407
2 SCD1U10V2KX-4GP
B UMA/DIS CRT Hsync/Vsync select circuit B
+3.3V_RUN DGPU_SELECT Hsync & Vsync level shift

DGPU_SELECT#
+5V_CRT_RUN UMA/DIS CRT signal select circuit
1
14
EC7401 U7408A C7408

DY SCD1U25V2ZY-1GP SSAHCT125PWR-GP SCD1U10V2KX-4GP +5V_CRT_RUN
2
2 3 VSYNC_5 U7435
[20] GMCH_VSYNC
2 1 16 VCC
+5V_CRT_RUN DGPU_SELECT# 1 S 4
YA M_BLUE [55]
14
2 IA0
7
[81] VGA_BLUE
4
+3.3V_RUN
SB-1026 [20] MCH_BLUE
3 IA1 YB 7 M_GREEN [55]
5 IB0
modify DGPU SEL circuit 5 6 VSYNC_5 [81] VGA_GREEN
6 IB1 9
[81] VGA_VSYNC [20] MCH_GREEN YC M_RED [55]
1
[81] VGA_RED 11 IC0

R7485 10 IC1 12
20KR2F-L-GP U7408B [20] MCH_RED YD
14 ID0
7
DGPU_SELECT# H=> -iGPU PCH (UMA) SSAHCT125PWR-GP 13 ID1 15

RN7445 OE#
8 GND
L=> -dGPU GPU (DIS)
DGPU_SELECT 2
VSYNC_5 1 4 JVGA_VS [55]

HSYNC_5 2 3 PI5C3257QE-GP
JVGA_HS [55]
DGPU_SELECT
SRN33J-5-GP-U 2ND = 73.03257.C0B
H=>IA1 -iGPU PCH (UMA)
DGPU_SELECT# +5V_CRT_RUN
+1.8V_RUN U7408C L=>IA0 -dGPU GPU (DIS)
14
10
SSAHCT125PWR-GP
3
A HSYNC_5 A
[20] GMCH_HSYNC 9 8 1st Samsung
1
Q7410
DMN66D0LDW-7-GP R7487 +5V_CRT_RUN
20KR2F-L-GP
Wistron Corporation
14
13
7
4

2
12 11 HSYNC_5 Taipei Hsien 221, Taiwan, R.O.C.

[81] VGA_HSYNC
Title
PX Swith-1
7
DGPU_1D8V_SEL# U7408D
www.vinafix.vn
[21,37,54] DGPU_SELECT# SSAHCT125PWR-GP Size Document Number Rev
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A 1st Samsung A
Wistron Corporation
Title

(Reserve) Rev
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
+DC_IN : 19.5V/85W Place near BTB1

+3.3V_RUN : 3300mA +DC_IN
DC_IN baord CON +5V_ALW : 1000mA
+1.5V_RUN : 500mA
1
D C7620 D
Please reoute 300 mil at least. +3.3V_ALW : 58mA DYSC4D7U25V5MX-1DLGP
2
+DC_IN
BTB1
52
1
NP2 C7621
SCD1U25V2ZY-1GP
[23] CLK_PCIE_LAN# 49 50 PCIE_ITXP4_MRXP4 [23]
LAN CLK WWAN PCIE
2
[23] CLK_PCIE_LAN 47 48 PCIE_ITXN4_MRXN4 [23]
45 46
[23] PCIE_ITXN3_LRXN3 43 44 PCIE_IRXP4_MTXP4 [23]
LAN PCIE [23] PCIE_ITXP3_LRXP3 41 42 PCIE_IRXN4_MTXN4 [23] WWAN PCIE
39 40
[23] PCIE_IRXN3_LRTXN3 37 38 CLK_PCIE_MINI2# [23]
LAN PCIE [23] PCIE_IRXP3_LRTXP3 35 36 CLK_PCIE_MINI2 [23]
WWAN CLK
33 34 +3.3V_RUN
[21] USB_PP2 31 32 USB_PP5 [21]
USB PORT2 [21] USB_PN2 29 30 USB_PN5 [21]
WWAN USB
1
27 28 C7601
[21] USB_OC#2_3
[37,63] USB_PWR_EN# 25 26
MINI2_CLKREQ_R# [23]
PCH_SMBDATA [7,18,19,23,40,64]
DY SC4D7U25V5KX-GP
[23] CLKREQ#_LAN 23 24 PCH_SMBCLK [7,18,19,23,40,64] WWAN SMBUS
2
[37] PM_LAN_ENABLE 21 22 LED_WWAN_OUT# [64,66]
[23,24] GPO_DSM 19 20 WWAN_RF_EN [21]
C [43] PS_ID_R2 17 18 PLT_RST# [9,21,34,36,37,64,70,80] C
15 16 PCIE_WAKE# [22,34]
13 14 +3.3V_RUN
11 12
+3.3V_RUN 9 10
+1.5V_RUN 7 8
1
+3.3V_ALW 5 6 C7602
3 4 SCD1U10V2KX-5GP
2
+5V_ALW 1 2 +DC_IN
NP1
51
ACES-CONN50A-2-GP SC-1130
+5V_ALW pop C7614 for RF
1
C7614
1ST: 20.F1631.050 SC1P50V2CN-1GP
2ND:
2
Remove AFTP test point
Confirmed with AFTE.
+5V_ALW
1
C7615
B SCD1U10V2KX-5GP B
2
+1.5V_RUN
1
C7618
SCD1U10V2KX-5GP
2
+3.3V_ALW
1
C7619
SCD1U10V2KX-5GP
2
A A
<Core Design>
Wistron Corporation
Title
DC_IN Board BTB Connector
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blank)
B B
A A
1st Samsung
Wistron Corporation
Title
Audio BD/IO BD CONN
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
D
A00-1223-1 D
1. dummy FP1 pin6, pin7 for power pin short to GND when plug in cable issue
2. add damping resister R7804
Finger Printer Connector
+3.3V_RUN
SB-1025
R7804
0R3J-0-U-GP 1. SWAP USB NET
1 2 FP_VDD
1
A00-0104-1 SB-14
C7801
FP1 LED&Capacity board CONN
SCD1U10V2KX-4GP 7
2
R7801
0R0603-PAD-2-GP 5
Biometric_USBPN
[21] USB_PN10 1
1
2
2 Biometric_USBPP
4
3
Close to MEDIA1
[21] USB_PP10
2 MEDIA1
0R0603-PAD-2-GP 21 +5V_RUN +5V_ALW +3.3V_RUN
R7802 BIO_DET# 1 1
[25] BIO_DET# +5V_RUN
C7803
C7804
C7805
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
6 +5V_ALW 2
SB-06 3
4
2
ACES-CON5-10-GP R7803 1
[37] KBC_PWRBTN#
2 100R2J-2-GP KBC_PWRBTN#_L 5
[66] WLAN_WIMAX_LED_R# WLAN_WIMAX_LED_R# 6
[66] SCRL_LED_R# SCRL_LED_R# 7
[66] CAP_LED_R# CAP_LED_R# 8
[66] NUM_LED_R# NUM_LED_R# 9
[66] SATA1_ACT_LED SATA1_ACT_LED 10
C 1ST: 20.K0315.005 [66] LED_BT_ACT_K_R# LED_BT_ACT_K_R# 11 C
2ND: 20.K0392.005 SB-1024 12
A00-0107-1 [66] PWR_BTN_LED_R# PWR_BTN_LED_R# 13 AFTP7806 1 WLAN_WIMAX_LED_R#
AFTP7802 1 +3.3V_RUN CAPA_INT# 14 AFTP7808 1 SCRL_LED_R#
remove EL7801 for no co-lay after XB AFTP7803 Biometric_USBPN [37] CAPA_INT# AFTP7809 CAP_LED_R#
1 15 1
AFTP7804 1 Biometric_USBPP SB-33 16 AFTP7810 1 NUM_LED_R#
AFTP7805 1 BIO_DET# THERM_SDA 17 AFTP7811 1 SATA1_ACT_LED
[37,39] THERM_SDA
THERM_SCL 18 AFTP7812 1 LED_BT_ACT_K_R#
[37,39] THERM_SCL
19 SB-1024
+3.3V_RUN 20 AFTP7814 1 CAPA_INT#
22
AFTP7816 1 THERM_SDA
PTWO-CON20-2-GP-U AFTP7817 1 THERM_SCL
AFTP7818 1 +3.3V_RUN
AFTP7819 1 +5V_RUN
AFTP7820 1 +5V_ALW
AFTP7821 1 PWR_BTN_LED_R#
AFTP7822 1 KBC_PWRBTN#_L
1ST: 20.K0392.020
2ND: 20.K0481.020
B B
A A
1st Samsung
Wistron Corporation
Title
Finger Printer/Felica/Capacity
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
HOLE:
SSID = EMI H16 H1
H2
H6 H7 H8 H10
HT85B85X925R29-S-GP HT85B85X925R29-S-GP HOLE256R115-GP HT925X85BE95R29-L-5-S-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP
EMI Request SC-1204-1

add EMI caps
1
+PWR_SRC +PWR_SRC +VCC_CORE +1.5V_SUS +5V_CRT_RUN +1.5V_RUN_GPU +3.3V_RUN_CARD
D D
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
1
EC7901
EC7902
EC7903
EC7904
EC7905
EC7906
EC7907
EC7908
EC7909
EC7910
EC7911
SC-1204-4 SB-12
DY SC-1207-1 change H2 to ZZ.00PAD.D11
2
2
add H16 for ME SB-13
H3 H14
HOLE256R115-GP HOLE256R115-GP
+5V_USB1 CHAGER_SRC +PBATT SSID = Mechanical
1
SC-1130-1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
1
EC7912
EC7913
EC7914
EC7915
add H15 for ME
2 FOR CPU HOLE
2
H15 H5
HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP
H11 H12 H13
HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP
C C
1
DY DY DY
1
SSID = RF
FORH4 FAN BOSS
STF296R138H83-GP
SB-29 SC-1130-1
RF Request add RC7931 for RF
1
+PWR_SRC +1.05V_VTT_P +1.5V_RUN_GPU SB-23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1
1
RC7901
RC7902
RC7903
RC7904
RC7905
RC7906
RC7907
RC7908
RC7909
RC7910
RC7928
RC7929
RC7931
B
DY DY DY DY DY DY DY DY DY DY DY B
2
A00-0105-1 SC-1130-1
change SPR5 from 34.4F822.002 to 34.42T14.002 by ME add SPR6 for ME
SPR1 SPR2 SPR3 SPR4 SPR5 SPR6

+PWR_SRC_3D3V +15V_ALW +5V_ALW +3.3V_ALW
SC4D7P50V2CN-1GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1
1
SPRING-24-GP-U SPRING-24-GP-U SPRING-24-GP-U SPRING-31-GP SPRING-57-GP SPRING-24-GP-U

RC7911
RC7912
RC7913
RC7914
RC7915
RC7916
RC7917
RC7918
RC7930
DY DY DY DY DY DY
2
+1.5V_SUS +1.05V_VTT +VCC_GFX_COREP +1.05V_VTT +PWR_SRC +PWR_SRC

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
SC56P50V2JN-2GP
1
A A
RC7919
RC7920
RC7921
RC7922
RC7924
RC7925
RC7926
RC7927
1st Samsung
DY DY DY DY DY
2
Wistron Corporation
Title
+3.3V_ALW +3.3V_ALW
Miscellaneous Components
www.vinafix.vn
Custom
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
PCIE_MTX_GRX_P[0..15]
SSID = VIDEO PCIE_MTX_GRX_P[0..15] [8]
PCIE_MTX_GRX_N[0..15]
PCIE_MTX_GRX_N[0..15] [8]
U8001B 2 OF 7
PCIE_MTX_GRX_P0 AE12 AD10 PCIE_MRX_GTX_C_P0 C8033 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P[0..15]

PCIE_MTX_GRX_N0 PEX_RX0 PEX_TX0 PCIE_MRX_GTX_C_N0 C8034 PCIE_MRX_GTX_P[0..15] [8]
AF12 PEX_RX0# PEX_TX0# AD11 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N0
PCIE_MTX_GRX_P1 AG12 AD12 PCIE_MRX_GTX_C_P1 C8035 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P1
PCIE_MTX_GRX_N1 PEX_RX1 PEX_TX1 PCIE_MRX_GTX_C_N1 C8036 PCIE_MRX_GTX_N[0..15]
AG13 PEX_RX1# PEX_TX1# AC12 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N[0..15] [8]
D PCIE_MTX_GRX_P2 AF13 AB11 PCIE_MRX_GTX_C_P2 C8037 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P2 D
PCIE_MTX_GRX_N2 PEX_RX2 PEX_TX2 PCIE_MRX_GTX_C_N2 C8038
AE13 PEX_RX2# PEX_TX2# AB12 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N2
PCIE_MTX_GRX_P3 AE15 AD13 PCIE_MRX_GTX_C_P3 C8039 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P3
AG16 PEX_RX4# PEX_TX4# AC15 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N4
PCIE_MTX_GRX_P5 AF16 AB14 PCIE_MRX_GTX_C_P5 C8044 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P5
PCIE_MTX_GRX_P6 AE18 AC16 PCIE_MRX_GTX_C_P6 C8047 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P6
AG19 PEX_RX7# PEX_TX7# AD18 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N7
PCIE_MTX_GRX_P8 AF19 AC18 PCIE_MRX_GTX_C_P8 C8052 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P8
PCIE_MTX_GRX_P9 AE21 AB19 PCIE_MRX_GTX_C_P9 C8054 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P9
AF21 PEX_RX9# PEX_TX9# AB20 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N9
PCIE_MTX_GRX_P11 AF22 AD21 PCIE_MRX_GTX_C_P11 C8058 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P11
AE22 PEX_RX11# PEX_TX11# AC21 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N11
PCIE_MTX_GRX_P12 AE24 AB21 PCIE_MRX_GTX_C_P12 C8078 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P12
AF24 PEX_RX12# PEX_TX12# AB22 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N12
PCIE_MTX_GRX_P13 AG24 AC22 PCIE_MRX_GTX_C_P13 C8080 2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P13
PCIE_MTX_GRX_P15 PCIE_MRX_GTX_C_P15 C8084 1SCD1U10V2KX-5GP PCIE_MRX_GTX_P15
PCIE_MTX_GRX_N15
AF27
AE27
PEX_RX15 PEX_TX15 AE25
AE26 PCIE_MRX_GTX_C_N15 C8085
2
2 1SCD1U10V2KX-5GP PCIE_MRX_GTX_N15
Revised decoupling C 2009/05/28
+1.05V_GFX_PCIE PEX_RX15# PEX_TX15# +1.05V_GFX_PCIE
Place under GPU Place near GPU
C C
AB13 PEX_IOVDDQ PEX_IOVDD AC9
AB16 AD7
SC1U10V2KX-1GP
SC1U10V3KX-3GP
SC22U6D3V5MX-2GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
PEX_IOVDDQ PEX_IOVDD
1
1
C8069
C8074
C8064
C8067
C8068
C8066
C8065
C8059
C8060
C8063
C8062
C8061
C8073
C8041
AB17 PEX_IOVDDQ PEX_IOVDD AD8
AB7 PEX_IOVDDQ PEX_IOVDD AE7
AB8 AF7
2
2
PEX_IOVDDQ PEX_IOVDD
AB9 PEX_IOVDDQ PEX_IOVDD AG7
AC13 PEX_IOVDDQ
AC7 AB10 CLK_PCIE_VGA
PEX_IOVDDQ PEX_REFCLK CLK_PCIE_VGA [23]
AD6 AC10 CLK_PCIE_VGA#
PEX_IOVDDQ PEX_REFCLK# CLK_PCIE_VGA# [23] +3.3V_RUN_GPU
AE6 PEX_IOVDDQ
AF6 PEX_IOVDDQ Change R8004
1
Place near GPU Place under GPU AG6 PEX_IOVDDQ PEX_TSTCLK_OUT AF10 PEX_TEST_PLL_CLK_OUT 2
DY 1
PEX_TSTCLK_OUT# AE10 PEX_TEST_PLL_CLK_OUT# 200R2F-L-GP R8002 R8004
10KR2J-3-GP
resistor value
Revised decoupling C 2009/05/28 2009/06/05
AE9 PEX_CLKREQ#
2
PEX_CLKREQ# PEX_RST#
PEX_RST# AD9
PEX_SVDD_3V3 AG9 +3.3V_RUN_GPU

PEX_TERMP 2 R8001 2K49R2F-GP
PEX_TERMP AG10 1 DW
C8049
SCD1U10V2KX-4GP
1
AF9 07/10 NO STUFF
PEX_PLLVDD +PEX_PLLVDD 1. R8002 made NO STUFF
K5 +GPU_PLLVDD
2
PLLVDD
GT218-ES-S-A1-GP
2009/05/28
B B
Place under GPU
Remove 0.01u capacity C8039
2009/05/28
Change power rail
2009/05/26
SB-30
+3.3V_RUN +PEX_PLLVDD
PEX_PLLVDD = 120mA +1.05V_GFX_PCIE
Place under GPU Place near GPU +1.05V_GFX_PCIE
U8028
1
L8011 (Pre pin)
+GPU_PLLVDD
[25] DGPU_HOLD_RST# B L8005
VCC 5 1 2
1 R8039 2 PLT_RST#_RC 2 1 2
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
[9,21,34,36,37,64,70,76] PLT_RST# A
1
PEX_RST#
C8087
C8070
C8046
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
Y IND-D1UH-20-GP
1
0R2J-2-GP
C8086
C8071
C8072
C8076
3
SC1U6D3V2KX-GP
GND BLM18SG121TN1D-GP
2
100NH 0603
C8075
2
2
2
DY I SP_PLLVDD=45mA
2
R8017 74LVC1G08GW -1-GP
DCR= 0.13 ohm
2
100KR2J-1-GP R8016
100KR2J-1-GP
1
NV suggestion. Place near GPU

DW Revised decoupling C 2009/05/28 Revised decoupling C 2009/05/28
07/10 Change
1. Change U8028 from Operating voltage Range 5 to 3 V .
A Add 1st Samsung A
2.Added Pull-down resistors on GPU Reset [PEX_REST#] Pin
Wistron Corporation
Title
VGA-PCIE/LVDS(1/4)
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
DW
07/05 +3.3V_RUN_GPU
1. LCD brightness control are separated by GPU,PCH,EC
2. LCD Power Enable control are separated by GPU,PCH,EC
SSID = VIDEO 3. LCD Backlight On/Off Status are separated by GPU,PCH,EC
2
1
07/10 Not Reserve
1. Shorted LBKLT_CTL_GPU,LCDVDD_EN_GPU,PANEL_BKEN_GPU Not Reserve R8134,R8135,R8136.
RN8112
U8001D 4 OF 7 SRN2K2J-1-GP
N1 R1 CRT_CLK_DDC
GPIO0 I2CA_SCL CRT_CLK_DDC [55]
G1 T3 CRT_DAT_DDC
CRT_DAT_DDC [55]
3
4
GPIO1 I2CA_SDA
C1
[54] LBKLT_CTL_GPU GPIO2 I2CB_SCL I2CB_SCL
M2 R2
[54] LCDVDD_EN_GPU GPIO3 I2CB_SCL I2CB_SDA I2CB_SDA
[37] PANEL_BKEN_GPU M3 R3
PWRCNTL_0 GPIO4 I2CB_SDA
[86] PWRCNTL_0 K3
PWRCNTL_1 GPIO5 LDDC_CLK
[86] PWRCNTL_1 K2 A2 LDDC_CLK [54]
GPIO6 I2CC_SCL LDDC_DATA
J2 B1 LDDC_DATA [54]
THERMTRIP_VGA# GPIO7 I2CC_SDA
[37] THERMTRIP_VGA# C2
GPIO8
D
M1
D2
GPIO9
GPIO10
I2CH_SCL
I2CH_SDA
A3
A4 Default X'tal D
D1
GPIO11
J3 T1
GPIO12 I2CS_SCL
J1 T2
GPIO13 I2CS_SDA
K1
F3
GPIO14 CLK GEN 27M select: X8101
GPIO15 TP_JTAG_TDI_GPU TP8102
G3
G2
GPIO16 JTAG_TDI
AG4
AE4 TP_JTAG_TDO_GPU
1
1 TP8104 XTAL_IN R8123 1 2 0R2J-2-GP
Main 82.30034.651 2 3
DEEPIDLE_WAKE_INT_R# F1
GPIO17 JTAG_TDO DY CLK_VGA_27M [7]
Second ?
[25] DEEPIDLE_WAKE_INT_R# GPIO18 TP_JTAG_TMS_GPU XTAL_SSIN
F2 AF4 1 TP8101 R8131 1 2 0R2J-2-GP
GPIO19 JTAG_TMS
AG3 JTAG_RST#_GPU 2 1 DY
JTAG_TRST#
1
SC-1204-1 AF3 TP_JTAG_TCK_GPU 1KR2J-1-GP
1 TP8103 R8120 GPU_XTAL_IN 1 4
JTAG_TCK R8132 R8125
add EC8101,EC8102,EC8103 for EMI DY Remove R8112,
1
10KR2J-3-GP 10KR2J-3-GP
ROM_SO
C10 ROM_SO_GPU
ROM_SI_GPU
ROM_SO_GPU [83] R8114 2009/06/09 R8115 XTAL-27MHZ-84-GP
[74] VGA_BLUE AD3 A10 ROM_SI_GPU [83] 1MR2J-1-GP
2
DACA_BLUE ROM_SI
[74] VGA_GREEN AE3
DACA_GREEN ROM_SCLK_GPU
[74] VGA_RED AE2 C9 ROM_SCLK_GPU [83]
2
DACA_RED ROM_SCLK GPU_XTALOUT
B10
1
ROM_CS#
VGA 27M R8123 R8131 R8125 R8132
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
1
1
R8116
R8118
R8119
0R0402-PAD-2-GP
EC8101
EC8102
EC8103
[74] VGA_VSYNC AD1
DACA_VSYNC XTAL_IN GPU_XTAL_IN
[74] VGA_HSYNC AD2
DACA_HSYNC XTAL_IN
D10 R8114 1 2 SS DY POP DY POP C8135 C8138
E10 GPU_XTALOUT_1 1 2 GPU_XTALOUT SC15P50V2JN-2-GP SC15P50V2JN-2-GP
2
DACA_RSET XTAL_OUT
AE1 R8113 0R0402-PAD-2-GP NON-SS POP DY POP DY
2
+DACA_VDD DACA_RSET XTALBUFF
AG2 E9 R8124 2 1 10KR2J-3-GP A00-0104-1 SB-19
2
DACA_VREF DACA_VDD XTAL_OUTBUFF
AF1 D11 XTAL_SSIN
DACA_VREF XTAL_SSIN
R8106
Added CLK GEN 27M select circuit 2009/06/15
124R2F-U-GP
R8133
R4 2009/06/03 1st: HARMONY 82.30034.651
SCD1U10V2KX-5GP
DACB_BLUE STRAP_CAL_PU_GND0 Added R8132 (DY) 2009/06/17
C8103
T4 F11 1 2
1
DACB_GREEN MULTI_STRAP_REF0_GND
T5 F10 STRAP_CAL_PU_GND1 1 2 40K2R2F-GP 2nd: ITTI 82.30034.801
1
DACB_RED MULTI_STRAP_REF1_GND R8126 40K2R2F-GP
+DACA_VDD = 120mA U4 VGA_THERMDC [39] 3rd: TXC 82.30034.681
1
DACB_VSYNC
U6 D8
DACB_HSYNC THERMDN
D9
DY C8102
THERMDP SC2200P50V2KX-2GP
Place near GPU Place under GPU V6 VGA_THERMDA [39]
2
DACB_VDD DACB_RSET
W5
+DACA_VDD DACB_VDD HDCP_TESTMODE R8107 2
R6 AD25 1 10KR2J-3-GP
+3.3V_RUN_GPU DACB_VREF TESTMODE CEC R8127 2 10KR2J-3-GP
L8106 N2 1 +3.3V_RUN_GPU
CEC
1
16mil +DACA_VDD R8111 STRAP0 SP_PLLVDD
L6 +SP_PLLVDD
1 2
BLM18SG331TN1D-GP 10KR2F-2-GP
[83] STRAP0
STRAP1
C7
STRAP0 SPDIF
F9 2009/06/03 SB-30
[83] STRAP1
STRAP2
B9
STRAP1 2009/05/28 Place near GPU
C8153
C8154
C8144
C8143
C8118
C8108
C8107
C A9 N5 C
SC470P50V2KX-3GP
SC4700P50V2KX-1GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
[83] STRAP2
1
STRAP2 BUFRST# +1.05V_GFX_PCIE
2
+SP_PLLVDD
Spec 300 ohm, L8110
2
ESR<0.25 ohm 1 2
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
1
BLM18SG121TN1D-GP
C8127
C8120
I SP_PLLVDD=45mA
2
U8001C 3 OF 7
[74] VGA_LVDSA_CLK AC4 F5
IFPA_TXC IFPD_L0
[74] VGA_LVDSA_CLK# AD4 F4
IFPA_TXC# IFPD_L0#
V5
IFPD_L1
E4
D5
+IFPAB_IOVDD
[74] VGA_LVDSA_DAT0 IFPA_TXD0 IFPD_L1#
[74] VGA_LVDSA_DAT0# V4 C3
IFPA_TXD0# IFPD_L2
[74] VGA_LVDSA_DAT1 AA5 C4
IFPA_TXD1 IFPD_L2#
[74] VGA_LVDSA_DAT1# AA4 B3
IFPA_TXD1# IFPD_L3 +1.8V_RUN_GPU
[74] VGA_LVDSA_DAT2 W4 B4
IFPA_TXD2 IFPD_L3#
[74] VGA_LVDSA_DAT2# Y4
IFPA_TXD2# L8107 IFPAB_IOVDD = 300mA
AB4 R8128
IFPA_TXD3 IFPD_PLLVDD +IFPAB_IOVDD
AB5 N6 2 1 1 2
IFPA_TXD3# IFPD_PLLVDD
+IFPAB_IOVDD 10KR2J-3-GP BLM18PG181SN1D-GP
C8126
C8149
C8150
V3 M6
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
1
1
IFPA_IOVDD IFPD_RSET
D3
+IFPAB_PLLVDD IFPD_AUX_I2CX_SCL
AD5 D4
2
IFPAB_PLLVDD IFPD_AUX_I2CX_SDA# R8129
1
R8121 DY 2 IFPAB_RSET AB6 IFPAB_RSET IFPDE_IOVDD
H6 IFPDE_IOVDD 2 1
Place near GPU
Place under GPU
1KR2F-3-GP 10KR2J-3-GP near IFPA_IOVDD
2009/05/28AB3
IFPB_TXC
AB2 D6
IFPB_TXC# IFPE_L0 +IFPAB_IOVDD
B W1
IFPE_L0#
C6
A6
Revised decoupling C 2009/05/28 B
IFPB_TXD4 IFPE_L1
C8151
V1 A7
SCD1U10V2KX-4GP
1
IFPB_TXD4# IFPE_L1#
W3 B6
IFPB_TXD5 IFPE_L2
DW30 LVDS only 1 chanel W2
AA2
IFPB_TXD5# IFPE_L2#
B7
E6
2
IFPB_TXD6 IFPE_L3
Vendor confirm tie to +1.8V powe rail AA3
IFPB_TXD6# IFPE_L3#
E7 Place under GPU
AB1 R8130
AA1
IFPB_TXD7
D7 IFPE_PLLVDD 2 1 near IFPB_IOVDD
IFPB_TXD7# IFPE_PLLVDD
F8
+IFPAB_IOVDD IFPE_RSET 10KR2J-3-GP
V2
IFPB_IOVDD
F7
IFPE_AUX_I2CY_SCL
G6
IFPE_AUX_I2CY_SDA#
P4
IFPC_L0
N4
IFPC_L0#
DW30 not support HDMI M5
M4
IFPC_L1 Unused IFP
IFPC_L1#
NV DG: pull-down 10K L4
IFPC_L2 Interfaces setting
K4
IFPC_L2#
H4
IFPC_L3
2009/06/03
J4
IFPC_L3#
IFPC_IOVDD
1 2
R8135 1 10KR2J-3-GP
2 IFPC_PLLVDD
J6
P6
IFPC_IOVDD +IFPAB_PLLVDD
R8134 10KR2J-3-GP IFPC_PLLVDD
R5
IFPC_RSET
G4 +1.05V_GFX_PCIE
IFPC_AUX_I2CW_SCL
G5
IFPC_AUX_I2CW_SDA# L8108 IFPAB_PLLVDD = 220mA
Change power rail 1 2 +IFPAB_PLLVDD
GT218-ES-S-A1-GP 2009/05/28 BLM18PG181SN1D-GP
C8128
C8152
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
1
2
2
Place near GPU
A A
1st Samsung
Wistron Corporation
Title
VGA-LVDS/CRT/DP PORT
www.vinafix.vn
A2 A00
Winery13 MB DIS
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO

D U8001G 7 OF 7 D
Place under GPU 6 OF 7
U8001F B2 AF8
GND GND
B5 GND GND AF5
+VCC_GFX_CORE J9 B8 AF26
VDD GND GND
J10 VDD B11 GND GND AF23
L9 B20 AF17
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VDD GND GND
M9 VDD B23 GND GND AF14
C8241
C8242
C8243
C8244
C8246
C8247
M11 VDD B26 GND GND AF11
1
M17 VDD E2 GND GND AC26
N9 VDD E5 GND GND AC23
N11 E8 AC20
2
2
VDD GND GND
N17 VDD F6 GND GND AC5
N19 VDD NC#J5 J5 H2 GND GND AC2
P11 D15 H5 Y26
SCD1U10V2KX-4GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
SCD047U10V2KX-2GP
VDD NC#D15 GND GND
P12 VDD NC#C15 C15 J11 GND GND Y23
C8234
P13 VDD J14 GND GND Y5
1
1
C8248
C8249
C8250
P14 VDD J17 GND GND Y2
P15 VDD K19 GND GND W17
P16 K9 W14
2
2
VDD GND GND
P17 VDD RFU_1 T6 L2 GND GND W11
R9 VDD RFU_2 W6 L11 GND GND V9
C R11 Y6 L12 V19 C
VDD RFU_3 GND GND
R12 VDD RFU_4 AA6 L13 GND GND U26
R13 VDD RFU_5 N3 Place under GPU Place near GPU L14 GND GND U23
R14 VDD L15 GND GND U17
Place near GPU R15 +3.3V_RUN_GPU L16 U16
VDD GND GND
R16 VDD L17 GND GND U15
R17 L5 U14
SC4D7U6D3V3KX-GP
VDD GND GND

C8240
C8229
C8230
C8232
C8211
C8231
T9 M12 U13
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
VDD GND GND
1
T11 VDD M13 GND GND U12
1
T17 VDD VDD33 A12 M14 GND GND U11

U9 B12 M15 U5
2
VDD VDD33 GND GND
U19 C12 M16 U2
2
VDD VDD33 GND GND

W9 VDD VDD33 D12 P2 GND
W10 VDD VDD33 E12 P5 GND
W12 VDD VDD33 F12 P9 GND
W13 VDD P19 GND
W18 VDD P23 GND
W19 VDD P26 GND
Revised decoupling C 2009/05/28 T12
T13
GND
GND
T14 GND GND_SENSE E14
TPAD14-GP TP8203 1 TP_VDD_SENSE_E15 E15 T15 W16
TPAD14-GP TP8205 TP_VDD_SENSE_W 15 W15 VDD_SENSE GND GND_SENSE
1 VDD_SENSE VID_PLLVDD K6 +GPU_PLLVDD T16 GND
2009/05/28
GT218-ES-S-A1-GP
GT218-ES-S-A1-GP
B
"Remote Voltage Sensing" not used,reserve Test-Point. B
Change FBVDDQ power rail
2009/05/28 FBVDD/Q = 2.24A
+1.5V_RUN_GPU
5 OF 7 U8001E Place under GPU +1.5V_RUN_GPU
L19 A13
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
FBVDDQ FBVDDQ
C8209
C8222
C8235
C8251
C8252
L23 B13 C8253

FBVDDQ FBVDDQ
1
L26 FBVDDQ FBVDDQ C13

M19 FBVDDQ FBVDDQ D13
N22 D14
2
FBVDDQ FBVDDQ
U22 FBVDDQ FBVDDQ E13
Y22 FBVDDQ FBVDDQ F13
FBVDDQ F14
FBVDDQ F15
FBVDDQ F16
FBVDDQ F17
FBVDDQ F19
FBVDDQ F22
H23 Place near GPU +1.5V_RUN_GPU
FBVDDQ
FBVDDQ H26
FBVDDQ J15
FBVDDQ J16
1
FBVDDQ J18
J19 C8219
FBVDDQ SC1U10V3KX-3GP
2
A 1st Samsung A
GT218-ES-S-A1-GP
Wistron Corporation
Revised decoupling C 2009/05/28 Title
VGA-POWER/GND(3/4)
www.vinafix.vn
A3 Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO Strap pin resistor need use 1% resistor (NV Design Guide) +3.3V_RUN_GPU
Strap pin define
U8001A 1 OF 7
[84,85] MDA[0..63]
15KR2F-GP
45K3R2F-L-GP
34K8R2F-1-GP
4K99R2F-L-GP
4K99R2F-L-GP
4K99R2F-L-GP
1
1
MDA0 D22 F26 FBA_CMD_0
FBA_D0 FBA_CMD0 FBA_CMD_0 [84]
MDA1 RAS#
R8306
R8302
R8305
R8309
R8311
R8312
D E24 FBA_D1 FBA_CMD1 J24 RAS# [84,85] D
MDA2 FBA_CMD_2
MDA3
E22
D24
FBA_D2 FBA_CMD2 F25
M23 BA1
FBA_CMD_2 [84] DY DY DY
FBA_D3 FBA_CMD3 BA1 [84,85]
MDA4 D26 N27 FBA_CMD_4
FBA_CMD_4 [85]
2
MDA5 FBA_D4 FBA_CMD4 FBA_CMD_5
D27 FBA_D5 FBA_CMD5 M27 FBA_CMD_5 [85]
MDA6 C27 K26 FBA_CMD_6 STRAP0
FBA_D6 FBA_CMD6 FBA_CMD_6 [85] [81] STRAP0
MDA7 B27 J25 FBA_CMD_7
MDA8 A21 J27 FBA_CMD_8 STRAP1
FBA_D8 FBA_CMD8 FBA_CMD_8 [85] [81] STRAP1
MDA9 B21 G23 MAA11
FBA_D9 FBA_CMD9 MAA11 [84,85]
MDA10 C21 G26 CAS# STRAP2
FBA_D10 FBA_CMD10 CAS# [84,85] [81] STRAP2
MDA11 C19 J23 W E#
FBA_D11 FBA_CMD11 W E# [84,85]
MDA12 C18 M25 BA0 ROM_SCLK_GPU
FBA_D12 FBA_CMD12 BA0 [84,85] [81] ROM_SCLK_GPU
MDA13 D18 K27 FBA_CMD_13
MDA14 B18 G25 MAA12 ROM_SI_GPU
FBA_D14 FBA_CMD14 MAA12 [84,85] [81] ROM_SI_GPU
MDA15 C16 L24 MEM_RST
FBA_D15 FBA_CMD15 MEM_RST [84,85]
MDA16 E21 K23 MAA7 ROM_SO_GPU
FBA_D16 FBA_CMD16 MAA7 [84,85] [81] ROM_SO_GPU
MDA17 F21 K24 MAA10
MDA18 D20 G22 FBA_CMD_18
MDA19 F20 FBA_D19 FBA_CMD19 K25 MAA0
MAA0 [84,85] Logical Strap Bit Mapping
MDA20 D17 H22 MAA9
30KR2F-GP
10KR2F-2-GP
Resistor Pull-Up Pull-Down
4K99R2F-L-GP
1
MDA21 F18 M26 MAA6
15KR2F-GP
20KR2F-L-GP
10KR2F-2-GP
MDA22 FBA_D21 FBA_CMD21 FBA_CMD_22
MAA6 [84,85] 5Kohms 1000 0000
R8307
R8301
R8316
R8304
R8308
R8313
D16 FBA_D22 FBA_CMD22 H24 FBA_CMD_22 [84]
MDA23 MAA8 10Kohms 1001 0001
MDA24
E16
A22
FBA_D23 FBA_CMD23 F27
J26 FBA_CMD_24
MAA8 [84,85]
15Kohms 1010 0010 DY DY DY
MDA25 C24 G24 MAA1 20Kohms 1011 0011
MAA1 [84,85]
2
MDA26 FBA_D25 FBA_CMD25 MAA13
D21 FBA_D26 FBA_CMD26 G27 MAA13 [84,85] 25Kohms 1100 0100
MDA27 B22 M24 BA2
FBA_D27 FBA_CMD27 BA2 [84,85] 30Kohms 1101 0101
MDA28 C22 K22 FBA_CMD_28
MDA29 A25 J22 FBA_CMD_29
FBA_CMD_29 [84]
35Kohms 1110 0110
C MDA30 FBA_D29 FBA_CMD29 FBA_CMD_30 C
B25 FBA_D30 FBA_CMD30 L22 FBA_CMD_30 [84] 45Kohms 1111 0111
MDA31 A26
MDA32 FBA_D31
MDA33
U24
V24
FBA_D32
C26 DQMA#0
2009/06/05
FBA_D33 FBA_DQM0 DQMA#0 [84]
MDA34 V23 B19 DQMA#1
MDA35 R24 FBA_D35 FBA_DQM2 D19 DQMA#2
DQMA#2 [84] Strap0 Strap1 Strap2
MDA36 T23 D23 DQMA#3 USER_BIT0 1 3GIO_PADCFG_LUT_ADR0 0 PCI_DEVID_0 1
MDA37 R23 T24 DQMA#4
MDA38 FBA_D37 FBA_DQM4 DQMA#5
DQMA#4 [85] USER_BIT1 1 3GIO_PADCFG_LUT_ADR1 1 PCI_DEVID_1 0
P24 FBA_D38 FBA_DQM5 AA23 DQMA#5 [85]
MDA39 P22 AB27 DQMA#6 USER_BIT2 1 3GIO_PADCFG_LUT_ADR2 1 PCI_DEVID_2 1
MDA40 AC24 T26 DQMA#7
DQMA#7 [85]
USER_BIT3 1 3GIO_PADCFG_LUT_ADR3 1 PCI_DEVID_3 0
MDA41 FBA_D40 FBA_DQM7
AB23 FBA_D41
MDA42 AB24 FBA_D42
EDID is used Reserved N11M-GE1 GPU Device ID=0x0A75
MDA43 W24 D25 QSA#0
FBA_D43 FBA_DQS_RN0 QSA#0 [84]
MDA44 AA22 A18 QSA#1
MDA45 W23 E18 QSA#2
MDA46 W22 FBA_D46 FBA_DQS_RN3 B24 QSA#3
QSA#3 [84] ROM_SI_GPU ROM_SO_GPU ROM_SCLK_GPU
MDA47 V22 R22 QSA#4 RAM_CFG0 VGA_DEVICE 1 PEX_PLL_EN_TERM 0
MDA48 AA25 Y24 QSA#5
MDA49 FBA_D48 FBA_DQS_RN5 QSA#6
QSA#5 [85] RAM_CFG1 SMB_ALT_ADDR 0 SLOT_CLK_CONFIG 1
W27 FBA_D49 FBA_DQS_RN6 AA27 QSA#6 [85]
MDA50 W26 R27 QSA#7 RAM_CFG2 FB_0_BAR_SIZE 0 SUB_VENDOR 0
MDA51 W25 RAM_CFG3 XCLK_417 0 PCI_DEVID_4 1
MDA52 FBA_D51
AB25 FBA_D52
MDA53 AB26 C25 QSA0
FBA_D53 FBA_DQS_WP0 QSA0 [84]
MDA54 AD26 FBA_D54 FBA_DQS_WP1 A19 QSA1
QSA1 [84] Default setting: SAMSUNG sDDR3 64Mx16BIT-->20K pull down (0x0011)
MDA55 AD27 E19 QSA2 If use Hynix sDDR3 64Mx16BIT(0x0010), R8308 change to 15K.
MDA56 V25 A24 QSA3
MDA57 R25 FBA_D57 FBA_DQS_WP4 T22 QSA4
QSA4 [85] RAM_CFG[3:0] Config FB_BUS Width Definitions
B
MDA58 V26 FBA_D58 FBA_DQS_WP5 AA24 QSA5
QSA5 [85] 0000 B
MDA59
MDA60
V27
R26
FBA_D59 FBA_DQS_WP6 AA26
T27
QSA6
QSA7
QSA6 [85] 0001
FBA_D60 FBA_DQS_WP7 QSA7 [85] 0010 64MX16 DDR3 64Bit Hynix
MDA61 T25 FBA_D61
MDA62 N25 FBA_D62
0011 64MX16 DDR3 64Bit Samsung
MDA63 N26 FBA_D63 FBA_CLK0 F24 CLKA0
CLKA0 [84] 0100 Default
FBA_CLK0# F23 CLKA0#
CLKA0# [84] 0101
40D2R2F-GP 2 1R8303 FB_CAL_PU_GND A15 N24 CLKA1 0110
+1.5V_RUN_GPU 40D2R2F-GP 2 1R8314 FB_CAL_PD_VDDQ B15
FB_CAL_PU_GND
FB_CAL_PD_VDDQ
FBA_CLK1
FBA_CLK1# N23 CLKA1# CLKA1 [85]
CLKA1# [85]
0111
60D4R2F-GP 1 2R8315 FB_CAL_TERM_GND B16
FB_CAL_TERM_GND
AC19 FB_PLLAVDD FBA_DEBUG M22
L8301 R19 FB_PLLAVDD
SUB_VENDOR XCLK_417 PEX_PLL_EN_TERM
1 2
16mil +FB_PLLVDD T19
FB_VREF A16
nVIDIA recommend
0 No VBIOS ROM 0 277MHz(POR) 0 Disable (POR)
+1.05V_GFX_PCIE FB_DLLAVDD 1 BIOS ROM present 1 Reserved 1 Enable
BLM18SG331TN1D-GP
GT218-ES-S-A1-GP
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
1
3GIO_PADCFG USER[3:0]
C8302
C8301
0000 Desktop 1111 Use EDID to detect panel settings

Place near GPU 1110 Notebook (POR)
2
SLOT_CLOCK_CFG
0 GPU and MCH do not share a common reference clock
1 GPU and MCH share a common reference clock (POR)
FB_PLLAVDD+FB_DLLAVDD=100mA
A 1st Samsung A
DW
07/10 Updated
1.+FB_PLLVDD power rail corrected to +1.05V_GFX_PCIE
Wistron Corporation
Title
VGA-MEMORY/STRAPS(4/4)
www.vinafix.vn
A3 Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
+1.5V_RUN_GPU +1.5V_RUN_GPU
MDA[0..63] [83,85] MDA[0..63] [83,85]
U8401 U8402
K8 E3 MDA17 K8 E3 MDA7
VDD DQL0 MDA18 VDD DQL0 MDA6
K2 F7 K2 F7
N1 F2 N1 F2
R9 F8 R9 F8
B2 H3 B2 H3
D9 H8 D9 H8
G7 G2 G7 G2
R1 H7 MDA[0..63] [83,85] R1 H7 MDA[0..63] [83,85]
VDD DQL7 VDD DQL7
D N9 N9 D
VDD MDA13 VDD MDA29
D7 D7
DQU0 MDA14 DQU0 MDA24
A8 C3 A8 C3
+1.5V_RUN_GPU VDDQ DQU1 MDA9 +1.5V_RUN_GPU VDDQ DQU1 MDA30
A1
VDDQ DQU2
C8
MDA8
A1
VDDQ DQU2
C8
MDA28
UMA
C1
C9
VDDQ DQU3
C2
A7 MDA12
UMA C1
C9
VDDQ DQU3
C2
A7 MDA25 swap for layout
VDDQ DQU4 VDDQ DQU4
1
1
D2
VDDQ DQU5
A2 MDA11
MDA15
swap for layout D2
VDDQ DQU5
A2 MDA26
MDA31
E9 B8 E9 B8
R8404 VDDQ DQU6 MDA10 R8403 VDDQ DQU6 MDA27
F1 A3 F1 A3
1KR2F-3-GP VDDQ DQU7 1KR2F-3-GP VDDQ DQU7
H9 H9
VDDQ QSA1 VDDQ QSA3
H2 C7 QSA1 [83] H2 C7 QSA3 [83]
2
2
VDDQ DQSU QSA#1 VDDQ DQSU QSA#3
B7 QSA#1 [83] B7 QSA#3 [83]
VREFA1 DQSU# VREFA2 DQSU#
H1 H1
VREFDQ QSA2 VREFDQ QSA0
M8 F3 QSA2 [83] M8 F3 QSA0 [83]
VREFCA DQSL VREFCA DQSL
1 2 ZQ_VRAM11 L8 G3 QSA#2 1 2 ZQ_VRAM12 L8 G3 QSA#0
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
QSA#2 [83] QSA#0 [83]
1
1
ZQ DQSL# ZQ DQSL#
C8420
C8421
R8406 243R2F-2-GP R8407 243R2F-2-GP
1
1
K1 FBA_CMD_30 K1 FBA_CMD_30
ODT FBA_CMD_30 [83] ODT FBA_CMD_30 [83]
R8401 MAA0 N3 R8402 MAA0 N3
[83,85] MAA0 A0 [83,85] MAA0 A0
1KR2F-3-GP MAA1 P7 1KR2F-3-GP MAA1 P7
[83,85] MAA1 [83,85] MAA1
2
2
FBA_CMD_22 A1 FBA_CMD_29 FBA_CMD_22 A1 FBA_CMD_29
[83] FBA_CMD_22 P3 L2 FBA_CMD_29 [83] [83] FBA_CMD_22 P3 L2 FBA_CMD_29 [83]
2
2
1
FBA_CMD_24 A2 CS# MEM_RST FBA_CMD_24 A2 CS# MEM_RST
[83] FBA_CMD_24 N2 T2 MEM_RST [83,85] [83] FBA_CMD_24 N2 T2 MEM_RST [83,85]
A3 RESET# A3 RESET#
1
FBA_CMD_0 P8 R8409 FBA_CMD_0 P8
[83] FBA_CMD_0 [83] FBA_CMD_0
1
FBA_CMD_2 A4 10KR2J-3-GP EC8401 FBA_CMD_2 A4
[83] FBA_CMD_2 P2 [83] FBA_CMD_2 P2
MAA6 A5 R8410 SC6D8P50V2CN-GP MAA6 A5
[83,85] MAA6 R8 T7 [83,85] MAA6 R8 T7
2
MAA7 A6 NC#T7 MAA7 A6 NC#T7
[83,85] MAA7 R2 L9 10KR2J-3-GP [83,85] MAA7 R2 L9
2
MAA8 A7 NC#L9 MAA8 A7 NC#L9
[83,85] MAA8 T8 L1 [83,85] MAA8 T8 L1
[83,85] MAA9 R3 J9 [83,85] MAA9 R3 J9
2
MAA10 A9 NC#J9 MAA10 A9 NC#J9
[83,85] MAA10 L7 J1 [83,85] MAA10 L7 J1
MAA11 A10/AP NC#J1 MAA11 A10/AP NC#J1
[83,85] MAA11 R7 [83,85] MAA11 R7
MAA12 A11 MAA12 A11
[83,85] MAA12 N7 [83,85] MAA12 N7
MAA13 A12/BC# MAA13 A12/BC#
[83,85] MAA13 T3 J8 [83,85] MAA13 T3 J8
A13 VSS A13 VSS
M7
NC#M7 VSS
M1
M9
Added MEN_RST M7
NC#M7 VSS
M1
M9
VSS VSS
BA0 VSS
J2 10K pull down R CLKA0 BA0 VSS
J2
[83,85] BA0 M2 P9 [83,85] BA0 M2 P9
BA0 VSS BA0 VSS
[83,85] BA1
BA1 N8
BA1 VSS
G8 2009/05/28 [83,85] BA1
BA1 N8
BA1 VSS
G8
BA2 M3 B3 BA2 M3 B3
[83,85] BA2 [83,85] BA2
1
BA2 VSS BA2 VSS
T1 T1
VSS R8418 VSS
A9 A9
CLKA0 VSS 243R2F-2-GP CLKA0 VSS
[83] CLKA0 J7 T9 [83] CLKA0 J7 T9
CLKA0# CK VSS CLKA0# CK VSS
[83] CLKA0# K7 E1 [83] CLKA0# K7 E1
CK# VSS CK# VSS
C P1 P1 C
2
FBA_CMD_18 VSS FBA_CMD_18 VSS
[83] FBA_CMD_18 UMA K9
CKE UMA [83] FBA_CMD_18 K9
CKE
1
G1 CLKA0# G1
swap for layout VSSQ swap for layout VSSQ
R8411
F9 F9
10KR2J-3-GP
DQMA#1 VSSQ DQMA#3 VSSQ

[83] DQMA#1 D3 E8 [83] DQMA#3 D3 E8
DMU VSSQ DMU VSSQ
1
DQMA#2 E7 E2 DQMA#0 E7 E2
[83] DQMA#2 DML VSSQ [83] DQMA#0 DML VSSQ
EC8402
D8 Revised FBCLK Termination D8

2
VSSQ VSSQ
D1 D1
SC6D8P50V2CN-GP
2
VSSQ VSSQ
[83,85] WE#
WE#
CAS#
L3
WE# VSSQ
B9 resistor value [83,85] WE#
WE#
CAS#
L3
WE# VSSQ
B9
[83,85] CAS# K3 B1 [83,85] CAS# K3 B1
CAS# VSSQ CAS# VSSQ
[83,85] RAS#
RAS# J3
RAS# VSSQ
G9 2009/06/05 [83,85] RAS#
RAS# J3
RAS# VSSQ
G9
DUMMY-K4W1G1646E-HC12-GP
Close to VRAM side DUMMY-K4W1G1646E-HC12-GP
Added CKE 64X16 SAMSUNG K4W1G1646E-HC12 P/N:72.41164.H0U

10K pull down R 64X16 HYNIX H5TQ1G63BFR-12C P/N:72.51G63.C0U
2009/06/05 SC-1203-2
change U8401, U8402 to ZZ.00PAD.R01 for layout
Place under / near VRAM Place under / near VRAM
1
1
C8422 C8423 C8424 C8425 C8426 C8427 C8428 C8429
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2
2
B B
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
C8404
C8410
C8405
C8409
C8414
C8415
C8413
1
1
C8408
C8411
C8412
2
2
Revised decoupling C 2009/05/28 Revised decoupling C 2009/05/28
A A
1st Samsung
Wistron Corporation
Title
VRAM(1/2)
www.vinafix.vn
A2
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
+1.5V_RUN_GPU
+1.5V_RUN_GPU
MDA[0..63] [83,84]
U8501
MDA[0..63] [83,84]
U8502
K8 E3 MDA46
VDD DQL0 MDA42 MDA63
K2 F7 K8 E3
N1 F2 K2 F7
R9 F8 N1 F2
B2 H3 R9 F8
D9 H8 B2 H3
G7 G2 D9 H8
D R1 H7 MDA[0..63] [83,84] G7 G2 D
VDD DQL7 VDD DQL6 MDA56
N9 R1 H7 MDA[0..63] [83,84]
VDD MDA51 VDD DQL7
D7 N9
DQU0 MDA52 VDD MDA36
A8 C3 D7
+1.5V_RUN_GPU VDDQ DQU1 MDA54 DQU0 MDA38
A1 C8 A8 C3
VDDQ DQU2 MDA49 +1.5V_RUN_GPU VDDQ DQU1 MDA33
C1 C2 A1 C8
VDDQ DQU3 MDA48 VDDQ DQU2 MDA39
C9 A7 C1 C2
1
VDDQ DQU4 MDA50 VDDQ DQU3 MDA34

D2 A2 C9 A7
VDDQ DQU5 VDDQ DQU4
1
E9 B8 MDA55 D2 A2 MDA37
R8510 VDDQ DQU6 MDA53 VDDQ DQU5 MDA32
F1 A3 E9 B8
1KR2F-3-GP VDDQ DQU7 R8501 VDDQ DQU6 MDA35
H9 F1 A3
VDDQ QSA6 1KR2F-3-GP VDDQ DQU7
H2 C7 QSA6 [83] H9
2
VDDQ DQSU QSA#6 VDDQ QSA4

B7 QSA#6 [83] H2 C7 QSA4 [83]
2
VREFA3 DQSU# VDDQ DQSU QSA#4
H1 B7 QSA#4 [83]
VREFDQ QSA5 VREFA4 DQSU#
M8 F3 QSA5 [83] H1
VREFCA DQSL VREFDQ
1 2 ZQ_VRAM21 L8 G3 QSA#5 M8 F3 QSA7
SCD01U16V2KX-3GP
ZQ DQSL# QSA#5 [83] VREFCA DQSL QSA7 [83]

1
R8509 243R2F-2-GP 2 ZQ_VRAM22 QSA#7

C8503
1 L8 G3
SCD01U16V2KX-3GP
QSA#7 [83]
1
1
FBA_CMD_28 ZQ DQSL#
C8506
K1 R8503 243R2F-2-GP
ODT FBA_CMD_28 [83]
1
R8507 MAA0 N3 K1 FBA_CMD_28
[83,84] MAA0 A0 ODT FBA_CMD_28 [83]
1KR2F-3-GP MAA1 P7 R8504 MAA0 N3
[83,84] MAA1 [83,84] MAA0
2
FBA_CMD_4 A1 FBA_CMD_8 1KR2F-3-GP MAA1 A0

[83] FBA_CMD_4 P3 L2 FBA_CMD_8 [83] [83,84] MAA1 P7
2
2
A2 CS# A1
1
FBA_CMD_6 N2 T2 MEM_RST FBA_CMD_4 P3 L2 FBA_CMD_8
[83] FBA_CMD_6 MEM_RST [83,84] [83] FBA_CMD_4 FBA_CMD_8 [83]
2
1
FBA_CMD_5 A3 RESET# FBA_CMD_6 A2 CS# MEM_RST
[83] FBA_CMD_5 P8 [83] FBA_CMD_6 N2 T2 MEM_RST [83,84]
FBA_CMD_13 A4 R8506 EC8502 FBA_CMD_5 A3 RESET#
[83] FBA_CMD_13 P2 [83] FBA_CMD_5 P8
MAA6 A5 10KR2J-3-GP FBA_CMD_13 A4
[83,84] MAA6 R8 T7 [83] FBA_CMD_13 P2
2
MAA7 A6 NC#T7 SC6D8P50V2CN-GP MAA6 A5
[83,84] MAA7 R2 L9 [83,84] MAA6 R8 T7
2
MAA8 A7 NC#L9 MAA7 A6 NC#T7
[83,84] MAA8 T8 L1 [83,84] MAA7 R2 L9
[83,84] MAA9 R3 J9 [83,84] MAA8 T8 L1
MAA10 A9 NC#J9 MAA9 A8 NC#L1
[83,84] MAA10 L7 J1 [83,84] MAA9 R3 J9
MAA11 A10/AP NC#J1 MAA10 A9 NC#J9
[83,84] MAA11 R7 [83,84] MAA10 L7 J1
MAA12 A11 MAA11 A10/AP NC#J1
[83,84] MAA12 N7 [83,84] MAA11 R7
MAA13 A12/BC# MAA12 A11
[83,84] MAA13 T3 J8 [83,84] MAA12 N7
A13 VSS MAA13 A12/BC#
M7 M1 [83,84] MAA13 T3 J8
NC#M7 VSS A13 VSS
M9 M7 M1
VSS NC#M7 VSS
J2 M9
BA0 VSS CLKA1 VSS
[83,84] BA0 M2 P9 J2
BA1 BA0 VSS BA0 VSS
[83,84] BA1 N8 G8 [83,84] BA0 M2 P9
BA2 BA1 VSS BA1 BA0 VSS
[83,84] BA2 M3 B3 [83,84] BA1 N8 G8
BA2 VSS BA1 VSS
1
T1 BA2 M3 B3
VSS [83,84] BA2 BA2 VSS
A9 R8517 T1
CLKA1 VSS 243R2F-2-GP VSS
[83] CLKA1 J7 T9 A9
CLKA1# CK VSS CLKA1 VSS
C
[83] CLKA1# K7 E1 [83] CLKA1 J7 T9 C
CK# VSS CLKA1# CK VSS
P1 [83] CLKA1# K7 E1
2
FBA_CMD_7 VSS CLKA1# CK# VSS
[83] FBA_CMD_7 K9 P1
CKE FBA_CMD_7 VSS
G1 [83] FBA_CMD_7 K9
1
VSSQ CKE
F9 G1
VSSQ VSSQ
1
R8508 DQMA#6 D3 E8 F9
[83] DQMA#6 DQMA#5 DMU VSSQ DQMA#4 VSSQ
10KR2J-3-GP EC8501 E7 E2 D3 E8
[83] DQMA#5 DML VSSQ [83] DQMA#4 DQMA#7 DMU VSSQ
D8 Revised FBCLK Termination [83] DQMA#7 E7 E2
2
SC6D8P50V2CN-GP VSSQ DML VSSQ

D1 D8
2
VSSQ VSSQ
[83,84] WE#
WE#
CAS#
L3
WE# VSSQ
B9 resistor value WE# VSSQ
D1
[83,84] CAS# K3 B1 [83,84] WE# L3 B9
CAS# VSSQ WE# VSSQ
[83,84] RAS#
RAS# J3
RAS# VSSQ
G9 2009/06/05 [83,84] CAS#
CAS# K3
CAS# VSSQ
B1
RAS# J3 G9
[83,84] RAS# RAS# VSSQ
DUMMY-K4W1G1646E-HC12-GP
Close to VRAM side
Added CKE DUMMY-K4W1G1646E-HC12-GP
10K pull down R SC-1203-2
2009/06/05 change U8501, U8502 to ZZ.00PAD.R01 for layout
+1.5V_RUN_GPU
Place under / near VRAM +1.5V_RUN_GPU
Place under / near VRAM
1
C8531 C8532 C8533 C8534
1
C8535 C8536 C8537 C8538
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
2
2
B B
+1.5V_RUN_GPU
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
C8520
C8519
C8518
C8517
C8516
EC8503
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
C8525
C8524
C8523
C8522
C8521
1
1
2
2
A A
1st Samsung
Wistron Corporation
Title
VRAM
www.vinafix.vn
A2
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_GFX
Vout=0.704V*(R1+R2)/R2
+PWR_SRC +PWR_SRC_GFX_CORE_
D D
PG8617
1 2 +PWR_SRC_GFX_CORE_
GAP-CLOSE-PWR
PG8613
SC2200P50V2KX-2GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
1 2
PC8603
1
1
PC8611
PC8606
PC8609
PC8604
GAP-CLOSE-PWR
PG8620 +3.3V_RUN_GPU
DY
1 2
2
1
5
6
7
8
D
D
D
D
GAP-CLOSE-PWR PR8634 PU8601
PG8605 100KR2J-1-GP DIS
1 2
DY SI7686DP-T1-GP
Thermal Design Current = 12.9A
2
GAP-CLOSE-PWR Max Current = 16.77A
G
S
S
S
PG8611
1 2
[25] GFX_CORE_PGOOD 18.45A<OCP<21.81A
4
3
2
1
SB-1103
GAP-CLOSE-PWR PU8603 PR8633 PC8616
2D2R3J-2-GP SCD1U25V3KX-GP +VCC_GFX_COREP +VCC_GFX_CORE
PR8632
1 11
+GFX_CORE_TRIP PGOOD GND +GFX_CORE_VBST 1
1 2 2 10 2 +GFX_CORE_VBST12 1 PL8601
73K2R2F-GP +GFX_CORE_EN TRIP VBST +GFX_CORE_DRVH PG8601
3 EN DRVH 9
+GFX_CORE_FB 4 8 +GFX_CORE_SW 1 2 2 1
PR8631 1 +GFX_CORE_CCM VFB SW +5V_ALW IND-1D5UH-34-GP
[37] GFX_CORE_EN 2 5 7
CCM V5IN
SCD1U10V2KX-4GP
+GFX_CORE_DRVL
GAP-CLOSE-PWR-3-GP
1KR2F-3-GP 6 GAP-CLOSE-PWR
DRVL
1
1
PTC8601 PTC8602 PG8619
SE330U2VDM-L-GP
SE330U2VDM-L-GP
C PR8638 1 PR8604 PC8617 PR8606 C
DY 2
DY DY 2 1
1+GFX_CORE_LL_R
[22,34,37,42,50,51] PM_SLP_S3#
5
6
7
8
PG8604
470KR2F-GP TPS51218DSCR-GP-U1 SC1U10V2KX-1GP PU8604 2D2R5F-2-GP
2
D
D
D
D
1
SIR460DP-T1-GE3-GP
PC8602
100KR2J-1-GP GAP-CLOSE-PWR
2
SC1KP50V2KX-1GP
PG8618
2
2 1
2
2
PC8634
GAP-CLOSE-PWR
1 GPU_VDD_SENS_GAP
S
S
S
PG8622
G
1 2
4
3
2
1
2009/08/05 PC8614 GAP-CLOSE-PWR
SC330P50V3KX-GP PG8612
DY
2
1 2
GAP-CLOSE-PWR
PG8621
1 2
Frequency setting SB-1023 PR8603 GAP-CLOSE-PWR

5K1R2F-2-GP PG8614
1. DY PD8601, PR8614, PR8618, PC8610, PQ8602, 1 2
470K -->290KHz PR8613; change PR8611 to 24.3K, PR8607 to 20K.
2
for N11M A3 change P12 stey Voltage to 0.85V GAP-CLOSE-PWR
200K -->340KHz PG8607
+GFX_CORE_FB 1 2
100K -->380KHz GAP-CLOSE-PWR
39K -->430KHz
1
PG8606
B DYPR8613
75KR2F-GP
PR8611
24K3R2F-1-GP
PR8607
20KR2F-L-GP
1 2 B
+3.3V_RUN_GPU GAP-CLOSE-PWR
PD8601 PG8608
2
PD8601_A 1
PWRCNTL_0#
DY
K A
DY 2
2009/08/26
1 2
1
B0530WS-7-F-GP PR8614 GAP-CLOSE-PWR
PR8619 5K1R2F-2-GP PG8602
10KR2F-2-GP 1 2
PWRCNTL_1#
PQ8602 GAP-CLOSE-PWR
2
PR8618 2N7002A-7-GP PG8615
1 PWRCNTL_0_R
DY
[81] PWRCNTL_0 2
DY G 1 2
2
+3.3V_RUN_GPU
SCD1U16V2KX-3GP
100KR2J-1-GP
10KR2F-2-GP GAP-CLOSE-PWR
DY
PC8610
PR8602
PG8610
S
DY 2009/08/05 1 2
2
1
PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE 2009/08/05

PR8620 GAP-CLOSE-PWR
D
1
H H 1.03V 10KR2F-2-GP PG8609
DY
PQ8601 1 2
H L 0.85V PR8617 2N7002A-7-GP
2
2 1 PWRCNTL_1_R G GAP-CLOSE-PWR
PG8603
[81] PWRCNTL_1
2
SCD1U16V2KX-3GP
100KR2J-1-GP
10KR2F-2-GP 1 2
PC8608
PR8616
DY
S
1
GAP-CLOSE-PWR
2
PR8621 PG8616
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L 10KR2F-2-GP 1 2
1
A Inductor: 1.5UH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat =33Arms 68.1R510.10J PD8615 1st Samsung A
K A PD8615_A 1 2 GAP-CLOSE-PWR
2
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01

H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 B0530WS-7-F-GP PR8615
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 5K1R2F-2-GP Wistron Corporation
Switching freq-->350KHz Taipei Hsien 221, Taiwan, R.O.C.
SC-1204-5
add PR8621 pull low 10K R Title
TPS51218 +VCC_GFX_CORE
Custom
Winery13 MB DIS A00
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
D D
+3.3V_RTC_LDO
+3.3V_RUN_GPU
SSID = VIDEO +15V_ALW
2
R8714
2
100KR2J-1-GP +3.3V_RUN_GPU
R8711
Peak current:360mA
1
3D3V_VGA_ON# 100KR2J-1-GP Design current: 252mA
1
1
C8704
SC10U6D3V5KX-1GP +3.3V_ALW
2
Q8710
4
Q8707 AO3434L-GP
D8706 DMN66D0LDW-7-GP R8713
A K 10KR2J-3-GP S D 1ST: 84.03434.031
RUN_ON_3D3GFX_R 2 1 RUN_ON_3D3GFX
2ND:
3
BAS16XV2T1G-GP-U
R8778
1
2KR2F-3-GP AO3434L-GP MAX 4.2A
G
2 1 C8708
[37] 3.3V_RUN_GPU_EN SCD01U50V2KX-1GP Rds(on) = 52 mOhm (Max)
2
1
C8786 3.3V_GPU_EN_R
SC1U6D3V2KX-GP
2
C +3.3V_RTC_LDO C
+1.05V_GFX_PCIE: +15V_ALW
2
R8712
2
100KR2J-1-GP +1.05V_GFX_PCIE
R8708
1
1D05V_VGA_ON# 100KR2J-1-GP
Design current:3550mA
1
1
C8701
SC10U6D3V5KX-1GP +1.05V_VTT
2
6
4
U8703
Q8704 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
R8716
3 S D 6
RUN_ON_1D05V_R 2 10KR2J-3-GP
1 RUN_ON_1D05V 4 G D 5
1
3
FDS8880-NL-GP 1ST: 84.08880.037
1
assign GPIO Added discharge circuit 10.7A 2ND: 84.04406.B37
C8705
2009/05/28 2009/06/17 SCD01U50V2KX-1GP Rds=12m ohm
2
1.05V_GFX_ON +1.5V_RUN_GPU
[37] 1.05V_GFX_ON
2
R8709 Place near device side(VGA chip),
+3.3V_RTC_LDO
+1.5V_RUN_GPU: +15V_ALW
DY 100R2J-2-GPuse 10 mil trace between power
rail and Q8701 Drain
1Q87_D
2
B B
R8715
D
2
100KR2J-1-GP +1.5V_RUN_GPU
R8710
Peak current:4230mA
1
1D5V_VGA_ON# Q8701
100KR2J-1-GP
1D5V_VGA_ON# G
DY 2N7002-7F-GP Design current:2961mA
1
1
C8702
S
SC10U6D3V5KX-1GP +1.5V_SUS
2
6
U8705
Q8705 1 S D 8
DMN66D0LDW-7-GP 2 S D 7
R8717
3 S D 6
RUN_ON_1D5V_R 2 10KR2J-3-GP
1 RUN_ON_1D5V 4 G D 5
1
FDS8880-NL-GP 1ST: 84.08880.037
1
10.7A 2ND: 84.04406.B37
C8707
SCD01U50V2KX-1GP Rds=12m ohm
2
1D5V_VGA_ON
[37] 1D5V_VGA_ON
A A
1st Samsung
Wistron Corporation
Title
LDO 1.8V
5 4 www.vinafix.vn 3 2
Size
Custom
Date:
Document Number
Winery13 MB DIS
Wednesday, January 13, 2010
1
Sheet 87 of
Rev
88
A00
5 4 3 2 1
Item Page# Date Request By Issue description Solution Description Rev.

01 66 2009/10/08 EE HDD LED light in S5. Change HDD LED power rail from +5V_ALW to +5V_RUN. SB
02 60 2009/10/08 EE External MIC NG. Add caps C6014 C6015. SB
03 66 2009/10/08 EE Correct battery LED color. Swap LED6601 pin2 & pin3. SB
04 49 2009/10/08 EE Improve VTT_PWRGD ramp up signal. Dummy C4912. SB
Change PR5102 from 2.2K to 3K and
D 05 51 2009/10/08 EE Fine tune +1.8V_RUN power on sequence behind +3.3V_RUN. SB D
PC5105 from 4700pF to 1uF.
06 54,78 2009/10/08 EE For KBC ESD protect. Add 100 ohm resistances R5413, R7803. SB
07
08 30 2009/10/08 EE Change CODEC to 92HD79. SB
09 64 2009/10/08 EE By ME request Change WLAN1 to 62.10043.841. SB
10
11 37 2009/10/09 EE Change board ID. Dummy R3708 and pop R3701. SB
12 79 2009/10/12 ME By ME request Change H6 to ZZ.00PAD.F91 SB
13 79 2009/10/12 ME By ME request Change H10 to ZZ.00PAD.D41 SB
14 78 2009/10/12 ME By ME request Change FP1 to 20.K0315.005 SB
15 27 2009/10/12 EE Follow Intel spec Remove L2701, C2701, C2702; Add TP2701 SB
16 27 2009/10/12 EE Follow Intel spec Remove L2704, C2721, C2722; Add TP2702 SB
17 27 2009/10/12 EE Cost down Change L2702, L2703 to 68.10050.10Y SB
18 24 2009/10/12 EE XTAL Load Capacitance as Vendor suggestion Change C2402, C2403 to 12pF SB
C C
19 81 2009/10/12 EE XTAL Load Capacitance as Vendor suggestion Change C8135, C8138 to 15pF SB
20 26 2009/10/13 EE Follow Intel spec Remove L2602, C2616; Add TP2601 SB
21 26 2009/10/13 EE Follow Intel spec Remove L2601, C2606; Add TP2602 SB
22 37 2009/10/13 EE Modify 10mW schematic SB
23 79 2009/10/13 ME By ME request Remove H9 (BT BOSS) SB
Change pg4910~pg4918 and pg4921
24 49 2009/10/13 EE By PSE request SB
close gap to mask type
25 73 2009/10/13 EE Two AFTP for +3.3V_RUN Remove AFTP6030 SB
26 34 2009/10/14 ME By ME request change NEW1 connector to 20.K0370.026 SB
27 79 2009/10/14 ME By ME request change SPR5 to 34.4F822.002 SB
28 64 2009/10/14 EE By AFTE request Add AFTP6402, AFTP6403 SB
29 79 2009/10/16 EE By RF request Add Cross Moat Caps SB
30 80,81 2009/10/16 EE Voltage Drop over 3% change bead value to 120 ohm DCR 0.55 ohm SB
31 22 2009/10/16 EE RTC data loss Added 3v/5v S5 power good to control resume reset SB
B sequence prevent RTC data loss B
32 25 2009/10/16 EE Swapped Q2515 C,E Pin SB

33 78 2009/10/16 EE remove CAPA_RST# from capacity board SB
34 37 2009/10/16 EE By SW request Added Switch Baord Detection circuit SB
A 1st Samsung A
Wistron Corporation
Title
Change List(1/3)
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1

01 37 2009/11/18 EE Correct R3745 power rail to KBC_PWR Change R3745 power rail to KBC_PWR SC
02 36 2009/11/25 EE TPM connector needn't AFTE test point Remove TPM1 AFTP SC
03 23 2009/11/25 EE No support HDMI and eDP so needn't pop 25MHz Xtal of PCH. C2313 pop 0 ohm if no use 25MHz XTAL SC
04 37 2009/11/25 EE Toggle VGA mode will flicker white screen in hybrid mode. Add U3703 mux for panel backlight enable signal select SC
D
05 54 2009/11/25 EE Toggle VGA mode will flicker white screen in hybrid mode. Add mux U5446 to select LCDVDD enable signal SC D
06 7 2009/11/30 RF For solve WiMAX noise Change C701 to 4.7pF for RF SC
07 43 2009/11/30 RF For solve WiMAX noise Pop PC4303 for RF SC
08 46 2009/11/30 RF For solve WiMAX noise Change PC4601 pull up to +5V_ALW for layout. SC
09 47 2009/11/30 EE For combine material item Change PC4762 to 0603 size SC
10 79 2009/11/30 ME For one hand hold issue, ODD have noise Add H15 for ME SC
11 79 2009/11/30 RF For solve WWAN noise Add RC7931 for RF SC
12 79 2009/11/30 RF For solve WiMAX noise Add SPR6 for RF SC
13 55 2009/12/04 EMI By EMI requirement Change L5501,L5502,L5503 for EMI SC
14 79 2009/12/04 EMI By EMI requirement Add EMI caps SC
15 81 2009/12/04 EMI By EMI requirement Add EC8101,EC8102,EC8103 for EMI SC
16 47 2009/12/04 ME For cosmatic issue when insert 8 cell battery Remove TC4701 for layout SC
17 79 2009/12/04 ME For cosmatic issue when insert 8 cell battery Change H2 to ZZ.00PAD.D11 SC
Base on Application Note: IDT 92H81/79 AUX Mode as input Connect U3001 pin17, pin18 to pin12 net and change
18 30 2009/12/04 EE of Diagnostic sound. R3016 to 120K for vendor request SC
C C
19 86 2009/12/04 EE Set PWRCNTL_1 for default low. Add PR8621 pull low 10K ohm SC
20 12 2009/12/07 EMI By EMI requirement Pop C1243 and change size to 0603 for EMI SC
Pop C3301, EC3302, EC3303, EC3305, EC3306, EC3307,
21 33 2009/12/07 EMI By EMI requirement EC3308 and change from 100p to 6.8p for EMI SC
22 54 2009/12/07 EMI By EMI requirement Pop EC5403 for EMI SC
23 60 2009/12/07 EMI By EMI requirement Pop EC6001 and EC6002 for EMI SC
24 63 2009/12/07 EMI By EMI requirement Pop R6307 for EMI SC
25 79 2009/12/07 ME For cosmatic issue when insert 8 cell battery Add H16 for ME SC
26 24 2009/12/08 EE Base on EA teset result, change to 0 ohm. Change R2413,R2414,R2415 from 15ohm to 0 ohm SC
27 53 2009/12/08 EE Base on ARD_Sightings_Report_18 #3622146 Change PR5311 from 4.7K to 470 ohm SC
28 60 2009/12/08 EE Audio AP LO THD+N fail Change EC6004,EC6005 from 0.1U to 0.01U SC
29 62 2009/12/08 EE Base on EA teset result, change to 0 ohm. Change R6206 from 15ohm to 0 ohm SC
30 68 2009/12/08 EE Change PCB Footprint Change Q6808 to 84.06402.B3D SC
31 73 2009/12/08 EMI By EMI requirement Pop L7301 for EMI SC
B B
A 1st Samsung A
Wistron Corporation
Title
Change List(2/3)
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1
5 4 3 2 1

01 34 2010/01/07 EE For no co-lay after XB remove R3402, R3403 A00
02 37 2010/01/05 EE Prevent SPI ROM data lost Add reset IC U3704 A00
03 46 2009/12/18 EE By POWER requirement changePL4602 from 2.2U to 3.3U A00
04 46 2009/12/18 EE TO improve +15V_Pump Power on issue pop PR4619; dummy PR4618 A00
D
05 51 2010/01/07 EE To prevent PM_SLP_S3# signal rebound change R5102 to short pad, PC5105 to 10K A00 D
06 52 2009/12/23 EE PREVNET MOS DEMAGE Change C701 to 4.7pF for RF A00
07 53 2009/12/18 EE By POWER requirement change PR5314 from 5.9K to 6.2K A00
08 55 2009/12/18 EMI By EMI requirement change L5501, L5502, L5503 to 0R A00
09 55 2009/12/18 EMI By EMI requirement change R5504, R5505, R5506 from 0R to 33R A00
10 55 2009/12/18 EMI By EMI requirement change C5520 from 22p to 10p A00
11 55 2010/01/04 ME By ME requirement change CRT1 from 20.20431.015 to 20.20401.015 A00
12 62 2010/01/04 ME By ME requirement change RCT1 from 20.D0210.102 to 20.D0075.102 A00
13 63 2010/01/06 EE For no co-lay after XB remove R6302, R6308,TR6301,TR6302, TR6303 A00
14 64 2010/01/07 EE For no co-lay after XB remove L6401 A00
15 73 2010/01/07 EE For no co-lay after XB remove R7302, R7303 A00
16 78 2009/12/23 EE TO PREVENT power pin short to GND when plug in cable dummy FP1 pin6, pin7 A00
17 78 2009/12/23 EE add damping resister R7804 add R7804 A00
18 79 2010/01/05 ME By ME requirement change SPR5 from 34.4F822.002 to 34.42T14.002 A00
C C
B B
A 1st Samsung A
Wistron Corporation
Title
Change List(3/3)
www.vinafix.vn
A3
Winery13 MB DIS A00
5 4 3 2 1

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5 4 3 2 1

Winery13 CALPELLA DIS N11M-GE1 Schematics

L1: Top Project code : 91.4EX01.001 +PWR_SRC +VCC_CORE

L2: GND Part Number : 48.4EX01.001

L5: VCC INPUTS OUTPUTS

USB 2.0 USB 2.0 x 1 PCIE x 1 Mini-Card

(3 in 1) 14 USB 2.0/1.1 ports Right Side:

480Mbps SATA ports (6) Free fall sensor USB 2.0 x 1

37 EMC2102 39,58 RT9025 51

HP OUT INPUTS OUTPUTS

ISL62883 ADP3211 TPS51218 TPS51218DSCR

+5V_ALW +3.3V_ALW +1.5V_CPU

+15V_ALW +3.3V_RTC_LDO +1.5V_RUN

+5V_USB2 +5V_RUN +5V_USB1 +3.3V_LAN +3.3V_CARDAUX +3.3V_RUN +1.8V_RUN +1.8V_RUN_GPU

Regulator LDO Switch

PCH SMBus Block Diagram +3.3V_ALW +3.3V_RUN

KBC SMBus Block Diagram N11M-GE1 +3.3V_RUN

SMBus address:0A SMBUS Block Diagram

Thermal Block Diagram Audio Block Diagram

DP2 VGA_THERMDA DPLUS

Thermal/Audio Block Diagram

Default (SPI): Leave both GNT0# and GNT1# floating. No pull up

Enable Intel Anti-Theft Technology:Connect to Vcc3_3

Platform design should provide appropriate pull-up or pull-down

1 GPIO8 Weak internal pull-up. Do not pull low.

SSID = Clock GEN

+3.3V_RUN +3.3V_RUN_SL585 +1.05V_VTT

C710 C711 C712

[23] CLKIN_DMI 0R4P2R-PAD 1 4 CLK_IN_DMI 13 16 CPU_STOP# R701 2 1 2K2R2J-2-GP

[23] CLK_PCIE_SATA 0R4P2R-PAD 1 4 CLK_PCIE_SATA1 10 SRC_1/SATA EC701

[23] CLK_CPU_BCLK 0R4P2R-PAD 2 3 CLK_CPU_BCLK1 23 27 CLK_XTAL_OUT 2N7002A-7-GP

Clock Generator SLG8SP585

PCI EXPRESS -- GRAPHICS

SSID = CPU [25] H_PECI AT15 PECI

TCK AN28 R923

JTAG & BPM

Remove XDP function for layout concern

SSID = CPU CPU1D 4 OF 9

SB_CK0 W8 M_CLK_DDR2 [19]

M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ40 AK3 AR5 M_B_DQS#6

DDR SYSTEM MEMORY - B

A CLARKUNF 1st Samsung A

TP1117 1 SB_DIMM_VREF# H17

15 -> 0, 14 -> 1, ... CFG10

0:Enabled; An external Display Port SA_CK2

CFG7 Clarksfield (only for early samples pre-ES1) -

Note: Only temporary for early CFD sample

Winery13 MB DIS A00

SSID = CPU +VCC_CORE

1.1V RAIL POWER

VCC VTT0 C1233 C1234

R28 AJ34 VCC_SENSE [47]

Winery13 MB DIS A00

+1.5V_CPU +1.5V_CPU +1.5V_CPU +1.5V_CPU

C1308 C1309 +1.05V_VTT

PEG & DMI

C1312 C1313 C1314 C1315 J25 H20