BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT

Avalahalli, Yelahanka, Bengaluru-64

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING

(Accredited by NBA-Tier II, Second time for 3 years 2019-20 to 2021-22 )

HDL LAB MANUAL: 18ECL58

Academic year : 2021-22
V Semester ETE

Designed & Compiled by,

Prof . Saritha I G
Assistant Professor
Department of ETE

Name : ………………………………………………………………………………………
USN : ………………………………………………………………………………………
Batch: ………………………………………………………………………………………

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 CONTENTS

Sl no Topics Page Nos

I. VTU Syllabus
II. Cycle of Experiments
III Introduction to HDL Lab
IV Introduction to FPGA
V PART A - Combinational & Sequential Circuits Programs
VI PART B -Interfacing Programs

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 INSTITUTION VISION AND MISSION
Vision
To emerge as one of the finest technical institutions of higher learning, to develop engineering
professionals who are technically competent, ethical and environment friendly for betterment of the
society.
Mission
Accomplish stimulating learning environment through high quality academic instruction, innovation
and industry-institute interface.

DEPARTMENT VISION AND MISSION

Vision
Emerge as premier department developing high quality Electronics & Telecommunication
Engineering professionals with ethics and eco friendliness for the betterment of the society.
Mission
Impart quality education in Electronics & Telecommunication Engineering by facilitating:
 Conducive learning environment and research activities
 Good communication skills, leadership qualities and ethics
 Strong Industry-Institute interaction

Program Educational Objectives (PEOs):

After three to four years of graduation our graduates will:
PEO 1: Excel as Professionals in Telecommunication, Electronics and IT related fields.
PEO 2: Engage in life-long learning.
PEO 3: Maintain ethical norms, exhibit good communication skills and leadership qualities.

Program Specific Outcomes (PSOs):

At the end of graduation our graduates will be able to:
PSO 1: Analyze and Design Communication Systems
PSO 2: Analyze and implement signal processing applications.
PSO 3: Design and implement embedded systems.

Course Outcomes (Cos):

Students will be able to:
CO 1: Conduct experiments using hardware components and software programs .
CO 2: Write a report for the conducted experiment
CO 3: Conduct open ended experiment in group related to Modulation techniques using
MATLAB/Simulink/Lab view/Equivalent
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 CO-PO/PSO Mapping Table
P P P P P P P P P P P P PS PS PS
O O O O O O O O O O O O O O O
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
CO1 3
CO2 2 2
CO3 2 2 2 2 2 2 2

DO’S

 Make sure your hands are dry and clean when you use computer

 Report any problems with your computer to the teacher immediately.

 After taking the kits, sign in the issue register with your USN and list of components

 Identify different ports and terminals of the evaluation board before making connection

 Handle the evaluation kit properly.

 After completing the circuit connection, consult with the staff member before switching it ‘ON’.

 The CRO once switched ‘ON’ need not switched ‘OFF’ till the completion of the experiment.

 After the completion of the experiment ensure that all AC Power Supply switches of the working table
are switched ‘OFF’.
 Always save your files in the folder named ‘BYxxECxxx’ in D: drive, for future reference

 Shut down the computer after the completion of the lab

 Return the kits taken from counter and get it verified from the instructor.

 Arrange the chairs/tables and equipment, properly before leaving the lab.

DON’T’S

 Do not keep your bags on the work bench

 Avoid unnecessary talking while doing the experiment

 Do not use cell phones, iPods, and any similar devices in labs.
 Do not loiter around in the lab.

 Do not throw bits & pieces around.

 Do not remove or disconnect any cable

 Avoid loose connections and short circuits

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 VTU SYLLABUS HDL LABORATORY
Laboratory Code:18ECL58 SEE Marks:60
Exam Hours;03 CREDITS: 02 CIE Marks:40
Number of Lecture Hours/Week 02Hr Tutorial (Instructions)+ 02 Hours Laboratory

Course Learning Objectives: This course will enable students to:

• Familiarize with the CAD tool to write HDL programs.
• Understand simulation and synthesis of digital design.
• Program FPGAs/CPLDs to synthesize the digital designs.
• Interface hardware to programmable ICs through I/O ports.
• Choose either Verilog or VHDL for a given Abstraction level

Note: Programming can be done using any compiler. Download the programs on a FPGA/CPLD board
and performance testing may be done using 32 channel pattern generator and logic analyser apart from
verification by simulation with tools such as Altera/Modelsim or equivalent.

Laboratory Experiments
PART A : Programming
1. Write Verilog program for the following combinational design along with test bench to
verify the design:
a. 2 to 4 decoder realization using NAND gates only (structural model)
b. 8 to 3 encoder with priority and without priority (behavioural model)
c. 8 to 1 multiplexer using case statement and if statements
d. 4-bit binary to gray converter using 1-bit gray to binary converter 1-bit adder and
subtractor.
2. Model in Verilog for a full adder and addfunctionality to perform logical operations of
XOR, XNOR,AND and OR gates. Write test bench with appropriate input patterns to
verify the modeled behavior.
3. Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by
selecting appropriatetest patterns. The functionality of the ALU is presented in Table 1.
a. Write test bench to verify the functionality of the ALU considering all possible input
patterns
b. The enable signal will set the output to required functions if enabled, if disabled all the
outputs are set to tri-state
c. The acknowledge signal is set high after every operation is completed Result[32:0]

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 4. Write Verilog code for SR, D and JK and verify the flip flop.
5. Write Verilog code for 4-bit BCD synchronous counter.
6. Write Verilog code for counter with given input clock and check whether it works as
clock divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of
the code.

PART-B: Interfacing and Debugging (EDWinXP, PSpice, MultiSim, Proteus, Circuit Lab
or any otherequivalent tool can be used)

1. Write a Verilog code to design a clock divider circuit that generates 1/2, 1/3rd and
1/4thclock from a given input clock. Port the design to FPGA and validate the
functionality through oscilloscope.
2. Interface a DC motor to FPGA and write Verilog code to change its speed and direction.
3. Interface a Stepper motor to FPGA and write Verilog code to control the Stepper motor
rotation which in turn may control a Robotic Arm. External switches to be used for
different controls like rotate the Stepper motor (i) +N steps if Switch no.1 of a Dip switch
is closed (ii) +N/2 steps if Switch no. 2 of a Dip switch is closed (iii) –N steps if Switch
no. 3 of a Dip switch is closed etc.
4. Interface a DAC to FPGA and write Verilog code to generate Sine wave of frequency F
KHz (eg. 200KHz) frequency. Modify the code to down sample the frequency to F/2
KHz. Display the Original andDown sampled signals by connecting them to an
oscilloscope.
5. Write Verilog code using FSM to simulate elevator operation.
6. Write Verilog code to convert an analog input of a sensor to digital form and to display
the same on asuitable display like set of simple LEDs, 7-segment display digits or LCD
display.

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 Course Outcomes: At the end of this course, students should be able to

• Write the Verilog/VHDL programs to simulate Combinational circuits in Dataflow,

Behavioral and Gate level Abstractions.
• Describe sequential circuits like flip flops and counters in Behavioral description and obtain
simulation waveforms.
• Synthesize Combinational and Sequential circuits on programmable ICs and test the
hardware.
• Interface the hardware to the programmable chips and obtain the required output

Conduct of Practical Examination

• All laboratory experiments are to be included for practical examination.

• Students are allowed to pick one experiment from the lot.
• Strictly follow the instructions as printed on the cover page of answer script for breakup of
marks.
• Change of experiment is allowed only once and Marks allotted to the procedure part to be
made zero

CYCLES OF EXPERIMENTS:
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 CYCLE EXPERIMENTS
1 1. Write Verilog program for the following combinational design along with
testbench to verify the design:
• 2 to 4 decoder realization using NAND gates only (Structural model)
• 8 to 3 encoders with priority and without priority (Behavioral model)
• 8 to 1 multiplexer using case statement and if statements.
• 4-bit binary to gray converter
2. Model in Verilog for a full adder and add functionality to perform logical
operations of XOR, XNOR, AND and OR gates. Write test bench with
appropriate input patterns to verify the modeled behavior.
3. Verilog 32-bit ALU and verify the functionality of ALU by selecting
appropriate test patterns
2 1. Write Verilog code for SR, D and JK and verify the flip flop.
2. Write Verilog code for 4-bit BCD synchronous counter.
3. Write Verilog code for counter with given input clock and check whether it
worksas clock divider performing division of clock by 2, 4, 8 and 16. Verify the
functionality of the code.
3 1. Write a Verilog code to design a clock divider circuit that generates 1/2, 1/3rd
and 1/4thclock from a given input clock. Port the design to FPGA and validate
the functionality through oscilloscope.
2. Interface a DC motor to FPGA and write Verilog code to change its speed and
direction.
3. Interface a Stepper motor to FPGA and write Verilog code to control the
Stepper motor rotation which in turn may control a Robotic Arm. External
switches to beused for different controls like rotate the Stepper motor (i) +N
steps if Switch no.1 of a Dip switch is closed (ii) +N/2 steps if Switch no. 2 of
a Dip switch is closed (iii) –N steps if Switch no. 3 of a Dip switch is closed etc.

4 4. Interface a DAC to FPGA and write Verilog code to generate Sine wave of
frequency F KHz (eg. 200 KHz) frequency. Modify the code to down sample
the frequency to F/2 KHz. Display the Original and Down sampled signals by
connecting them to an oscilloscope.
5. Write Verilog code using FSM to simulate elevator operation.
6. Write Verilog code to convert an analog input of a sensor to digital form and
to display the same on a suitable display like set of simple LEDs, 7-segment
displaydigits or LCD display.
5. Open Ended Experiments:
a.Design a 3bit priority encoder. The input I is 3-bit and the output P is 3-bit.I (0)
when high, has the highest priority, followed by I (1) and I (2).The output P for
highest Priority to lowest is 0, 1 and 2 (decimal). Respectively Construct the truth
table, minimize and write the Verilog codes for same .
b. Design a 4-bit parity generator .The output is 0 for even parity and 1 for odd
parity Write the Verilog codes for same .

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1.Introduction to HDL
An HDL is a programming language used to describe electronic circuit essentially digital logic circuits.
It can be used to describe the operation, design and organization of a digital circuit. It can also be used
to verify the behaviour by means of simulations. The principle difference between HDL and other
programming languages is that HDL is a concurrent language whereas the others are procedural i.e.
single threaded. HDL has the ability to model multiple parallel processes like adders, flip-flops etc which
execute automatically and independently of each other. It is like building many circuits that can operate
independently of each other.
The two widely used HDLs are:
1. VHDL: Very High Speed Integrated Circuits HDL.
2. Verilog HDL
VHDL (VHSIC Hardware Description Language) is a hardware description language used in
electronic design automation to describe digital and mixed-signal systems such as field-programmable
gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming
language. Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model
electronic systems. It is most commonly used in the design and verification of digital circuits at the
register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal
circuits, as well as in the design of genetic circuits.

1.1 Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed - signal
circuits at various levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming language so
that it would be familiar to engineers and readily accepted. The language is case- sensitive, has a
preprocessor like C, and the major control flow keywords, such as "if" and "while", are similar.
The formatting mechanism in the printing routines and language operators and their precedence are
also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to
define a block of code. The concept of time, so important to a HDL won't be found in C The language
differs from a conventional programming language in that the execution of statements is not strictly
sequential. A Verilog design consists of a hierarchy of modules are defined with a set of input, output,
and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and
sequential statements define the behavior of the module by defining the relationships between the
ports, wires, and registers Sequential statements are placed inside a begin/end block and executed in
sequential order within the block. But all concurrent statements and all begin/end blocks in the design
are executed in parallel, qualifying Verilog as a Dataflow language. A module can also contain one
or more instances of another module to define sub-behavior
A subset of statements in the language is synthesizable. If the modules in a design contains a netlist
that describes the basic components and connections to be implemented in hardware only
synthesizable statements, software can be used to transform or synthesize the design into the net list
may then be transformed into, for example, a form describing the standard cells of an integrated circuit
(e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).

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 Difference between Verilog and VHDL
1. VHDL is based on Pascal and ADA while Verilog is based on C language.
2. VHDL is strongly typed i.e., does not allow the intermixing, or operation of variables, with different
classes whereas Verilog is weakly typed.
3. VHDL is case insensitive and Verilog is case sensitive.
4. Verilog is easier to learn compared to VHDL.
5. Verilog has very simple data types, while VHDL allows users to create more complex data types.
6. Verilog lacks the library management, like that of VHDL

2.INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY)

FPGA contains a two dimensional arrays of logic blocks and interconnections between logic blocks.
Both the logic blocks and interconnects are programmable. Logic blocks are programmed to
implement a desired function and the interconnects are programmed using the switch boxes to connect
the logic blocks.
To implement a complex design (CPU for instance), the design is divided into small sub functions and
each sub function is implemented using one logic block. All the sub functions implemented in logic
blocks must be connected and this is done by programming the interconnects.

2.1 INTERNAL STRUCTURE OF AN FPGA

FPGAs, alternative to the custom ICs, can be used to implement an entire System On one Chip (SOC).
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 The main advantage of FPGA is ability to reprogram. User can reprogram an FPGA to implement a
design and this is done after the FPGA is manufactured. This brings the name “Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when produced in bulk
amounts. But FPGAs are easy to implement within a short time with the help of Computer Aided
Designing (CAD) tools.
FPGA DESIGN FLOW
1. Design Entry – the first step in creating a new design is to specify it's structure and functionality.
This can be done either by writing an HDL model using some text editor or drawing a schematic
diagram using schematic editor.
2.Design Synthesis – next step in the design process is to transform design specification into a more
suitable representation that can be further processed in the later stages in the design flow. This
representation is called the netlist. Prior to netlist creation synthesis toolchecks the model syntax
and analyse the hierarchy of your design which ensures that your design is optimized for the design
architecture you have selected. The resulting netlist is saved to a Native Generic Circuit (NGC) file
(for Xilinx® Synthesis Technology (XST) compiler) or an Electronic Design Interchange Format
(EDIF) file (for Precision, or Simplify/Simplify Pro tools).
3. Design Implementation: Implementation step maps netlist produced by the synthesis tool onto
particular device's internal structure. It consists from three steps:
a. Translate step – merges all incoming netlists and constraints into a Xilinx Native
Generic Database (NGD) file.
b. Map step - maps the design, specified by an NGD file, into available resources on the
target FPGA device, such as LUTs, Flip-Flops, BRAMs,... As a result, an Native
Circuit Description (NCD) file is created.
c. Place and Route step - takes a mapped Native Circuit Description (NCD) file, places
and routes the design, and produces an NCD file that is used as input for bit
stream generation.

Figure: FPGA Design Flow

4. Design Verification – is very important step in design process. Verification is comprised

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 of seeking out problems in the HDL implementation in order to make it compliant with the
design specification. A verification process reduces to extensive simulation of the HDL code.
Design Verification is usually performed using two approaches: Simulation and Static Timing
Analysis.
There are two types of simulation:
Functional (Behavioral) Simulation – enables you to simulate or verify a code syntax and
functional capabilities of your design. This type of simulation tests your design decisions before the
design is implemented and allows you to make any necessary changes early in the design process.
In functional (behavioral) simulation no timing information is provided.

Timing Simulation – allows you to check does the implemented design meet all functional and
timing requirements and behaves as you expected. The timing simulation uses the detailed
information about the signal delays as they pass through various logic and memory components and
travel over connecting wires. Using this information it is possible to accurately simulate the
behaviour of the implemented design. This type of simulation is performed after the design has been
placed and routed for the target PLD, because accurate signal delay information can now be
estimated. A process of relating accurate timing information with simulation model of the
implemented design is called Back-Annotation.
 Static Timing Analysis – helps you to perform a detailed timing analysis on mapped, placed
only or placed and routed FPGA design. This analysis can be useful in evaluating timing
performance of the logic paths, especially if your design doesn't meet timing requirements.
This method doesn't require any type of simulation.

5. Generate Programming File – this option runs BitGen, the Xilinx bitstream generation
program, to create a bitstream file that can be downloaded to the device.

6. Programming – iMPACT Programmer uses the output from the Generate Programming File
process to configure your target device.

7. Testing – after configuring your device, you can debug your FPGA design using the Xilinx
Chip Scope Pro tool or some external logic analyzer.

8. Estimate Power – after implementation, you can use the XPower Analyzer for estimation
and power analysis. XPower Analyzer is delivered with ISE Design Suite. With this tool you
can estimate power, based on the logic and routing resources of the actual design.

ABOUT XILINX ISE SOTWARE

Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx for synthesis
and analysis of HDL designs, enabling the developer to synthesize ("compile") their designs,
perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli,
and configure the target device with the programmer.
Xilinx ISE is a design environment for FPGA(Field programmable gate arrays) products from
Xilinx, and is tightly-coupled to the architecture of such chips, and cannot be used with FPGA
products from other vendors. The Xilinx ISE is primarily used for circuit synthesis and design, while
ISIM or the ModelSim logic simulator is used for system-level testing

STEPS TO EXECUTE A PROGRAM

1) Starting the ISE software
Start _ program _ XILINX ISE 7 _ Project Navigator
2) Creating a New Project in ISE
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 A project is a collection of all files necessary to create and to download a design to
aselected FPGA or CPLD devices.
Project name:
Project location:
Top-Level Source Type: HDL
Click Next to move to the project properties page.

3) Fill in the properties in the table as shown below

Device Family:
Spartan 3Device:
XC3S50 Package:
PQ208Speed Speed: -5
Top-Level Module Type: HDL
HDL Synthesis Tool: XST(VHDL/VERILOG)
Simulator: ISE Simulator (VHDL/ Verilog)
4) Creating an HDL Source
Create a top-level HDL file for the design. Determine the language that you wish to use(Verilog
module or VHDL module).This simple AND Gate design has two inputs: A and B. This design has
one output called C Click New Source in the New Project Wizard to add one new source to your
project.
a) Select VERILOG MODULE as the source type in the New Source dialog box.
b) Type in the file name for ex: and_gate
c) Verify that the Add to project checkbox is selected.
d) Click Next.
e) Define the ports for your Verilog source.
In the Port Name column, type the port names on three separate rows: A, B and C. In the Direction
column, indicate whether each port is an input, output, or inout. For A and B, select in from the list.
For C, select out from the list.
5) Click next in the Define Verilog Source dialog box.
6) Click Finish in the New Source Information dialog box to complete the new source file template.
Click Next in the New Project Wizard. Click next again.
7) Click Finish in the New Project Information dialog box.
ISE creates and displays the new project in the Sources in Project window and adds the and_gate.v
file to the project.
8) Double-click on the and_gate.v file in the Sources in Project window to open the Verilog file in the
ISE Text Editor. The and_gate.v file contains: Module name with the inputs and outputs declared.
9) Add the relationship between input and output after the input and output declared in module. Save
the file by selecting File > Save.
10) When the source files are complete, the next step is to check the syntax of the design. Syntax
errors and typos can be found using this step.
a)Select the counter design source in the ISE Sources window to display the related processes in
the Processes for Source window.
b) Click the “+”next to the Synthesize-XST process to expand the hierarchy.

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 c)Double-click the Check Syntax process.
11) When an ISE process completes, you will see a status indicator next to the process name.
a)If the process completed successfully, a green check mark appears.
b)If there were errors and the process failed, a red X appears.
c)A yellow exclamation point means that the process completed successfully, but some Warnings
occurred.
d)An orange question mark means the process is out of date and should be run again.
e)Look in the Console tab of the Transcript window and read the output and status messages
produced by any process that you run .Caution! You must correct any errors found in your source
files. If you continue without valid syntax, you will not be able to simulate or synthesize your
design.
12) After the successful check syntax in the process Examine RTL diagrams.
13) To Create Testbench waveform, Right click on file name in source window, and_gate.v and
add source.
14)Add testbench waveform source with a new file name and click next.
15)A timing window pops up. Click on combinatorial and click next.
16)A graphical window of input and output appears. Make changes according to the truth table and
save.
17) <file_name>.tb file is added to the project.
18)In source window change implementation to behavioral simulation.
19)In process window click on Xilix ISE simulator and RUN. Output window appears. Analyze the
waveforms according to the truth table.

20) Double-click the Assign Package Pins process found in the User Constraints process group. ISE
runs the Synthesis and Translate step and automatically creates a User Constraints File(UCF).
You will be prompted with the following message.
21)Click Yes to add the UCF file to your project. The file is added to your project and is visible in
the Sources in Project.
22) Now the Xilinx Pin out and Area Constraints Editor (PACE) opens.
23) You can see your I/O Pins listed in the Design Object List window. Enter a pin location for each
pin in the Loc column as specified below A: P1, B:P2, C:P3.
24) Click on the Package View tab at the bottom of the window to see the pins you just added. Put
your mouse over grid number to verify the pin assignment. (VHDL/ Verilog)

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 25) Right click on the Generate Programming file in the process view window and select run.
26) Under the Generate Programming file tab, right click on the Configure device (Impact) and
click on the Run option.
27)Select the appropriate BIT extension file in the pop up window.
28) Right click on the Chip picture in the pop up window and Select “Program”. Debug the errors
if it is there. Set the conditions for the inputs using Dip switch and observe the output.

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 HDL LAB 18ECL58

Generating a Program File

The Program File is created. It is written into a file called andgate.jed This is the actual
configuration data
1. Double Click the Generate Programming File process located near the bottom of theProcesses
for Source window. This section provides simple instructions for configuring a Spartan-3 xc3s200
Note: Your board must be connected to your PC before proceeding.

If the device on your board does not match the device assigned to the project, you will get errors.
Please refer to the IMPACT Help for more information. To access the help, select Help > Help
Topics To configure the device:
1. Click the “+” sign to expand the Generate Programming

2. Double click on the Configure device IMPACT

3. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected andClick Next.
4. Verify that Automatically connect to cable and identify Boundary-Scan chain is selectedand click
Finish

5. If you get a message saying that there was one device found, click OK to continue

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 HDL LAB 18ECL58

6.The iMPACT will now show the detected device, right click the device and select
NewConfiguration File.

7. The Assign New Configuration File dialog box appears. Assign a configuration file to
each device in the JTAG chain. Select the andgate.jed file and click Open
8. Right-click on the counter device image, and select Program... to open the Program
Options dialog box.
9. Click OK to program the device. ISE programs the device and displays
ProgrammingSucceeded if the operation was successful.
10. Close IMPACT without saving
. .

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 HDL LAB 18ECL58

BASIC PROGRAM – ALL LOGIC GATES

Aim: Write Verilog code to realize all the logic gates
Learning Objective: To study the Verilog code for all the logic gates
Algorithm:

 Start
 Initialize Input & output ports. .
 Construct the truth table and extract the expression.
 Write the Verilog code using a dataflow modeling style.
 verify the functionality of design with the truth table
 observe the timing diagram and verify
 End the program.

Logic Gates and Truth Table:

VERILOG CODE :
AND gate
module and_gate (a,b,c);
input a;
input b; output c;
assign c= a&b;
endmodule

OR gate
module or_gate (a,b,c);
input a; input b;
output c;
assign c= a|b;
endmodule

NOT gate
module not_gate (a,c);
input a;
output c;
assign c= ~a;
endmodule

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 HDL LAB 18ECL58

NAND gate
module nand_gate
(a,b,c);
input a; input b;
output c;
assign c= ~(a&b);
endmodule

NOR gate
module nor_gate
(a,b,c);
input a; input b;
output c;
assign c= ~(a|b);
endmodule

XOR gate
module xor_gate
(a,b,c);
input a; input b;
output c;
assign c= a^b;
endmodule

XNOR gate
Module xnor_gate
(a,b,c);
input a; input b;
output c;
assign c= ~(a^b);
endmodule

VERILOG CODE
module gates(a_in, b_in,
not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op); input a_in, b_in;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op
assign not_op= ~a_in;
assign and_op=a_in&b_in; assign nand_op=~(a_in&b_in);assign
or_op=a_in|b_in;
assign nor_op=~(a_in|b_in); assign xor_op=a_in^b_in;assign
xnor_op=~(a_in^b_in);
endmodule
Result: The Simulation has carried out and verified with respect to truth table.
Outcomes: Familiar with Verilog HDL Program, usage of Xilinx software and understand
ISE Simulator.

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HDL LAB 18ECL58

VIVA QUESTIONS
1. What is HDL?
2. What is the importance of HDL?
3. What are the differences between CPLD & FPGA?
4. What are the different types of HD Language?
5. What is Module?
6. What is entity & architecture?
7. What is package?
8. What is port?
9. Whether VHDL is case sensitive or not?
10. What is bit?
11. What is keyword?
12. What is binding?
13. What is import?
14. What is out port?
15. What is buffer?
16. What is inout port?
17. What are the different types of operator?
18. What is operator?
19. What are the different types of operator?
20. What are logical operators?
21. What are relational operators?
22. What are arithemetic operator?
23. What are shift operator?
24. What are Boolean logical operator?
25. What are rotate operator?
26. What is data type?
27. What are the different types of data types?
28. What are the different types of scalar types?
29. What are files types?
30. What are the different verilog data types?
31. What are the different types of styles or architecture?
32. What is behavioral description?
33. What is structural description?
34. What is switch level description?
35. What is data flow description?
36. What is mixed-language description?
37. What is simulation?
38. What is synthesis? What is wire?
39. What are the differences between VHDL & Verilog?
40. What is mixed-type description?
41. What is procedure?
42. What is function and task?

5
 HDL LAB 18ECL58

PIN SHEET OFXC3S400-5TQ144

FRC1 FRC2 FRC3
1 74 IO 1 84 IO 1 100 IO

2 76 IO 2 85 IO 2 102 IO

3 77 IO 3 86 IO 3

4 79 IO 4 87 IO 4 103 IO

5 78 IO 5 89 IO 5 105 IO

6 82 IO 6 90 IO 6 107 IO

7 80 IO 7 92 IO 7 108 IO

8 83 IO 8 96 IO 8 113 IO

9 VCC POWER 9 VCC POWER 9 VCC POWER

10 GND SUPPLY 10 GND SUPPLY 10 GND SUPPLY

FRC4 FRC6 FRC7

1 112 IO 1 28 IO 1 57 IO

2 116 IO 2 31 IO 2 59 IO

3 119 IO 3 33 IO 3 63 IO

4 118 IO 4 44 IO 4 69 IO

5 123 IO 5 46 IO 5 68 IO

6 131 IO 6 47 IO 6 73 IO

7 130 IO 7 50 IO 7 70 IO

8 137 IO 8 51 IO 8 20 IO

9 VCC POWER 9 VCC POWER 9 VCC POWER

10 GND SUPPLY 10 GND SUPPLY 10 GND SUPPLY

FRC5 FRC8 FRC10

1 1 IO 1 93 IO 1 60 IO

2 12 IO 2 95 IO 2 56 IO

3 13 IO 3 97 IO 3 41 IO

4 14 IO 4 98 IO 4 40 IO

5 15 IO 5 99 IO 5 36 IO

6 17 IO 6 194 IO 6 35 IO

7 18 IO 7 IO 7 32 IO

8 21 IO 8 122 IO 8 10 IO

9 23 IO 9 129 IO 9 11 IO

10 24 IO 10 132 IO 10 8 IO

11 26 IO 11 135 IO 11 7 IO

12 27 IO 12 140 IO 12 6 IO

13 5 13 5 13 5

14 -5 14 -5 14 -5

15 VCC 15 VCC 15 VCC

16 GND SUPPLY 16 GND SUPPLY 16 GND SUPPLY

6
HDL LAB 18ECL58

FRC9

1 5 IO

2 4 IO

3 2 IO

4 141 IO

5 NA IO

6 NA IO

7 NA IO

8 NA IO

9 VCC
POWER
10 GND SUPPLY

Clk 55

7
HDL LAB 18ECL58

PART– A
PROGRAMS

8
 HDL LAB 18ECL58

EXPERIMENT NO.1 :
1.Write Verilog program for the following combinational design along with test bench to verify the
design:
a. 2 to 4 decoder realization using NAND gates only (Structural model)
b. 8 to 3 encoders with priority and without priority (Behavioral model)
c. 8 to 1 multiplexer using case statement and if statements
d. 4-bit binary to gray converter.

Aim : To Verify Verilog program for the following combinational Logic circuits using test bench
to verify the design:
a. 2 to 4 decoder realization using NAND gates only (Structural model)
b. 8 to 3 encoders with priority and without priority (Behavioral model)
c. 8 to 1 multiplexer using case statement and if statements
d. 4-bit binary to gray converter.

a) 2 TO 4 DECODER using NAND gates.

Theory : 2 to 4 decoder: A decoder is a digital logic circuit that converts n-bits binary input code in to M output
lines. OR It is a logic circuit that decodes from binary to octal, decimal, Hexa-decimal or any other code such
as 7-segment etc.
The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The 2 binary inputs
labelled A and B are decoded into one of 4 outputs, hence the description of 2-to-4 binary decoder. Each output
represents one of the minterms of the 2 input variables, (each output = a minterm).

Truth Table
EN I1 I2 Y3 Y2 Y1 Y0
0 x x 1 1 1 1
1 0 0 1 1 1 0
1 0 1 1 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 1 1

9
 HDL LAB 18ECL58

Logic diagram :

VERILOG CODE
module decrd_2_to_4
( input i1,i0, E, output [3:0] Y );
wire s0,s1;
nand n1(s0,i0,i0);
nand n2(s1,i1,i1);
nand n3(Y[0],s1,s0,E);
nand n4(Y[1],s1,i0,E);
nand n5(Y[2],s0,i1,E);
nand n6(Y[3],i0,i1,E);
endmodule

Output Waveforms

10
 HDL LAB 18ECL58

b)(i) 8 TO 3 ENCODER WITHOUT PRIORITY

Theory: Encoder: The term ‘encode’ specifies the conversion of information(number or character) into a
coded form. An encoder is a combinational logic circuit that converts information such as a decimal number
or an alphabetic character, into some coded form. An encoder accepts an active level on one of its inputs
representing a digit, such as decimal or octal digit, and converts it to a coded output, such as binary or BCD.
Priority encoder: Whenever two or more inputs are applied at a time, internal hardware will check this
condition and if the priority is set such that higher numbered input should be taken into account and remaining
are considered as don’t care then output code will be appear will be “higher numbered input”.

Truth Table

INPUTS OUTPUTS
en Din(7) Din(6) Din(5) Din(4) Din(3) Din(2) Din(1) Din(0) Dout(0) Dout(1) Dout(2)
1 x x x x x x x x z z Z
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 x 0 0 1
0 0 0 0 0 0 1 x x 0 1 0
0 0 0 0 0 1 x x x 0 1 1
0 0 0 0 1 x x x x 1 0 0
0 0 0 1 x x x x x 1 0 1
0 0 1 x x x x x x 1 1 0
0 1 x x x x x x x 1 1 1

11
 HDL LAB 18ECL58

VERILOG CODE
module priori (en,Din,Dout);
input en;
input [ 7 : 0 ] Din;
output [ 2 : 0 ] Dout;
reg [ 2 : 0 ] Dout;
always@(en,Din)
begin
if(en == 1) // Active high enable
begin
Dout = 3'bZZZ; // Initializing Dout to high
Impedance
end
else
begin
casex(Din)
8'b00000001 :Dout = 3'b000;
8'b0000001X :Dout = 3'b001;
8'b000001XX :Dout = 3'b010;
8'b00001XXX :Dout = 3'b011;
8'b0001XXXX :Dout = 3'b100;
8'b001XXXXX :Dout = 3'b101;
8'b01XXXXXX :Dout = 3'b110;
8'b1XXXXXXX :Dout = 3'b111;
endcase
end
end
endmodule

12
 HDL LAB 18ECL58

Output Waveforms

13
 HDL LAB 18ECL58
c) 8 TO 1 MULTIPLEXER
Theory: The multiplexer is a combinational circuit which accepts several data inputs and allows only one
of them AT A TIME to get through to the output. A multiplexer has many input lines and one output line.
The signal from one input line will be directed to the output line. The input line is chosen based on the
signals which are carried to the multiplexer on another set of input lines called control lines. Multiplexers
are sometimes called selectors because they choose or select one of their inputs.
The number of control lines needed depends on the number of input lines. A multiplexer with 2 control
lines can select from 4 input lines, a multiplexer with 3 control lines can select from 8 input lines. In
general, a multiplexer with n control lines can select from up to 2ninput lines.
Truth Table:
S(2) S(1 S(0 Y
0 0) 0) D(0)
0 0 1 D(1)
0 1 0 D(2)
0 1 1 D(3)
1 0 0 D(4)
1 0 1 D(5)
1 1 0 D(6)
1 1 1 D(7)

Logic diagram :

14
HDL LAB 18ECL58

VERILOG CODE
module mux8_1(S,I,Y);

15
 HDL LAB 18ECL58
input [2:0] S;
input [7:0] I;
output Y;
reg Y;
always@(S,I)
begin
case(S)
3'b000:Y=I[0];
3'b001:Y=I[1];
3'b010:Y=I[2];
3'b011:Y=I[3];
3'b100:Y=I[4];
3'b101:Y=I[5];
3'b110:Y=I[6];
3'b111:Y=I[7];
endcase
end
endmodule

Output Waveforms

16
 HDL LAB 18ECL58

d) 4-BIT BINARY TO GRAYCONVERTER

Theory: The logical circuit which converts the binary code to equivalent gray code is known as
binary to gray code converter. An n-bit gray code can be obtained by reflecting an n-1 bit code
about an axis after 2n-1 rows and putting the MSB (Most Significant Bit) of 0 above the axis and the
MSB of 1 below the axis. Reflection of Gray codes.

Truth Table:

Logic diagram :

17
 HDL LAB 18ECL58

VERILOG CODE
module bin2gray(b,g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule

Output Waveforms

VIVA QUESTIONS:

1. What is package?
2. What is Library function?
3. What is process?
4. What is signal assignment operator?
5. What is signal?
6. What is Vector?
7. Why do we need Procedures, Tasks and Functions?
8. Explain the difference between Function and Procedure in VHDL?
9. Explain the difference between Function and Task in Verilog?
10. How do we specify the signals in Procedure‟s declaration?
11. Give an Example of a built-in Procedure?
12. Give an Example of a built-in Task?
13. Where the Procedures can be called from(from which part of the Program)?
14. Where the Tasks can be called from(from which part of the Program)?
15. Where the Functions can be called from(from which part of the Program) in VHDL?
16. Where the Tasks can be called from(from which part of the Program) in Verilog?
17. What does return statement do in Functions?
18. Give Examples for built-in Function?
19. What are the limitation for Mixed –Language Description?
20. What are the Advantages of Mixed-Language Description?

Results: Verilog program for the above combinational Logic circuits using test bench
and on FPGA Kit verified the design.

18
 HDL LAB 18ECL58
EXPERIMENT NO.2
Model in Verilog for a full adder and add functionality to perform logical operations of XOR,
XNOR, AND and OR gates. Write test bench with appropriate input patterns to verify the
modeled behavior.

AIM: Write Verilog code to describe the functions of a full Adder Using Behavior modeling style.

Theory: An Adder is a circuit which performs addition of binary numbers. Producing sum and carry.
An half adder is a digital circuit which performs addition of two binary numbers which are one bit
eachand produces a sum and a carry(one bit each). A full adder is a digital circuit which performs
addition of three binary numbers (one bit each), to produce a sum and a carry(one bit each). Full
adders are basic block of any adder circuit as they add two numbers along with the carry from the
previous addition .Column by column addition, similar to decimal addition is performed a logic circuit
known as half adder adds two 1 bit signals. In actual addition there is often a third bit, the carry bit
that must be added. Hence to add 3 bits at a time a logic circuit known as a Full adder is used.
Truth Table:

Logic diagram :

19
 HDL LAB 18ECL58

Behavioral Model
VERILOG CODE
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(a,b,cin)
begin
case ({a,b,cin}) // Concatenating (a,b,cin)
3'b000:{cout,sum}=2'b00;
3'b001:{cout,sum}=2'b01;
3'b010:{cout,sum}=2'b01;
3'b011:{cout,sum}=2'b10;
3'b100:{cout,sum}=2'b01;
3'b101:{cout,sum}=2'b10;
3'b110:{cout,sum}=2'b10;
3'b111:{cout,sum}=2'b11;
endcase
end
endmodule
Output Waveforms

Result: The Simulation has carried out and verified with respect to truth table.

Outcomes: Be able to design a model in three modeling style such as dataflow, behavioraland
structural.
VIVA QUESTIONS

1. Give an Example of a built-in Procedure?

2. Give an Example of a built-in Task?
3. Where the Procedures can be called from(from which part of the Program)?
4. Where the Tasks can be called from(from which part of the Program)?
5. Where the Functions can be called from(from which part of the Program) in VHDL?
6. Where the Tasks can be called from(from which part of the Program) in Verilog?
7. What does return statement do in Functions?
8. Give Examples for built-in Function?
9. What are the limitations for Mixed –Language Description?
10. What are the Advantages of Mixed-Language Description?

20
 HDL LAB 18ECL58
EXPERIMENT NO. 3
Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by selecting
appropriate test patterns. The functionality of the ALU is presented in Table 1
a. Write test bench to verify the functionality of the ALU considering all possible
input patterns.
b. The enable signal will set the output to required functions if enabled, if
disabled all the outputs are set to tri-state
c. The acknowledge signal is set high after every operation is completed
Opcode (2:0) ALU Operation Remarks
000 A+B Addition of two Both A and B are in two’s
numbers complement format
001 A–B Subtraction of
two numbers
010 A+1 Increment A is in two’s
Accumulator by 1 complement format
011 A-1 Decrement
accumulator by 1
100 A True Inputs can be in any
101 A Complement Complement format
110 A OR B Logical OR
111 A AND B Logical AND

AIM: Write a Verilog code of 32-bit ALU and test bench to verify the functionality of
the ALU considering all possible input patterns.

Theory: ALU is a basic building block of many types of computing circuits, including the
central processing unit (CPU), ALU performs bitwise arithmetic and logical operations on
integer binaries, in contrast to a floating-point unit (FPU).The ALU is one component of the
CPU (Central Processing Unit). Here, using VHDL we have designed a 32 bit ALU which can
perform the various arithmetic operations of Addition, Subtraction, Increment, Decrement,
Transfer, logical operations such as AND, OR, XOR, NOT and also the shift operation.
Truth Table:

21
 HDL LAB 18ECL58

Logic Circuit

VERILOG CODE
module alu32( a, b,en,cout,opcode,zout );
input [31:0] a,b;
output cout;
input[3:0] opcode;
output [31:0]zout;
reg [31:0]zout;
reg [32:0]temp;
reg cout;
always@( a, b, opcode)
begin
case(opcode)
4'b0001: temp = a + b;
4'b0010: temp = a - b;
4'b0011: temp[31:0]= ~a;
4'b0100: temp= a[15:0]* b[15:0];
4'b0101: temp[31:0]= a & b;
4'b0110: temp[31:0]= a | b;
4'b0111: temp[31:0]= ~(a & b);
4'b1000: temp[31:0]= a ^ b;
default : temp= 8'bZ;
endcase
zout=temp[31:0]; cout=temp[32];
temp[32]=0;
end
endmodule

22
 HDL LAB 18ECL58

Output Waveforms

23
HDL LAB 18ECL58
32 bit Arithmetic Logic Unit

VERILOG CODE

module alu32( a, b,en,cout,opcode,zout );

input [31:0] a,b;
output cout;
input[3:0] opcode;
output [31:0]zout;
reg [31:0]zout;
reg [32:0]temp;
reg cout;
always@( a, b, opcode)
begin
case(opcode)
4'b0001: temp = a + b;
4'b0010: temp = a - b;
4'b0011: temp[31:0]= ~a;
4'b0100: temp= a[15:0]* b[15:0];
4'b0101: temp[31:0]= a & b;
4'b0110: temp[31:0]= a | b;
4'b0111: temp[31:0]= ~(a & b);
4'b1000: temp[31:0]= a ^ b;
default : temp= 8'bZ;
endcase
zout=temp[31:0]; cout=temp[32];
temp[32]=0;
end
endmodule

24
 HDL LAB 18ECL58

EXPERIMENT NO.4
Write Verilog code for SR, D and JK and verify the flip flop.

AIM: Develop the Verilog code for the following flip-flop: SR, D, and JK.
Theory: SR flip-flop is a gated set-reset flip-flop. The S and R inputs control the state of the
flip-flop when the clock pulse goes from LOW to HIGH. The flip-flop will not change until the
clock pulse is on a rising edge. When both S and R are simultaneously HIGH, it is uncertain
whether the outputs will be HIGH or LOW.

4.1) SR FLIP – FLOP

VERILOG CODE
module sr(sr,clk,q,qb);
input clk;
input[1:0]sr;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bZ;
endcase
qb=~q;
end
endmodule

25
 HDL LAB 18ECL58

4.2)D-FLIP FLOP

Theory: The D flip-flop is a clocked flip-flop with a single digital input 'D'. Each time a D flip-
flop is clocked, its output follows the state of 'D'. The D Flip Flop has only two inputs D and CP.
The D inputs go precisely to the S input and its complement is used to the R input.

VERILOG CODE
module dff(d,clk,q,qb);
input d,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
q= d;
end
qb=~q;
endmodule

26
 HDL LAB 18ECL58

4.3) JK-FLIP FLOP

Theory:JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry.
The invalid or illegal output condition occurs when both of the inputs are set to 1 and are
prevented by the addition of a clock input circuit.

VERILOG CODE FOR TEST

BENCH WAVEFORM
module jkff1(jk,clk,q,qb);
input clk;
output q,qb;
reg q=0,qb=1;
input [1:0]jk;
always@(posedge clk)
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

27
HDL LAB 18ECL58

VERILOG CODE FOR

DOWNLOADING ONTO A
FPGA
module jkff1(jk,clk,q,qb);
input clk;
output q,qb;
reg q=0,qb=1;
input [1:0]jk;

reg[24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always@(posedge clkd[21])
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

28
HDL LAB 18ECL58

Result: The Simulation has carried out and verified with respect to truth table.

Outcomes: Be able to model a memory system with clock.

VIVA QUESTIONS
1. Which part of the Program provides information about the inputs, outputs and their types?
2. How do you map an array onto a logic diagram?
3. How the Sequential statements are mapped onto a logic diagram?
4. How the following codes can be mapped onto logic diagram?
a. Process(a,x,x1) b. Cases(ct) c. for i in 0 to 3 loop d. begin e. 1‟b0:4‟b d=a+b; f.
ifa(i)=‟1‟ g. then h. if(a = „1‟) then i. 1‟b1: ; j. result:=result+2**I k. endcase l. end if;
m. Else n.Y<=x1; o. end loop; p. End if;
5. How the Procedures/ tasks are mapped?
6. How the Functions are mapped?
7. Differentiate between procedure mapping and function mapping?
8. What is Simulation?
9. On what basis the codes are synthesized.
10. What is meant by mapping?
11. What are the functions of compiler?
12. Will different Simulators assign same number of gates for a single code?
13. Is there any differences between mapping or signal and variable assignment? Statement?
14. Differentiate between behavioral and structural descriptions?
15. In which applications behavioral desc is used?
16. Explain the Structure of behavioral?
17. Difference between process and always?
18. Explain Syntax of process?
19. What is Sensitivity list?
20. What is Event?
21. Is process a Concurrent or Sequential Statement?
22. What is “INITIAL”?
23. Why Label required for a statement?
24. Explain structure of IF-ELSE statement?
25. Explain structure of CASE statement?
26. Explain different Loops Structures?
27. How is For different from While?
28. How is 2‟s Compliment computed in VHDL?
29. Differentiate between Active High and Active Low Signal?
30. Differentiate between Synchronous and Asynchronous Clear Signal?

29
 HDL LAB 18ECL58

PROGRAM 5 - COUNTERS
Write Verilog code for 4-bit BCD synchronous counter.

AIM: Design 4 bit binary, BCD Counter (Synchronous reset and Asynchronous reset) and
“any sequence” Counters.
Theory: Counter is a sequential circuit. A digital circuit which is used for a counting pulses is
known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a
clock signal applied. Counters are of two types.
Asynchronous or ripple counters
Synchronous counters.
Application of counters
1.Frequency counters 2. Digital clock 3.Time measurement
4.A to D converter 5.Frequency divider circuits 6.Digital triangular wave generator.
Asynchronous or ripple counters: Asynchronous counters are those whose output is free from
the clock signal. Because the flip flops in asynchronous counters are supplied with different clock
signals, there may be delay in producing output. The required number of logic gates to design
asynchronous counters is very less. So they are simple in design.

5.1) SYNCHRONOUS RESET COUNTER

30
HDL LAB 18ECL58

VERILOG CODE
module syncnt(clk,reset,count);
input clk,reset;
output [3:0] count;
reg[3:0]count=4'b0000;
reg[24:0] clkd;
always@(posedge clk)
begin
clkd = clkd+1;
end
always @(posedge clkd[20])
begin
if(reset==1)
count = 4'b0000;
else
count = count+1;
end
endmodule

5.2)ASYNCHRONOUS RESET COUNTER

31
 HDL LAB 18ECL58

VERILOG CODE
module asyncnt(clk,reset,count);
input clk,reset;
output [3:0] count;
reg[3:0]count=4'b0;
reg[24:0] clkd;
always@(posedgeclk)
begin
clkd = clkd+1;
end
always @(posedge clkd[20] or posedge reset)
begin
if(reset==1)
count = 4'b0000;
else
count = count+1;
end
endmodule

5.3 Binary synchronous UP COUNTER

VERILOG CODE

32
 HDL LAB 18ECL58
module bin( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @ (posedgeclk)
begin
if (rst)
count =4'd0;
else
count = count +4'd1;
end
endmodule

5.5 Binary synchronous down COUNTER

VERILOG CODE
module bin( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @ (posedgeclk)
begin
if (rst)
count =4'd15;
else
count = count -4'd1;
end
endmodule

33
 HDL LAB 18ECL58
5.4 Binary asynchronous UP COUNTER

VERILOG CODE
module async_bin1( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
initial
begin
count =4'd0;
end
always @(posedge clk or posedge rst)
begin
if (rst)
count =4'd0;
else
count = count +4'd1;
end
endmodule

5.6 BCD Synchronous Reset Counter

34
HDL LAB 18ECL58

VERILOG CODE
module bin_sync( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
//reg [23:0] clkd;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bcd_out=bcd_out+4'd1;
else
bcd_out=4'd0;
end
endmodule

35
 HDL LAB 18ECL58

6.7 Four Bit BCD Asynchronous Reset Counter

VERILOG CODE
module bcd_async( clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] bcd_out;
//reg [23:0] clkd;
initial
begin
bcd_out=4'd0;
end
always @ (posedge clk or posedge rst)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
bcd_out=4'd0;
else if(bcd_out<4'd9)
bcd_out=bcd_out+4'd1;
else
bcd_out=4'd0;
end
endmodule

36
 HDL LAB 18ECL58

5.7 4 Bit 3 to 9 sequence Counter

VERILOG CODE
module seqcnt( clk, rst, count);
input clk, rst;
output [3:0] count;
reg [3:0] count;
//reg [23:0] clkd;
initial
begin
count=4'd0;
end
always @ (posedge clk or posedge rst)
begin
/*clkd = clkd+1;
end
always @ (posedge clkd[22])
begin */
if (rst)
count=4'd3;
else if(count<4'd9)
count=count+4'd1;
else
count=4'd3;
end
endmodule

Result: The Simulation has carried out and verified with respect to truth table.
Outcomes: Be able to model a memory system with clock Truth table implementation seen
VIVA QUESTIONS
1. What is meant by “Rising-Edge Signal”?
2. In Verilog how it is represented?
3. Differentiate between Casex and Casez?
4. Difference between Encoder with and without priority?
5. Difference between repeat and Forever in Verilog?
6. Difference between Next and Exit?
7. Difference between Syntax and Semantic Errors?
8. What is Port Map?
9. Explain different types of Mapping?
10. Does Verilog or VHDL have built in primitive Gates. Example?
11. What is Three state Output?
12. What is State mission?
13. Difference between Mealy and Moore Circuits
37
 HDL LAB 18ECL58

EXPERIMENT-6
Write Verilog code for counter with given input clock and check whether it works as clock
divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the code.
Aim: To write verilog code for counter with given input clock and check whether it works as clock
divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the code.

Theory: A clock divider circuit creates lower frequency clock signals from an input clock source.
The divider circuit counts input clock cycles, and drives the output clock low and then high for some
number of input clock cycles.

VERILOG CODE
module Clockdivider (clock,out);
input clock;
output [2:0]out;
reg [1:0]mod_threecounter = 2'b00;
reg [1:0] counter = 2'b00;
reg temp = 1'b0;
always@(posedge clock)
begin
counter = counter + 2'b01;
if (mod_threecounter ==2'b10)
mod_threecounter = 2'b00;
else
mod_threecounter = mod_threecounter + 2'b01;
end
always@ (negedge clock)
begin
temp = mod_threecounter[0];
end
assign out[0] = counter[0];
assign out[1] = temp & mod_threecounter[0];
assign out[2] = counter[1];
endmodule

38
 HDL LAB 18ECL58

EXPERIMENT-7
Write a Verilog code to design a clock divider circuit that generates 1/2, 1/3rd and 1/4thclock from a given
input clock. Port the design to FPGA and validate the functionality through oscilloscope.

Aim: Verilog project provides full Verilog code for the Clock Divider on FPGA together with Testbench for
simulation. The Verilog clock divider is simulated and verified on FPGA.
Theory: The frequency of the output clock_out is equal to the frequency of the input clock_out divided by the
value of the DIVISOR parameter in the Verilog code. F(clock_out) = F(clock_in)/DIVISOR
To change the clock frequency of the clock_out, just modify the DIVISOR parameter.
The frequency of the output clock_out is equal to the frequency of the input clock_out divided by the value of
the DIVISOR parameter in the Verilog code.
F(clock_out) = F(clock_in)/DIVISOR
To change the clock frequency of the clock_out, just modify the DIVISOR parameter.

Block Diagram

39
HDL LAB 18ECL58

VERILOG CODE for Clock divider on FPGA

module Clock_divider(clock_in,clock_out );
input clock_in; // input clock on FPGA
output reg clock_out; // output clock after dividing the input clock by divisor
reg[27:0] counter=28'd0;
parameter DIVISOR = 28'd2;
// The frequency of the output clk_out
// = The frequency of the input clk_in divided by DIVISOR
// For example: Fclk_in = 50Mhz, if you want to get 1Hz signal to blink LEDs
// You will modify the DIVISOR parameter value to 28'd50.000.000
// Then the frequency of the output clk_out = 50Mhz/50.000.000 = 1Hz
always @(posedge clock_in)
begin
counter <= counter + 28'd1;
if(counter>=(DIVISOR-1))
counter <= 28'd0;
clock_out <= (counter<DIVISOR/2)?1'b1:1'b0;
end
endmodule

Verilog Testbench code for the clock divider on FPGA

timescale 1ns / 1ps

// fpga4student.com FPGA projects, VHDL projects, Verilog projects
// Verilog project: Verilog code for clock divider on FPGA
// Testbench Verilog code for clock divider on FPGA
module tb_clock_divider;
// Inputs
reg clock_in;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog

40
HDL LAB 18ECL58
Clock_divider uut (
.clock_in(clock_in),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock_in = 0;
// create input clock 50MHz
forever #10 clock_in = ~clock_in;
end
endmodule

Simulation waveform for the clock divider in Verilog

41
HDL LAB 18ECL58

PART- B
INTERFACING
PROGRAMS

42
 HDL LAB 18ECL58

Experiment No 8:
Interface a DC motor to FPGA and write Verilog code to change its speed
and direction.
Aim : Write Verilog code to control speed and direction of DC.
Theory:

Reset Direction/rly PWM operation

0 0 01 stop
1 1 11 Anticlockwise
1 0 11 clockwise

Verilog Code
module dc(clk,rst,dir,row,pwm,rly);
input clk,rst,dir;
input [3:0] row;
output [1:0] pwm;
output rly;
reg rly;
reg [1:0] pwm=11;
reg [7:0] counter=11111110;
integer dutycycle = 100;
reg [12:0] dclk;
reg tick;
always@(posedge clk)
begin
dclk=dclk+1;
rly=dir;
end
always@(posedge dclk[12])
begin
tick=row[0]&row[1]&row[2]&row[3];
end
always@(negedge tick)
begin
case(row)
4'b1110:dutycycle=255;
4'b1101:dutycycle=200;
4'b1011:dutycycle=150;
4'b0111:dutycycle=100;
default:dutycycle=255;
43
 HDL LAB 18ECL58
endcase
end
always@(posedge dclk[12])
begin
if(!rst)
counter=8'b11111111;
else
counter = counter + 1;
end
always@(posedge dclk[12])
begin
if(counter>=dutycycle)
pwm=2'b01;
else
pwm=2'b11;
end
endmodule

Experiment 9 : Interface a Stepper motor to FPGA and write Verilog code to control the
Stepper motor rotation which in turn may control a Robotic Arm. External switches to be
used for different controls like rotate the Stepper motor (i) +N steps if Switch no.1 of a Dip
switch is closed (ii) +N/2 steps if Switch no. 2 of a Dip switch is closed (iii) –N steps if Switch
no. 3 of a Dip switch is closed etc
44
 HDL LAB 18ECL58
STEPPERMOTOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;

architecture Behavioral of steppermt is

signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div<= clk_div+'1';
end if;
end process;
process(rst,clk_div(15)) -- speed is maximumat15
begin
if rst='0' then shift_reg<="0001";
elsifrising_edge (clk_div(15)) then
if dir='1' then
shift_reg<= shift_reg(0) &shift_reg(3 downto 1);----Clockwise
else
shift_reg<= shift_reg( 2downto 0) &shift_reg(3);---Anticlockwise
end if;
end if;
end process;
dout<= shift_reg;

end Behavioral;

NET "clk" LOC ="p52";

NET "dir" LOC = "p85";
NET "rst" LOC = "p84";
NET "dout<0>" LOC = "p112";
NET "dout<1>" LOC = "p116";
NET "dout<2>" LOC = "p119";
NET "dout<3>" LOC = "p118";

45
 HDL LAB 18ECL58

CLOCKWISE (DIR= ‘1’) ANTICLOCKWISE (DIR=’0’)

A B C D A B C D
1 0 0 0 0 0 1 0
0 1 0 0 0 1 0 0
0 0 1 0 1 0 0 0
0 0 0 1 0 0 0 1
ABCD ABCD ABCD ABCD….. CBAD CBADCBAD CBAD…..

Reset Direction operation

0 X stop
1 1 clockwise
1 0 anticlockwise

When current is passed through the coil, the circular magnetic field is generated.

46
 HDL LAB 18ECL58

Experiment 10 :Interface a DAC to FPGA and write Verilog code to generate

Sine wave of frequency F KHz (eg. 200 KHz) frequency. Modify the code to
down sample the frequency to F/2 KHz. Display the Original and Down
sampled signals by connecting them to an oscilloscope.

a) DAC-SQUAREWAVE:

Ramp :
timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 15:00:06 01/05/2008

// Design Name:

// Module Name: rampwave

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module rampwave(clk,rst,dac_out);

input clk,rst;

output [7:0] dac_out;

47
 HDL LAB 18ECL58
reg [7:0] dac_out;

reg [3:0] temp=0000;

always@(posedge clk)

begin

temp=temp+1;

end

always@(posedge temp[3])

begin

if(rst)

dac_out=8'b0;

else

dac_out=dac_out+8;

end

endmodule

SAW:
timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 15:23:47 01/05/2008

// Design Name:

// Module Name: saw

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

48
 HDL LAB 18ECL58
// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module saw(clk,rst,dac_out);

input clk,rst;

output [7:0] dac_out;

reg [7:0] dac_out;

reg [3:0] temp=0000;

always@(posedge clk)

begin

temp=temp+1;

end

always@(posedge temp[3])

begin

if(rst)

dac_out=8'b0;

else

dac_out=dac_out+1;

end

endmodule

49
 HDL LAB 18ECL58

Sine :
timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 16:30:18 04/18/2008

// Design Name:

// Module Name: sine

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

50
 HDL LAB 18ECL58
// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module sine(rst,clk, dacout);

input rst,clk;

output [7:0] dacout;

reg [7:0] dacout;

reg [3:0] temp;

integer i;

reg [179:0] j [255:0];

always@(posedge(clk))

begin

for (i=0;i<180;i=i+1)

begin

j = 8'd128;

j = 8'd132;

j = 8'd136;

j = 8'd141;

j = 8'd154;

j = 8'd150;

j = 8'd154;

j = 8'd158;

j = 8'd163;

j = 8'd167;

51
HDL LAB 18ECL58
j = 8'd171;

j = 8'd175;

j = 8'd180;

j = 8'd184;

j = 8'd188;

j = 8'd192;

j = 8'd195;

j = 8'd199;

j = 8'd203;

j = 8'd206;

j = 8'd210;

j = 8'd213;

j = 8'd216;

j = 8'd220;

j = 8'd223;

j = 8'd226;

j = 8'd228;

j = 8'd231;

j = 8'd234;

j = 8'd236;

j = 8'd238;

j = 8'd241;

j = 8'd243;

j = 8'd244;

j = 8'd246;

j = 8'd247;

j = 8'd248;

j = 8'd249;

j = 8'd250;

52
HDL LAB 18ECL58
j = 8'd251;

j = 8'd252;

j = 8'd253;

j = 8'd254;

j = 8'd255;

j = 8'd255;

j = 8'd255;

j = 8'd255;

j = 8'd255;

j = 8'd254;

j = 8'd254;

j = 8'd253;

j = 8'd252;

j = 8'd251;

j = 8'd249;

j = 8'd246;

j = 8'd244;

j = 8'd243;

j = 8'd241;

j = 8'd238;

j = 8'd236;

j = 8'd234;

j = 8'd231;

j = 8'd228;

j = 8'd226;

j = 8'd223;

j = 8'd220;

j = 8'd216;

j = 8'd213;

53
HDL LAB 18ECL58
j = 8'd210;

j = 8'd206;

j = 8'd203;

j = 8'd199;

j = 8'd195;

j = 8'd192;

j = 8'd188;

j = 8'd184;

j = 8'd180;

j = 8'd175;

j = 8'd171;

j = 8'd167;

j = 8'd163;

j = 8'd158;

j = 8'd154;

j = 8'd150;

j = 8'd145;

j = 8'd141;

j = 8'd136;

j = 8'd132;

j = 8'd128;

j = 8'd123;

j = 8'd119;

j = 8'd114;

j = 8'd110;

j = 8'd105;

j = 8'd101;

j = 8'd97;

j = 8'd92;

54
HDL LAB 18ECL58
j = 8'd88;

j = 8'd84;

j = 8'd80;

j = 8'd75;

j = 8'd71;

j = 8'd67;

j = 8'd64;

j = 8'd60;

j = 8'd56;

j = 8'd52;

j = 8'd49;

j = 8'd45;

j = 8'd42;

j = 8'd39;

j = 8'd35;

j = 8'd32;

j = 8'd29;

j = 8'd27;

j = 8'd24;

j = 8'd21;

j = 8'd19;

j = 8'd17;

j = 8'd14;

j = 8'd12;

j = 8'd11;

j = 8'd9;

j = 8'd7;

j = 8'd6;

j = 8'd4;

55
HDL LAB 18ECL58
j = 8'd3;

j = 8'd2;

j = 8'd1;

j = 8'd1;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd0;

j = 8'd1;

j = 8'd1;

j = 8'd2;

j = 8'd3;

j = 8'd4;

j = 8'd6;

j = 8'd7;

j = 8'd9;

j = 8'd11;

j = 8'd12;

j = 8'd14;

j = 8'd17;

j = 8'd19;

j = 8'd21;

j = 8'd24;

j = 8'd27;

j = 8'd29;

56
 HDL LAB 18ECL58
j = 8'd32;

j = 8'd35;

j = 8'd39;

j = 8'd42;

j = 8'd45;

j = 8'd49;

j = 8'd52;

j = 8'd56;

j = 8'd60;

j = 8'd64;

j = 8'd67;

j = 8'd71;

j = 8'd75;

j = 8'd80;

j = 8'd84;

j = 8'd88;

j = 8'd92;

j = 8'd97;

j = 8'd101;

j = 8'd105;

j = 8'd110;

j = 8'd114;

j = 8'd119;

j = 8'd123;

j = 8'd128;

end

if (rst)

dacout<=8'b00000000;

57
 HDL LAB 18ECL58
else

if (i<180)

i=0;

else

begin

dacout<=j(i);

i=i+1;

end

end

endmodule

Square :
timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 12:41:45 01/05/2008

// Design Name:

// Module Name: squarewave

// Project Name:

// Target Devices:
58
 HDL LAB 18ECL58
// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module squarewave(clk,rst,dac_out);

input clk,rst;

output [7:0] dac_out;

reg [7:0] dac_out;

reg [3:0] temp=0000;

reg [7:0] counter;

always@(posedge clk)

begin

temp=temp+1;

end

always@(posedge temp[3])

begin

if(!rst)

counter=8'b0;

else

counter=counter+1;

end

always@(counter)

begin

59
 HDL LAB 18ECL58
if(counter<=127)

dac_out=8'b00000000;

else

dac_out=8'b11111111;

end

endmodule

Triangle

timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:31:31 01/05/2008
// Design Name:
// Module Name: tri
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tri();

endmodule
60
 HDL LAB 18ECL58

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;

architecture Behavioral of squarewg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

process(temp(3))
begin
if rst='1' then
cnt<="00000000";
elsifrising_edge (temp(3)) then if
cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsifcnt=0 then
61
 HDL LAB 18ECL58
en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process; end
Behavioral;

NET "clk" LOC = "p52" ; NET

"dac<0>" LOC = "p21" ; NET
"dac<1>" LOC = "p18" ; NET
"dac<2>" LOC ="p17" ; NET
"dac<3>" LOC ="p15"; NET
"dac<4>" LOC ="p14" ; NET
"dac<5>" LOC ="p13" ; NET
"dac<6>" LOC ="p12"; NET
"dac<7>" LOC ="p1" ; NET
"rst" LOC ="p74" ;

0000 0000-00000001=FF

Experiment 11: Write Verilog code using FSM to simulate elevator operation.

ELEVATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssg is
Port ( keyreturn : in STD_LOGIC_VECTOR (3 downto 0);
keyscan : buffer STD_LOGIC_VECTOR (3 downto 0):="1000";
segm : out STD_LOGIC_VECTOR (3 downto 0);
clk : inSTD_LOGIC;
dis : out STD_LOGIC_VECTOR (6 downto 0):="0000000"); end
ssg;
62
 HDL LAB 18ECL58

architecture Behavioral of ssg is

signal a,temp:integer range 0 to 15:=0;----initial content to be displayed after dumping
signal b:integer range 0 to 2000009;
begin
process(clk)
begin
if(clk'event and clk='1')then

keyscan<=keyscan(0) &keyscan(3 downto 1);

if keyscan="0001" and keyreturn="0001" thena<=0;

elsifkeyscan="0001" and keyreturn="0010" then a<=1;
elsifkeyscan="0001" and keyreturn="0100" then a<=2;
elsifkeyscan="0001" and keyreturn="1000" then a<=3;
elsifkeyscan="0010" and keyreturn="0001" then a<=4;
elsifkeyscan="0010" and keyreturn="0010" then a<=5;
elsifkeyscan="0010" and keyreturn="0100" then a<=6;
elsifkeyscan="0010" and keyreturn="1000" then a<=7;
elsifkeyscan="0100" and keyreturn="0001" then a<=8;
elsifkeyscan="0100" and keyreturn="0010" then a<=9;
elsifkeyscan="0100" and keyreturn="0100" then a<=10;
elsifkeyscan="0100" and keyreturn="1000" then a<=11;
elsifkeyscan="1000" and keyreturn="0001" then a<=12;
elsifkeyscan="1000" and keyreturn="0010" then a<=13;
elsifkeyscan="1000" and keyreturn="0100" then a<=14;
elsifkeyscan="1000" and keyreturn="1000" then a<=15;
endif;
end if;
endprocess;

Process(clk,a,temp)
begin
if(clk'event and clk='1')then
b<=b+1;
if(b=2000000)then ------Delay between one floor to next floor
if(temp<a) then -------a=current floor and temp= destination floor
temp<=temp+1 ;
b<=0;
elsif(temp/=a) then
temp<=temp-1 ;
b<=0;
end if;
end if;
end if;
end process;

63
 HDL LAB 18ECL58
process(temp) ---- when the key of destination floor is pressed process will be activated
type sevseg is array (0 to 15 )ofstd_logic_vector(6 downto 0);
constantsegdis:sevseg:= ( "1111110","0110000","1101101","1111001",
"0110011","1011011","1011111","1110000",
"1111111","1111011","1110111","0011111",
"1001110","0111101","1001111","1000111");
begin
dis<=segdis(temp);
segm<="1110";
end process;
end Behavioral;

CURRENT FLOOR DESTINATION FLOOR INCREMENT/DECREMENT

0 5
1 4
2 6
3 8
4 A
5 7
6 E
7 6
8 1
9 3
A 2
B 8
C 1
D 5
E 6
F 3
increment from 0 to 5
increment from 1 to 4
increment from 2 to 6
increment from 3 to 8
increment from 4 to A
increment from 5 to 7
increment from 6 to E
decrement from 7 to 6
decrement from 8 to 1
decrement from 9 to 3
decrement from A to 2
decrement from B to 8
decrement from C to 1
decrement from D to 5
decrement from E to 6
decrement from F to 3

64
 HDL LAB 18ECL58

Experiment no 12 Write Verilog code to convert an analog input of a sensor to

digital form and to display the same on a suitable display like set of simple LEDs,
7-segment display digits or LCD display.

SEVEN SEGMENTDISPLAY:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssg is
Port ( keyreturn : in STD_LOGIC_VECTOR (3 downto 0);
keyscan : buffer STD_LOGIC_VECTOR (3 downto 0):="1000"; segm :
out STD_LOGIC_VECTOR (3 downto 0);
clk : inSTD_LOGIC;
dis : out STD_LOGIC_VECTOR (6 downto 0):="0000000"); end
ssg;

architecture Behavioral of ssg is

signal a:integer range 0 to 15:=0;
begin
process(clk)
begin
if(clk'event and clk='1')then keyscan<=keyscan(0)
&keyscan(3 downto 1);
if keyscan="0001" and keyreturn="0001" then a<=0;
elsifkeyscan="0001" and keyreturn="0010" then a<=1;
elsifkeyscan="0001" and keyreturn="0100" then a<=2;
elsifkeyscan="0001" and keyreturn="1000" then a<=3;
elsifkeyscan="0010" and keyreturn="0001" then a<=4;
elsifkeyscan="0010" and keyreturn="0010" then a<=5;
elsifkeyscan="0010" and keyreturn="0100" then a<=6;
elsifkeyscan="0010" and keyreturn="1000" then a<=7;
elsifkeyscan="0100" and keyreturn="0001" then a<=8;
elsifkeyscan="0100" and keyreturn="0010" then a<=9;
elsifkeyscan="0100" and keyreturn="0100" then a<=10;
elsifkeyscan="0100" and keyreturn="1000" then a<=11;
elsifkeyscan="1000" and keyreturn="0001" then a<=12;
elsifkeyscan="1000" and keyreturn="0010" then a<=13;
elsifkeyscan="1000" and keyreturn="0100" then a<=14;
elsifkeyscan="1000" and keyreturn="1000" then a<=15;
endif;
end if;

65
 HDL LAB 18ECL58
end process; process(a)
type sevseg is array (0 to 15 )ofstd_logic_vector(6 downto 0);
constantsegdis:sevseg:= ("1111110","0110000","1101101","1111001",

"0110011","1011011","1011111","1110000",

"1111111","1111011","1110111","0011111",

"1001110","0111101","1001111","1000111");

begin
dis<=segdis(a);
segm<="1110";---To activate one segment out of four segments
end process;
end Behavioral;

NET "clk" LOC = "p52" ; NET

"dis<0>" LOC = "p18" ; NET
"dis<1>" LOC = "p17" ; NET
"dis<2>" LOC = "p15" ; NET
"dis<3>" LOC = "p14" ; NET
"dis<4>" LOC = "p13" ; NET
"dis<5>" LOC = "p12" ; NET
"dis<6>" LOC = "p1";
NET "keyreturn<0>" LOC = "p112" ;
NET "keyreturn<1>" LOC = "p116" ;
NET "keyreturn<2>" LOC = "p119" ;
NET "keyreturn<3>" LOC = "p118" ;
NET "keyscan<0>" LOC = "p123" ;
NET "keyscan<1>" LOC = "p131" ;
NET "keyscan<2>" LOC = "p130" ;
NET "keyscan<3>" LOC = "p137" ;
NET "segm<0>" LOC = "p27";
NET "segm<1>" LOC = "p26" ;
NET "segm<2>" LOC = "p24" ;
NET "segm<3>" LOC = "p23";
If common cathode, a=b=c=d=e=f=g= 1
Ifcommonanode, a=b=c=d=e=f=g=0
Keyscan / keyreturn 0111 1011 1101 1110
0111 0 1 2 3
1011 4 5 6 7
1101 8 9 A B
1110 C D E F

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 HDL LAB 18ECL58

Display a b c d e f g

0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1

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 HDL LAB 18ECL58

Open ended
1) 4-BIT COMPARATOR

Truth Table

Inputs Comparator O/P

a b agtb aeq altb
1000 100 0 b
1 0
0111 0
100 0 0 1
RTL Schematic 1000 0
011 1 0 0
1

VERILOG CODE

module comp(a,b,aeqb,agtb,altb);
input [3:0] a,b;
output aeqb,agtb,altb;
reg aeqb,agtb,altb;
always @(a ,b)
begin
aeqb=0; agtb=0; altb=0;
if(a==b) //checking for equality condition
aeqb=1;
else if (a>b) // checking greater than condition
agtb=1;
else
altb=1;
end
endmodule

2.Open ended Experiment

Design a 3bit priority encoder. The input I is 3-bit and the output P is 3-bit.
I (0) when high, has the highest priority, followed by I (1) and I (2).The
output P for highest Priority to lowest is 0, 1 and 2 (decimal). Respectively
Construct the truth table, minimize and write the Verilog codes for same .
3. Open ended Experiment

Design a 4-bit parity generator .The output is 0 for even parity and 1 for odd
parity Write the Verilog codes for same .

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