New DSD Manual Rvitm (4-7)

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RV Institute of Technology & Management
RashtreeyaSikshanaSamithi Trust
RV Institute of Technology and Management®
(Affiliated to VTU, Belagavi)
JP Nagar, Bengaluru – 560076
Department of Electronics and Communication Engineering
Course Name: DIGITAL SYSTEM DESIGN USING VERILOG LABORATORY

Course Code: 21EC32
III Semester
2021 Scheme
Prepared By
Dr. Madhumathy P
Dr. Vikash Kumar
Department of ECE
III-Semester, Lab Manual (21EC32), ECE Dept., RVITM1

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Laboratory Experiments
PART A : Programming
1 To simplify the given Boolean expressions and realize using Verilog program.
2 To realize Adder/Subtractor (Full/half) circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description a) Gray to
binary and vice versa b) Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder, Priority encoder
6 To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder, 2-bit Comparator
7 To realize using Verilog Behavioral description: Flip-flops: a) JK type b) SR type c) D type
8 To realize Counters - up/down (BCD and binary) using Verilog Behavioral description.
Demonstration Experiments
1 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the
specified direction (by N steps)
2 Verilog programs to interface a Relay or ADC to the FPGA/CPLD and demonstrate its
working.
3 Verilog programs to interface DAC to the FPGA/CPLD for Waveform generation.
4 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate its
working
III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 2

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FPGA Development Board

Features:
• XILINX SPARTAN6 XC6SLX4 device.
• 16 digit SMD LED interface.
• Interface 16 digit Logic inputs through Toggle switch and two push button switch
• 4 digit seven segment display
• 16X2 LCD interface
• Buzzer interface for tone generation.
• USB Programmer.
• EEPROM interface.
General description
 VFPGA-F-2.0 provides a hardware platform for developing embedded system using
SPARTAN6 XC6SLX4 device.
 These features make VFPGA-F-2.0 board ideal for instrumentation, communication and
other demanding application areas where flexibility and in-circuit hardware upgradeability
is of paramount important.
 VFPGA-2.0 board comes with complete drivers for windows98/Me/2000/XP/2007. 8051
code examples and windows DLL interface which can be used to interface it to most
common programming language. As it comes with complete with all XILINX ISE14.7
development software required and example code.it is also ideal as classroom training too
for colleges and universities as well as engineers wanting to learn more about hardware
development using SPARTAN6.
VFPGA6-2.0 board consists of the following.

 VFPGA-F-2.0 board fitted in soft wooden box.
 USB cable for BIT file downloading and 5V dc power for VFPGA-F-2.0 board.
 Technical/operational Manual with hardware schematics and sample programs.
 Software CD.

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Block Diagram of VFPGA6-2.0Microcontrollerkit
Buzzer 5V, 3.3V and 1.2V supply
Key Switch
Toggle Switch SPARTAN6 LCD Display

XC6SLX4
EEPROM
7segment Display
Flash Programmer
Fig. 1Block Diagram of VFPGA6
Starting the ISE14.7 Software
To start the ISE software, double-click the ISE Project Navigator icon on your desktop, or select
Start > All Programs > Xilinx ISE Design Suite 12.1 > ISE Design Tools > Project Navigator.
Project Navigator Desktop Icon Creating a New Project
To create a new project using the New Project Wizard, do the following:
1. From Project Navigator, select File > New Project.
Fig. 2 Project Navigator

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The New Project Wizard appears.
Fig. 3 New Project Wizard
2. In the Location field, browse to D:\vhdl ex\test\and.vhd or to the directory in which you
installed the project.
3. In the Name field, enter and.vhdor file name you want to creat.
4. Verify that HDL is selected as the Top-Level Source Type, and click Next.
The New Project Wizard—Device Properties page appears.
Fig. 4 Project Settings

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Select the following values in the New Project Wizard—Device Properties page:
 Product Category: All
 Family: Spartan6
 Device: XC6SLX4
 Package: TQG144
 Speed: -3
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISim (VHDL/Verilog)
 Preferred Language: VHDL or Verilog depending on preference. This will determine the
default language for all processes that generate HDL files.
Other properties can be left at their default values.
Click Next, then Finish to complete the project creation.
Creating an HDL-Based Module

Next you will create a module from HDL code. With the ISE software, you can easily create
modules from HDL code using the ISE Text Editor. The HDL code is then connected to your top-
level HDL design through instantiation and is compiled with the rest of the design.
You will author a new HDL module. This macro will be used to debounce the strtstop,mode and
lap_load inputs.
X-Ref Target - Figure 2-4
Using the New Source Wizard and ISE Text Editor
In this section, you create a file using the New Source wizard, specifying the name and ports of
the component. The resulting HDL file is then modified in the ISE Text Editor.
To create the source file, do the following:
1. Select Project > New Source.
The New Source Wizard opens in which you specify the type of source you want to create.
Fig.5New Source Wizard

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2. In the Select Source Type page, select VHDL Module.
Fig6New Source Wizard—Select Source Type Page
3. In the File Name field, enter file name for example and.
4. Click Next.
5. In the Define Module page, enter two input ports named a and b and an output Port named
cfor the debounce component as follows:
a. In the first three Port Name fields, enter sig_in, clkand sig_out.
b. Set the Direction field to input for a andb and to output for c.
Fig. 7 New Source Wizard—Define Module Page

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6. Click Next to view a description of the module.
Fig.8 New Source Wizard—Summary Page
7. Click Finish to open the empty HDL file in the ISE Text Editor.Following is an example
VHDL file.
Fig.9VHDL File in ISE Text Editor

Now Type c<= a and b; for AND gate execution. C is the output which stores the result of a
AND b. Save the file.

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8. Now double click on Synthesize-xst in the process pane and check for syntax errors.if any
errors are there correct them and resynthesize.
Fig.10Synthesis-XST page
9. Now expand the user constraints button and double click on I/O Pin planning(Plan Ahead)-
post synthesis.
Fig.11I/O pin Planning (Plan Ahead)-page
10. Now ISE project Navigator window will open and ask for opening plan ahead. Click on yes

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11. Now Plan Ahead 14.7 window will open.
12. Now select and expand required I/O bank
Fig.14I/O Bank Selection
13. Now select the proper input and output pin no‘s and save the changes.

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Fig.15I/O pin selection
14. Now close the Plan Ahead window and Double click on Generate Programming file. Now
the ISE project Navigator will generate and.bit file that will be used for downloading to FPGA
trainer kit.
Fig.16Generate Programming file -page

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Experiment 1
Simplify the given Boolean expressions and realize using Verilog program
Aim:To simplify the given Boolean expressions and realize using Verilog program.
Software Tools: Xilinx ISE Design Suite 13.1

Hardware: Spartan 6 FPGA Development Board
Theory:
A Boolean function is a special kind of mathematical function f:Xn→Xf: Xn→X of degree n,
where X={0,1}X={0,1} is a Boolean domain and n is a non-negative integer. It describes the way
how to derive Boolean output from Boolean inputs. A Boolean expression always produces a
Boolean value. A Boolean expression is composed of a combination of the Boolean constants (True
or False), Boolean variables and logical connectives. Each Boolean expression represents a Boolean
function.
Boolean expression approach: f m(1,3,4,5,10,12,13)
1 - 0001
3 - 0011
4 - 0100
5 - 0101
10 - 1010
12 - 1100
13 – 1101
Verilog Code
Verilog Code
Boolean Function: F = ~(AB+CD)

// Verilog code for AND-OR-INVERT gate
module AOI (A, B, C, D, F);
output F;
input A, B, C, D;

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assign F = ~((A & B) | (C & D));

endmodule
Test Bench code

module AOI_T;
wire F;
reg A;
reg B;
reg C;
reg D;
AOI uut (.A(A), .B(B),.C(C), .D(D), .F(F));
initial
begin
#10 A=1'b0;B=1'b0;C=1'b0;D=1'b0;
#10 A=1'b1;B=1'b0;C=1'b1;D=1'b1;
#10 A=1'b0;B=1'b0;C=1'b1;D=1'b1;
end
endmodule
Expected Waveform

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Result: The given Boolean expressions is realized using Verilog program

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Experiment 2
Adder (Full/half) circuits using Verilog data flow description
Aim: To Realize Adder (Full/half) circuits using Verilog data flow description
Theory:
Half Adder (HA):
Half adder is the simplest of all adder circuits. Half adder is a combinational arithmetic circuit that
adds two numbers and produces a sum bit (s) and carry bit (c) both as output. The addition of 2 bits
is done using a combination circuit called a Half adder. The input variables are augend and addend
bits and output variables are sum & carry bits. A and B are the two input bits.
Full Adder (FA):

A Full adder circuit, on a basic level is used to add 3 bits to give their sum and a carry.The
advantages of full adder include the following.
 Full adders hold the ability to add a carry bit which is the resulting from the previous addition
 With full adder, crucial circuits such as adder, multiplexer, and many others can be
implemented
 The full adder circuits consume minimal power
 The advantages of a full adder over a half adder are, a full adder is used to overcome the
drawback of a half adder because; half adder is mainly used to add two 1-bit numbers. Half
adders don‘t add the carry bit, so to overcome this full adder is employed. In Full adder, the
addition of three bits can be done and generates two outputs.

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 Designing of adders is simple and it is a basic building block so that one-bit addition can be
easily understood.
 This adder can be converted to half subtractor by adding an inverter.
 By using a full adder, high output can be obtained.
 High speed
 Very strong to supply voltage scaling
A full adder can be used as a part of many other larger circuits like
 Ripple carry adder, it adds n-bits at a time When connected with other full adders, say n
number of full adders, it can be used to create ripple adders of n-bits that perform addition in
series.
 carryout Multiplication -the dedicated multiplication circuit uses it.
 ALU- Arithmetic Logic Unit (one of the circuit is a full adder).
 to generate memory addresses inside a computer and to make the Program Counter point to
next instruction, the ALU makes use of this adder.
 For graphics related applications, where there is a very much need of complex computations,
the GPU uses optimized ALU which is made up of full adders, other circuits as well….
 Basically, it is used in designing ALU and this ALU is used for wide variety of applications
(from designing CPU to GPU).
Entity level diagram:
Truth Table:
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Program:
Half Adder (Using dataflow, BehavioralModeling):
module ha(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
assign sum=a^b;
assign carry=a&b;
endmodule
Testbench Code- Half Adder
modulehalfaddert_b;
reg a;
reg b;
wire sum;
wire carry;
hauut ( .a(a),.b(b),.sum(sum), .carry(carry));
initial begin
#10 a=1'b0;b=1'b0;
#10 a=1'b0;b=1'b1;
#10 a=1'b1;b=1'b0;
#10 a=1'b1;b=1'b1;
end
endmodule

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Full AdderVerilog Code:
modulefa(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
wired,e,f;
xor(sum,a,b,c);
and(d,a,b);
and(e,b,c);
and(f,a,c);
or(carry,d,e,f);
endmodule
Verilog Program for Test Bench:

modulefulladdt_b;
reg a;
reg b;
reg c;
wire sum;
wire carry;
fauut ( .a(a), .b(b),.c(c),.sum(sum),.carry(carry));
initial begin
#10 a=1'b0;b=1'b0;c=1'b0;
#10 a=1'b0;b=1'b0;c=1'b1;
#10 a=1'b0;b=1'b1;c=1'b0;
#10 a=1'b0;b=1'b1;c=1'b1;

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#10 a=1'b1;b=1'b0;c=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;
#10 a=1'b1;b=1'b1;c=1'b0;
#10 a=1'b1;b=1'b1;c=1'b1;
#10 $stop;
end
endmodule
Expected Waveform:
Half Adder
Full Adder

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Result:Adder (Full/half) circuits are realized using Verilog data flow description

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Experiment 3
4-bit ALU using Verilog program.
Aim: To realize 4-bit ALU using Verilog program.

Theory:
ALU is a main component of the central processing unit, which stands for arithmetic logic unit and
performs arithmetic and logic operations.
The operations performed by ALU are:
o Logical Operations: The logical operations consist of NOR, NOT, AND, NAND, OR,
XOR, and more.
o Bit-Shifting Operations: It is responsible for displacement in the locations of the bits to the
by right or left by a certain number of places that are known as a multiplication operation.
o Arithmetic Operations: Although it performs multiplication and division, this refers to bit
addition and subtraction. But multiplication and division operations are more costly to make.
In the place of multiplication, addition can be used as a substitute and subtraction for
division.

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Truth Table:
module ALU (a,b,en,opcode,y,ack);

input [31:0]a,b;
input en;
input [2:0]opcode;
output [31:0]y;
outputack;
reg [31:0]y, ack;
always@(en or opcode or a or b)
begin
if(en==0)y=32'dz;
else
case(opcode) 3'b000:y=a + b;
3'b001:y=a - b; 3'b010:y= a+1;
3'b011:y=a-1;
3'b100:y=a;
3'b101:y=~a;
3'b110:y=a | b; 3'b111:y=a & b;
default: y=32'dX;

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endcase
ack<=1;
end
endmodule
//Test bench
moduletest_ALU;
// Inputs
reg [31:0] a; reg [31:0] b;
reg en;
reg [2:0] opcode;
// Outputs
wire [31:0] y;
wire [31:0] ack;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.a(a),
.b(b),
.en(en),
.opcode(opcode),
.y(y),
.ack(ack)
);
initial begin en=1'b0;
#10 en=1'b1; a=32'h00000002; b=32'h00000001; opcode=3'b000;
#10 opcode=3'b001;
#10 opcode=3'b010;
#10 opcode=3'b011;

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#10 opcode=3'b100;
#10 opcode=3'b101;
#10 opcode=3'b110;
#10 opcode=3'b111;
#10 $finish;
end
endmodule
Expected Waveform:
4 bit ALU
32 bit ALU
Result:32-bit ALU using Verilog program is realised

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Experiment 4
Gray to binary and vice versa
Binary to excess3 and vice versa
Aim: Write a Verilog code for Gray to binary and vice versa b) Binary to excess3 and vice versa using
verilog program
Theory:
Conversion of Binary to Gray Code

Gray codes are used in rotary and optical encoders, Karnaugh maps, and error detection. The hamming
distance of two neighbours Gray codes is always 1 and also first Gray code and last Gray code also has
Hamming distance is always 1, so it is also called Cyclic codes.
Using Karnaugh (K) - map −You can construct Gray codes using other methods but they may not be
performed in parallel like given above method. For example, 3 bit Gray codes can be contracted using K-
map which is given as following below:
Decimal Binary Gray Code
0 000 000
1 001 001
2 010 011
3 011 010
4 100 110

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Decimal Binary Gray Code
5 101 111
6 110 101
7 111 100
Using Reflect and Prefix method −

n-bit Gray code can be generated recursively using reflect and prefix method which is explained as
following below.
 Generate code for n=1: 0 and 1 code.

 Take previous code in sequence: 0 and 1.
 Add reversed codes in the following list: 0, 1, 1 and 0.
 Now add prefix 0 for original previous code and prefix 1 for new generated code: 00, 01, 11, and 10.
Therefore, Gray code 0 and 1 are for Binary number 0 and 1 respectively. Gray codes: 00. 01, 11, and 10
are for Binary numbers: 00, 01, 10, and 11 respectively. Similarly you can construct Gray code for 3 bit
binary numbers:
Using Exclusive-Or (⊕) operation −

This is very simple method to get Gray code from Binary number. These are following steps for n-bit
binary numbers −

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 The most significant bit (MSB) of the Gray code is always equal to the MSB of the given Binary code.
 Other bits of the output Gray code can be obtained by XORing binary code bit at the index and previous
index.
For example, for 3-bit binary number, let Binary digits are b 2 , b1 , b0, where b2 is the most significant bit
(MSB) and b0 is the least significant bit (LSB) of Binary. Gray code digits are g 2 , g1 , g0, where g2 is the
most significant bit (MSB) and g0 is the least significant bit (LSB) of Gray code.
Binaryb2 b1 b0 Gray Codeg2 g1 g0
000 000
001 001
010 011
011 010
100 110
101 111
110 101
111 100
Therefore, you solve boolean expression using k-map, you will get g2=b2, g1=b1⊕b2, and g0=b0⊕b1.

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Similarly, you can convert n-bit (bnb(n-1)...b2b1b0) Binary number into Gray code (gng(n-1)...g2g1g0). For least
significant bit (LSB) g0=b0⊕b1, g1=b1⊕b2, g2=b1⊕b2 , …. g(n-1)=b(n-1)⊕bn, gn=bn.
Example −Convert Binary number 111010 into Gray code.
So, according above algorithm,
g0=b0⊕b1 = 0⊕1 = 1
g1=b1⊕b2 = 1⊕0 = 1
g2=b2⊕b3 = 0⊕1 = 1
g3=b3⊕b4 = 1⊕1 = 0
g4=b4⊕b5 = 1⊕1 = 0
g5=b5 = 1 = 1
So, Gray will be 100111.
Conversion of Gray to Binary Code

Gray codes are used in rotary and optical encoders, Karnaugh maps, and error detection. The hamming
distance of two neighbours Gray codes is always 1 and also first Gray code and last Gray code also has
Hamming distance is always 1, so it is also called Cyclic codes. You can convert a Gray code to Binary
number using two methods.
Using Karnaugh (K) - map −
You can construct Gray codes using other methods but they may not be performed in parallel like given
above method. For example, 3 bit Gray codes can be contracted using K-map which is given as following
below:
Decimal Gray Code Binary
0 000 000
1 001 001

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Decimal Gray Code Binary
2 011 010
3 010 011
4 110 100
5 111 101
6 101 110
7 100 111
Using Exclusive-Or (⊕) operation −

This is very simple method to get Binary number from Gray code. These are following steps for n-bit
binary numbers −
 The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given binary number.
 Other bits of the output binary code can be obtained by checking gray code bit at that index. If current gray
code bit is 0, then copy previous binary code bit, else copy invert of previous binary code bit.
For example, for 3-bit binary number, let Binary digits are b 2 , b1 , b0, where b2 is the most significant bit
(MSB) and b0 is the least significant bit (LSB) of Binary. Gray code digits are g 2 , g1 , g0, where g2 is the
most significant bit (MSB) and g0 is the least significant bit (LSB) of Gray code.
Gray Codeg2g1g0 Binaryb2b1b0
000 000
001 001
011 010
010 011
110 100

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Gray Codeg2g1g0 Binaryb2b1b0
111 101
101 110
100 111
Therefore, you solve boolean expression using k-map, you will get b2=g2, b1=g1⊕g2, and b0=g0⊕g1⊕g2.
Similarly, you can convert n-bit (bnb(n-1)...b2b1b0) Binary number into Gray code (gng(n-1)...g2g1g0). For least
significant bit (LSB) bn=gn, b(n-1)=g(n-1)⊕gn, …. b1=g1⊕g2⊕g3...⊕gn and b0=g0⊕g1⊕g2⊕g3...⊕gn.
Example − Convert Gray code 100111 into Binary number.
So, according above algorithm,
b5=g5=1=1
b4=g5⊕g4 =1⊕0 =1
b3=b4⊕g3 =1⊕0 =1
b2=b3⊕g2 =1⊕1 =0
b1=b2⊕g1 =0⊕1 =1
b0=b1⊕g0 =1⊕1 =0
So, Binary number will be 111010.
Excess-3, as its name says, there is an excess of number 3. That means we add 3 to a decimal digit
to get the corresponding Excess-3 number. We get the Excess-3 code of a corresponding decimal
number by adding 3 to its individual digits.

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If we want to convert a binary number to Excess-3 code or vice versa, then we need to take decimal
as the intermediary. This means for, binary to Excess-3 code conversion, we need to convert the
binary number to decimal number first, then convert the decimal number to final Excess-3 code as
done above.
Following are few advantages of Excess-3 code:
 Excess-3 code is beneficial for the arithmetic operation where the 8421 BCD addition
exceeds the value 9.
 Excess-3 representation can be used as codeword representation for data transmitted on
transmission line as it does not use both 0000 and 1111, which are more prone to
transmission error.
 Excess-3 code is self-complementing. Therefore, it is beneficial in case of subtraction
//Binary to Gray Code Converter:
module bin2gray (input [3:0] bin, output [3:0] G);

assign G[3] = bin[3];
assign G[2] = bin[3]^bin[2];
endmodule
module gray2bin (input [3:0] G, output [3:0] bin);

assign bin[3] = G[3];
assign bin[2] = G[3]^G[2];
assign bin[1] = G[3]^G[2]^G[1];
assign bin[0] = G[3]^G[2]^G[1]^G[0];
endmodule
module tb;
// Inputs
reg [3:0] bin;
// Outputs
wire [3:0] G;

bin2gray uut (
.bin(bin),
.G(G)
);

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always begin
// Initialize Inputs
bin<=0; #10;
bin<=1; #10;
bin<=2; #10;
bin<=3; #10;
bin<=4; #10;
bin<=5; #10;
bin<=6; #10;
bin<=7; #10;
bin<=8; #10;
bin<=9; #10;
bin<=10; #10;
bin<=11; #10;
bin<=12; #10;
bin<=13; #10;
bin<=14; #10;
bin<=15; #10;
#100; $stop;
end
endmodule

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//Gray to Binary code

module gr2bi #(
parameter N = 4
) (
input [N-1:0] gr,
output reg [N-1:0] bi
);
integer i = N-2;
always @(*) begin

bi[N-1] = gr[N-1];
for (i=N-2;i>=0;i=i-1)
bi[i] = gr[i] ^ bi[i+1];
end
endmodule
module tb;
parameter N = 4;
reg [N-1:0] gr;

wire [N-1:0] bi;
initial begin
gr = 0;
repeat (2**N) begin
#10;
gr = gr + 1;
end
end
gr2bi #(
.N (N)
) UUT (
.gr (gr),
.bi (bi)
);
endmodule

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Binary to excess3
module Bin_excess(b,e);
input [2:0] b;
output wire [2:0] e;
assign e[2]=b[0]|b[1]|b[2];
assign e[1]=b[2]|~(b[1]^b[0]);
assign e[0]=~b[0];
endmodule
//TEST BENCH
module BIN_EXCESS3_tb;
// Inputs
reg [2:0] b;
// Outputs
wire [2:0] e;
Bin_excess uut (
.b(b),
.e(e)
);
initial begin

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b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
b=3’b000;
#100;
b=3’b001;
#100;
b=3’b010;
#100;
b=3’b011;
#100;
end
endmodule
Result: Verilog code forGray to binary and vice versa b) Binary to excess3 and vice versausing verilog
programis verified.

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Experiment 5
8:1 mux, 8:3 encoder, Priority encoder
Aim: Write a Verilog code for 8:1 mux, 8:3 encoder, Priority encoder
Theory:
The multiplexer or MUX is a digital switch, also called as data selector. Multiplexer is a
combinational circuit that has maximum of 2n data inputs, ‗n‘ selection lines and single output line.
One of these data inputs will be connected to the output based on the values of selection lines. Since
there are ‗n‘ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux. 8x1 Multiplexer has 8
data inputs, 3 selection lines and one output. These are mostly used to form a selected path between
multiple sources and a single destination. A basic multiplexer has various data input lines and a
single output line. These are found in many digital system applications such as data selection and
data routing, logic function generators, digital counters with multiplexed displays, telephone network,
communication systems, waveform generators, etc. In this article we are going to discuss about types
of multiplexers and its design. In all types of digital system applications, multiplexers find its
immense usage. Since these allows multiple inputs to be connected independently to a single output,
these are found in variety of applications including data routing, logic function generators, control
sequencers, parallel-to serial converters, etc. Data Routing: Multiplexers are extensively used in data
routing applications to route the data to a one particular destination from one of several sources.
Entity level diagram and truth table
S2 S1 S0 Y
0 0 0 10
0 0 1 11
0 1 0 12
0 1 1 13
1 0 0 14
1 0 1 15
1 1 0 16
1 1 1 17

®
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines; hence it encodes the information from 2 n inputs into
an n-bit code. It will produce a binary code equivalent to the input, which is active High. Therefore,
the encoder encodes 2n input lines with ‘n‘ bits. Encoders are very common electronic circuits used
in all digital systems. Encoders are used to translate the decimal values to the binary in order to
perform the binary functions such as addition, subtraction, multiplication, etc. One of the main
disadvantages of standard digital encoders is that they can generate the wrong output code when
there is more than one input present at logic level ―1‖. One simple way to overcome this problem
is to ―Prioritise‖ the level of each input pin. if there is more than one input at logic level ―1‖ at the
same time, the actual output code would only correspond to the input with the highest designated
priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder
for short. The Priority Encoder solves the problems mentioned above by allocating a priority level
to each input. The priority encoders output corresponds to the currently active input which has the
highest priority. when an input with a higher priority is present, all other inputs with a lower priority
will be ignored. Priority encoders can be used to reduce the number of wires needed in a particular
circuits or application that have multiple inputs. Other applications especially for Priority Encoders
may include detecting interrupts in microprocessor applications.
Entity level diagram
Truth Table:
En D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 X X X X X X X X Z Z Z
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 1 X X 0 1 0
1 0 0 0 0 1 X X X 0 1 1
1 0 0 0 1 X X X X 1 0 0
1 0 0 1 X X X X X 1 0 1
1 0 1 X X X X X X 1 1 0
1 1 X X X X X X X 1 1 1
1 1 X X X X X X X Z Z Z
Verilog Code for 8:1 Multiplexer

®
module m81(out, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
input wire D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
output reg out;
always@(*)
begin
case(S0 & S1 & S2)
3'b000: out=D0;
3'b001: out=D1;
3'b010: out=D2;
3'b011: out=D3;
3'b100: out=D4;
3'b101: out=D5;
3'b110: out=D6;
3'b111: out=D7;
default: out=1'b0;
endcase
end
endmodule
//Testbench
module top;
wire out;
reg D0, D1, D2, D3, D4, D5, D6, D7, D8, S0, S1, S2;
m81
uut(.D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .S0(
S0), .S1(S1), .S2(S2), .out(out));
initial
begin
D0=1'b0; D1=1'b0; D2=1'b0; D3=1'b0; D4=1'b0; D5=1'b0; D6=1'b0; D7=1'b0;S0=1'b0;
S1=1'b0; S2=1'b0;
#500 $finish;
end
always #1 D0=~D0;
always #2 D1=~D1;
always #3 D2=~D2;
always #4 D3=~D3;
always #5 D4=~D4;
always #6 D5=~D5;
always #7 D6=~D6;
always #8 D7=~D7;
always #9 S0=~S0;
always #10 S1=~S1;
always #11 S2=~S2;
always@(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or S0 or S1 or S2)
$monitor("At time = %t, Output = %d", $time, out);
Endmodule
Verilog Code for 8:3 Encoder
module encoder (din, dout);

input [7:0] din;
output [2:0] dout;
reg [2:0] dout;

®
always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b00000010) dout=3'b001;
else if (din ==8'b00100000) dout=3'b101;
else dout=3'bX;
end
endmodule
module encodert_b;
reg [0:7] din;
wire [2:0] dout;
encoder uut (.din(din), .dout(dout));
initial begin
#10 din=8'b10000000;
#10 din=8'b01000000;
#10 din=8'b00100000;
#10 din=8'b00010000;
#10 din=8'b00001000;
#10 din=8'b00000100;
#10 din=8'b00000010;
#10 din=8'b00000001;
#10 $stop;
end
endmodule
Verilog Code for Priority encoder

module encoder_wp(D, Q, En);
input En;
input [7:0] D;
output [2:0] Q;
reg [ 2:0] Q;
always@ ( En,D)
begin if ( En ==1)
begin if ( D[7]== 1) Q = 3'b111;
else if ( D[6] == 1) Q = 3'b110;
else if ( D[5] == 1) Q = 3'b101;
else if ( D[4] == 1) Q = 3'b100;
else if ( D[3] == 1) Q = 3'b011;
else if ( D[2] == 1) Q = 3'b010;
else if ( D[1] == 1) Q = 3'b001;
else if ( D[0] == 1) Q = 3'b000;
else Q = 3'bzzz;
end
end
endmodule
module prio_enco_8x3_tst;

®
reg [7:0] D;
reg En;
wire[2:0] Q;
encoder_wp uut (.D(D),.Q(Q),.En(En));
initial
begin
En=1'b0;
#10 En=1'b1;
#10 D=8'b00000001;
#10 D=8'b00000010;
#10 D=8'b00000110;
#10 D=8'b00001010;
#10 D=8'b00010000;
#10 D=8'b00100010;
#10 D=8'b01000000;
#10 D=8'b10000110;
#10 D=8'b10001000;
#10 $stop;
end
endmodule
Expected Waveform for 8:1 Multiplexer
Expected Waveform for 8:3 encoder

®
Expected Waveform for Priority encoder
Result:Verilog code for 8:1 mux, 8:3 encoder, Priority encoder are realized.

®
Experiment 6
1:8Demux, 3:8 decoder, 2 bit comparator
Aim: Write a Verilog code for 1:8 Demux, 3:8 decoder, 2 bit comparator
Theory:
The 1:8 Demux consists of 1 data input bit, 3 control bits and 8 output bits. I 0, I1, I2, I3, I4, I5, I6,
I7 are the eight output bits, S0, S1 and S2 are the control bits and input D.
The applications include: Demultiplexers are used in clock data recovery solutions. Demultiplexer
along with multiplexer is necessary for any communication system for data transmission.
Demultiplexers are used in ATM packets broadcasting. The output of Arithmetic Logic Unit is
stored in respective registers using Demultiplexers.

®
Decoder- In this tutorial, you learn about the Decoder which is one of the most important topics
in digital electronics. In this article we will talk about the Decoder itself, we will have a look at
the 3 to 8 decoder, 3 to 8 line decoder designing steps, a technique to simplify the Boolean
function, and in the end, we will draw a logic diagram of the 3 to 8 decoder.
A digital decoder converts a set of digital signals into corresponding decimal code. A decoder is also
the most commonly used circuit prior to the use of an encoder. The encoded data is decoded for the
user interface in most of the output devices like monitors, calculator displays, printers, etc.
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than, or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A and
the other for B and have three output terminals, one for A > B condition, one for A = B condition,
and one for A < B condition.

®
Verilog Program for 1:8 Demux
module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule
module TestModule;
// Inputs
reg in;
reg s0;
reg s1;
reg s2;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

Demultiplexer uut (
.in(in),
.s0(s0),
.s1(s1),
.s2(s2),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;

®

#100;
in = 1;
s0 = 0;
s1 = 1;
s2 = 0;
#100;
end
endmodule
d1 = 0;
d2 = 0;
d3 = 0;
d4 = 1;
d5 = 1;
d6 = 0;
d7 = 1;
sel = 5;

#100;

end
endmodule
Verilog Program 8:3 decoder.
module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a&~b&~c),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule
module TestModule;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire d0;
wire d1;
wire d2;

®
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

Decoder uut (
.a(a),
.b(b),
.c(c),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
a = 0;
b = 0;
c = 0;
#100;
a = 1;
b = 0;
c = 1;
#100;
end
endmodule
Verilog Program 4bit comparator.
module comparator(
Data_in_A, //input A
Data_in_B, //input B
less, //high when A is less than B
equal, //high when A is equal to B
greater //high when A is greater than B
);
//what are the input ports.

input [3:0] Data_in_A;
input [3:0] Data_in_B;
//What are the output ports.
output less;
output equal;
output greater;

®
//Internal variables
reg less;
reg equal;
reg greater;
//When the inputs and A or B are changed execute this block

always @(Data_in_A or Data_in_B)
begin
if(Data_in_A > Data_in_B) begin //check if A is bigger than B.
less = 0;
equal = 0;
greater = 1; end
else if(Data_in_A == Data_in_B) begin //Check if A is equal to B
less = 0;
equal = 1;
greater = 0; end
else begin //Otherwise - check for A less than B.
less = 1;
equal = 0;
greater =0;
end
end
endmodule
Testbench for Comparator:
module tb_tm;
// Inputs
reg [3:0] Data_in_A;
reg [3:0] Data_in_B;
// Outputs
wire less;
wire equal;
wire greater;

comparator uut (
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.less(less),
.equal(equal),
.greater(greater)
);
initial begin
//Apply inputs
Data_in_A = 10;
Data_in_B = 12;
#100;
Data_in_A = 15;
Data_in_B = 11;

®
#100;
Data_in_A = 10;
Data_in_B = 10;
#100;
end
endmodule
Expected Waveform for 1:8 Demultiplier
Expected Waveform for 3:8 Decoder

®
Expected Waveform for 4 bit comparator

®
Experiment 7
SR flip flop , JK flip flop, D flip flop
Aim: Write a Verilog code for SR,JK,D flip flop and verify the functionality using FPGA board.
Theory:
A flip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many other
types of systems. Flip-flops and latches are used asdata storageelements. It is the basic storage
element in sequential logic. The basic building block that makes computer memories possible and
is also used in many sequential logic circuits is the flip-flop or bistable circuit. Just two inter-
connected logic gates make up the basic form of this circuit whose output has two stable output
states.
The SR flip-flop can be considered as a 1-bit memory since it stores the input pulse even after it
has passed. Flipflops (or bi-stables) of different types can be made from logic gates and, as with
other combinations of logic gates, the NAND and NOR gates are the most versatile, the NAND
being most widely used. This is because, as well as being universal, i.e. it can be made to mimic
any of the other standard logic functions, it is also cheaper to construct. Other, more widely used
types of flip-flop are the JK, the D type and T type. Applications of flipflops include Registers,
Counters, Event Detectors, Data Synchronizers, Frequency Dividers.
The SR (Set-Reset) flip-flop is one of the simplest sequential circuits. The output of each gate is
connected to one of the inputs of the other gate, giving a form of positive feedback or ‗cross-
coupling‘. This SR flip flop circuit has a
|
set input (S) and a reset input (R). In this circuit when ―S‖ is active the output ―Q‖ would be
high and ―Q ‖ will be low. The indeterminate or uncertain logic state only occurs if the inputs
change from 0,0 to 1,1 together. This should be avoided in normal operation but is likely to
happen when power is first applied. This could lead to uncertain results, but the flip-flop will work
normally once an input pulse is applied to either input. The SR Flip-flop is therefore, a simple 1-
bit memory.

®
Truth Table:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Invalid
Verilog Code :SR Flipflop
module srff_behave(s,r,clk, q, qbar);
input s,r,clk;
output reg q, qbar;
always@(posedge clk)
begin
if(s == 1)
begin
q = 1;
qbar = 0;
end
else if(r == 1)
begin
q = 0;

®
qbar =1;
end
else if(s == 0 & r == 0)
begin
q <= q;
qbar <= qbar
end
end
endmodule
//test bench for d flip flop

//1. Declare module and ports
module dff_test;
reg S,R, CLK;
wire Q, QBAR;
//2. Instantiate the module we want to test. We have instantiated the

srff_behavior
srff_behavior dut(.q(Q), .qbar(QBAR), .s(S), .r(R), .clk(CLK)); // instantiation

by port name.
//3. Monitor TB ports

$monitor("simtime = %g, CLK = %b, S = %b, R = %b, Q = %b, QBAR = %b", $time,
CLK, S, R, Q, QBAR);
//4. apply test vectors

initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
S= 1; R= 0;
#100; S= 0; R= 1;
#100; S= 0; R= 0;
#100; S= 1; R=1;
end
endmodule

®
Expected Waveform
Verilog Code for D Flip Flop
module DFF( Q,
Qbar,
D,
Clk,
Reset
);
output reg Q;
output Qbar;
input D,
Clk,
Reset;
assign Qbar = ~Q;
always @(posedge Clk)
begin
if (Reset == 1'b1) //If not at reset

®
Q = 1'b0;
else
Q = D;
end
endmodule
module DFF_tb;
// Inputs
reg D;
reg Clk;
reg Reset;
// Outputs
wire Q;
wire Qbar;
DFF uut (
.Q(Q),
.Qbar(Qbar),
.D(D),
.Clk(Clk),
.Reset(Reset)
);
initial begin
D = 1'b0;
Clk = 1'b0;
Reset = 1'b1;

®
#100;
Reset = 1'b0;
#20;
forever #40 D = ~ D;
end
always #10 Clk = ~Clk;
endmodule
Expected Waveform:
Verilog Code for JK Flip Flops
module jkff_behave(clk,j,knq,qbar);
input clk,j,k;
output reg q,qbar;

®
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
else if(j = 1)
begin
q <= 0;
qbar <= 0;
end
else if(j = 0 & k = 0)
begin
q <= q;
qbar <= qbar;
end
else if(j = 1 & k = 1)
begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule
//test bench for JK flip flop

//1. Declare module and ports
module jkff_test;
reg J,K, CLK;
wire Q, QBAR;
//2. Instantiate the module we want to test. We have instantiated the

jkff_behavior
jkff_behavior dut(.q(Q), .qbar(QBAR), .j(J), .k(K), .clk(CLK)); // instantiation
by port name.
//3. Monitor TB ports

$monitor("simtime = %g, CLK = %b, J = %b, K = %b, Q = %b, QBAR = %b", $time,
CLK, J, K, Q, QBAR);
//4. apply test vectors

initial begin

®
clk=0;
forever #10 clk = ~clk;
end
initial begin
J= 1; K= 0;
#100; J= 0; K= 1;
#100; J= 0; K= 0;
#100; J= 1; K=1;
end
endmodule
Expected Waveform:

®
Experiment 8
BCD synchronous counter,up/down binary counter
Aim: Write a Verilog code for 4-bit BCD synchronous counter, up/down binary counter and verify
the functionality using FPGA board.
Theory:
In digital electronics, counter is a sequential logic circuit consisting of a series of flip-flops which is
used to counts the number of occurrences of input in terms of negative or positive edge transitions.
Countersare of two types depending upon clock pulse applied. These counters are: Asynchronous
counter, and Synchronous counter. In Asynchronous Counter is also known asRippleCounter,
different flip flops are triggered with different clock, not simultaneously. While in Synchronous
Counter, all flip flops are triggered with same clock simultaneously and Synchronous Counter is
faster than asynchronous counter in operation. In synchronous counter, all flip flops are triggered
with same clock simultaneously. Synchronous Counter is faster than asynchronous counter in
operation. Synchronous Counter does not produce any decoding errors. Synchronous Counter is
also called Parallel Counter. Synchronous Counter designing as well implementation are complex
due to increasing the number of states. Synchronous Counter will operate in any desired count
sequence. Synchronous Counter examples are:Ringcounter,Johnsoncounter. In synchronous
counter, propagation delay is less.
Synchronous counters are used in Alarm Clock, Set AC Timer, Set time in camera to take the
picture, flashing light indicator in automobiles, car parking control etc. Counting the time allotted
for special process or event by the scheduler. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop.
Synchronous Counter:

®
Truth Table of Synchronous Counter
clk(rising edge) rst q[4:0]

1 0 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 0000
Truth Table of Binary up/down Counter
BCD synchronous counter
Verilog Code:[ Simulation]
modulebcd_counter(clk,rst,q);
inputrst; input clk;
output [3:0]q;

®
reg[3:0]q=4'b0000;
always@(posedgeclk)
begin if(rst==1 ||
q==4'b1001)
q=4'b0000; else
q=q+1; end
endmodule
Verilog code for testbench:
moduletest_bcd_counter;
// Inputs
regclk; regrst;
// Outputs
wire [3:0] q;

bcd_counteruut (
.clk(clk),
.rst(rst),
.q(q)
);
initial begin
clk = 0;
rst = 1;
#5 rst=0;
#150 rst=1;
#10 rst=0; #200
$finish;
end
always #5 clk=~clk;
endmodule
Verilog Code:

®
modulebcd_counter_synt(clk,rst,q);
inputrst,clk; output [3:0]q;
reg [3:0]q=4'b0000; reg
[31:0] clkdiv=25'd0;
always@(posedgeclk)
clkdiv=clkdiv+1;
always@(posedgeclkdiv[24])
begin
if(rst==1 || q==4'b1001)
q=4'b0000; else
q=q+1; end endmodule
# PlanAhead Generated physical constraints

NET "clk" LOC = P56;
NET "q[0]" LOC = P98;
NET "q[1]" LOC = P99;
NET "q[2]" LOC = P100;
NET "q[3]" LOC = P101;
NET "rst" LOC = P121;
Verilog code for up-down counter

moduleup_down_counter(inputclk, reset,up_down, output[3:0] counter
);
reg [3:0] counter_up_down;
// down counter
always @(posedgeclkorposedge reset)
begin
if(reset)
counter_up_down<=4'h0;
elseif(~up_down)
counter_up_down<=counter_up_down+4'd1;
else
counter_up_down<=counter_up_down-4'd1;
end
assign counter =counter_up_down;
endmodule
Testbench Verilog code for up-down counter

moduleupdowncounter_testbench();
regclk, reset,up_down;
wire [3:0] counter;
up_down_counterdut(clk, reset,up_down, counter);
initialbegin
clk=0;
forever #5clk=~clk;
end
initialbegin

®
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule
Expected Waveform:
BCD Counter:
Binary Counter
Verilog code for 4-bit BCD synchronous counter, up/down binary counterare verified using
Result:
FPGA board.

®
PART-B
Interfacing and Debugging

®
Experiment 9
Verilog Program to interface a Stepper motor to the FPGA and rotate the motor
in the specified direction (by N steps).
Aim:Interface a Stepper motor to FPGA and write Verilog code to control the Stepper motor
rotation
Theory:
A stepper motor is a special type of electric motor that moves in increments, or steps, rather than
turning smoothly as a conventional motor does. Typical increments are 0.9 or 1.8 degrees, with 400
or 200 increments thus representing a full circle. The speed of the motor is determined by the time
delay between each incremental movement.
U8 is a Driver Buffer (ULN2003) device connected to LPC-1768 Device and can be used for
driving Stepper Motor. On the LPC-1768, P1.22 to P1.25 is used to generate the pulse sequence
required to run the stepper Motor. Also, the Stepper Motor is powered by its own power supply pin
(COM), which is connected to a 12V supply. Table shows connections for stepper Motor.
Construction & Working Principle
The construction of a stepper motor is fairly related to a DC motor. It includes a permanent magnet
like Rotor which is in the middle & it will turn once force acts on it. This rotor is enclosed through a
no. of the stator which is wound through a magnetic coil all over it. The stator is arranged near to
rotor so that magnetic fields within the stators can control the movement of the rotor.
The stepper motor can be controlled by energizing every stator one by one. So the stator will
magnetize & works like an electromagnetic pole which uses repulsive energy on the rotor to move
forward. The stator’s alternative magnetizing as well as demagnetizing will shift the rotor
gradually &allows it to turn through great control. The stepper motor working principle is
Electro-Magnetism. It includes a rotor which is made with a permanent magnet whereas a stator is
with electromagnets. Once the supply is provided to the winding of the stator then the magnetic
field will be developed within the stator. Now rotor in the motor will start to move with the
rotating magnetic field of the stator. So this is the fundamental working principle of this motor
The applications of stepper motor include the following.

1. Industrial Machines – Stepper motors are used in automotive gauges and machine tooling
automated production equipment.
2. Security – new surveillance products for the security industry.
3. Medical – Stepper motors are used inside medical scanners, samplers, and also found inside
digital dental photography, fluid pumps, respirators, and blood analysis machinery.

®
4. Consumer Electronics – Stepper motors in cameras for automatic digital camera focus and zoom
functions.
And also have business machines applications, computer peripherals applications
Block Diagram:
Verilog Program:
module step_motor(input clk, output reg[3:0]stp, input dipsw1, input dipsw2, input
dipsw3); reg[20:0]count=21'd0; reg[3:0]stpval=4'b0001; always@(posedgeclk)
begin
count=count+1;
if(count==21'd20000000)
begin stp=stpval;
if(dipsw1==1)
begin
stpval=stpval>>1;
if(stpval==4'b0000)stpval=4'b1000;
end
else if(dipsw2==1)
begin
stpval=stpval>>1;
end
else if(dipsw3==1)
begin count=0;
stpval=stpval<<1;
end
endend
endmodule
UCF

®

NET "stp[0]" LOC = P29;
NET " dipsw1" LOC = P121;
Result:Verilog code to control the Stepper motor rotation is written and verified.

®
Experiment 10
Verilog Program to interface aADC to FPGA
Aim:Write Verilog code to convert an analog input of a sensor to digital form and to display the
same on a suitable display like set of simple LEDs.
Theory:
Transducers are also used to convert the input analog variables in the form of currents or voltages.
Basically, the digital numbers used here are binary i,e ‘0’ and ‘1’. The ‘0’ indicates the ‘off’ state
and ‘1’ represents the ‘on’ state. Hence all the analog values are converted into digital binary values
by an ADC. For example, if we have to install an alarm in our house or at some facility, whose
function is to set off in case of fire or overheating. Our whole alarm system will be electronic but
the temperature sensor will give analog values at the output after sensing the temperature. Therefore
to convert the varying values of temperature in digital or discrete values, we have to use an analog
to digital converter.
Block Diagram:
Clk Write_en
Logic Int_pin Analog to
Circuit Digital
Converter
(8-bit) Digital-
8
bit
LED Display Sensor Input
Verilog Code:
moduleadc( input clk, input [7:0] digital_data, input int_pin,

output regwrite_en, output reg [7:0] led_display); reg
[4:0]count=0; reg await=0; always@(posedgeclk)
begin
if(count==0)
begin
write_en=0;

®
await=1; end
if(count==5)
begin
write_en=1;
await=0; end
if(await==0)
begin
if(int_pin==0)
begin
led_display=di
gital_data;
await=1;
endend
if(await==1)co
unt=count+1;
if(count==10)c
ount=0;
endendmodul
e
UCF

NET "digital_data[0]" LOC = P12;
NET "int_pin" LOC = P26;
NET "led_display[0]" LOC = P120;
NET "write_en" LOC = P24;
Result:Verilog code is written to convert an analog input of a sensor to digital form and to displayed
the same on a suitable display.

®
Experiment 11
Verilog Program to interface a DAC to FPGA
Aim: To Interface a DAC to FPGA and write Verilog code to generate Sine wave of frequency F KHz
(eg.20 KHz) frequency.
Block Diagram:
Digital-to-analog converter (DAC) provides a voltage reference to on-chip modules or an output to a

package pin. It can also be used as a waveform generator to generate square, triangle, and sawtooth
waveforms through automatic mode. The DAC can be put in power-down mode if needed. The
maximum settling time will not exceed two microseconds with a maximum output load (3 kΩ || 400
pf) when the output swings from minimum output to maximum output or vice-versa. The DAC
provides the ability to select either high-speed or low-speed mode and also supports two digital
formats. It has a glitch filter to suppress output glitches during data conversion. The DAC supports two
conversion modes, asynchronous and synchronous. In asynchronous conversion mode, data can be
immediately presented to the DAC and converted to an analog output when written to the DAC
buffered data register. In synchronous conversion mode, data in the DAC buffered data register is
controlled by the SYNC_IN signal when the buffered data is presented to the input of the DAC. The DAC
supports two operation
modes: Normal and Automatic mode. In Normal mode, it generates an analog representation
of digital words. In Automatic mode, it generates sawtooth, triangle, and square waveforms
without CPU intervention, with programmable period, update rate, and range.
Verilog Code:
modulesinewave(input clk, output reg[7:0]dac1,output regwr);

reg[7:0] sine[0:255]; integer i=0; reg[4:0]count=0;
reg[31:0]clkdiv=32'd0;
initial
begin
$readmemh("DAC_SINE.lst",sine); end
always@(posedgeclk) clkdiv=clkdiv+1;
always@(posedgeclk)//clk for f=20KHz; clkdiv[0] for f=10KHz
begin
if(count==0)
begin
dac1=sine[i]; i=i+1; if(i==255)

®
i=0; end
if(count==1)wr=1;
if(count==4)wr=0; count=count+1;
if(count==10)count=0;
end
endmodule
UCF

NET "dac1[0]" LOC = P66;
NET "wr" LOC = P81;
Expected Waveform
Result: Interfacinga DAC to FPGA using Verilog code is verified.

®
Experiment 12
Verilog Program to interface Switches and LEDsto FPGA
Aim: Write a Verilog programs to interface Switches and LEDs to the FPGA/CPLD and
demonstrate its working.
Block Diagram:
A digital circuit contains a power supply, devices, and conduction nets. Some nets provide the
circuit with inputs from the “outside world,” while others, conversely, provide information from the
circuit to the outside world. The nets that provide an interface between the circuit and the outside
world are called ports.
Circuits need input devices to generate input signals. Input devices can take many forms, among
them keyboards (such as on a PC), buttons, and switches. Circuits also need output devices to
communicate their state to the user. In this project, a switch is used as the input device and an LED
is used as the output device. The digital circuit we will build is called the “led_sw,” as shown in
Fig. 1 below. The circuit created in this project will be implemented inside the FPGA board. The
board has an input port called “sw,” which receives an input signal from the external switch in the
circuit and an output port called “led,” which drives the external LED in the circuit. The “led_sw” is
a simple circuit that bypasses the signal on the input port and directly sends information to the
output port. You can view this as a direct wired connection between the net “sw” and the net “led.”
The circuit will be implemented using Verilog HDL. On different FPGA boards, switches and
LEDs are connected to different pins on an FPGA chip. Thus, a user constraint file (XDC) is needed
to map the input and output net of the circuit to the physical pin location on the FPGA chip. Take
Nexys3 as an example, the Slide Switch 0 (SW0) is connected to FPGA pin T10, and FPGA pin
U16 drives LED 0 (LD0). When you slide the switch to the ON position, a high voltage will be
placed on FPGA pin T10, which is mapped to the input port of the circuit “led_sw.” The digital
circuit then transmits the signal onto the output port LED, which is connected to FPGA pin U16.
The high voltage on the output port “led” will cause a voltage drop between node A and node B.
This voltage drop will drive current through the LED, which will light the LED and inform the user
that the switch is on.
Verilog Code:
module example (
inputclk,
inputrst,
input push,

®
outputregled_on
);
reg on;
reg off;
regt_on_off;
regt_off_on;
always @* begin
t_on_off = on & (push);
end
always @* begin
t_off_on = off & (push);
end
always @(posedgeclk or posedgerst) begin

if (rst) on <= 1'b0;
else if (t_off_on) on <= 1'b1;
else if (t_on_off) on <= 1'b0;
end
always @(posedgeclk or posedgerst) begin

if (rst) off <= 1'b1;
else if (t_off_on) off <= 1'b0;
else if (t_on_off) off <= 1'b1;
end
always @* begin
led_on = on;
end
endmodule
Result: Verilog programs to interface Switches and LEDs using the FPGA is verified.

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RV Institute of Technology & Management

Department of Electronics and Communication Engineering

Course Name: DIGITAL SYSTEM DESIGN USING VERILOG LABORATORY

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM1

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 2

FPGA Development Board

VFPGA6-2.0 board consists of the following.

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 3

Block Diagram of VFPGA6-2.0Microcontrollerkit

Buzzer 5V, 3.3V and 1.2V supply

Toggle Switch SPARTAN6 LCD Display

Fig. 1Block Diagram of VFPGA6

Starting the ISE14.7 Software

Project Navigator Desktop Icon Creating a New Project

Fig. 2 Project Navigator

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 4

The New Project Wizard appears.

Fig. 3 New Project Wizard

The New Project Wizard—Device Properties page appears.

Fig. 4 Project Settings

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 5

Click Next, then Finish to complete the project creation.

Creating an HDL-Based Module

Fig.5New Source Wizard

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 6

2. In the Select Source Type page, select VHDL Module.

Fig6New Source Wizard—Select Source Type Page

Fig. 7 New Source Wizard—Define Module Page

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 7

6. Click Next to view a description of the module.

Fig.8 New Source Wizard—Summary Page

Fig.9VHDL File in ISE Text Editor

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 8

Fig.11I/O pin Planning (Plan Ahead)-page

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 9

Fig.12I/O pin Planning (Plan Ahead)-page

11. Now Plan Ahead 14.7 window will open.

Fig.13I/O pin Planning (Plan Ahead)-page

12. Now select and expand required I/O bank

Fig.14I/O Bank Selection

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 10

Fig.15I/O pin selection

Fig.16Generate Programming file -page

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 11

Software Tools: Xilinx ISE Design Suite 13.1

Boolean expression approach: f m(1,3,4,5,10,12,13)

Boolean Function: F = ~(AB+CD)

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 12

assign F = ~((A & B) | (C & D));

Test Bench code

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 13

Result: The given Boolean expressions is realized using Verilog program

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 14

Software Tools: Xilinx ISE Design Suite 13.1

Hardware: Spartan 6 FPGA Development Board

Half Adder (HA):

Full Adder (FA):

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 15

Entity level diagram:

A B Cin SUM Cout

III-Semester, Lab Manual (21EC32), ECE Dept., RVITM 16

Half Adder (Using dataflow, BehavioralModeling):

module ha(a, b, sum, carry);