EEE303-Week02 - Boolean Algebra

Weekly Lecture Plan
Week Topic Textbook

Harris 1.4, 5.3,
1 Introduction to Number Systems and codes, Introduction to VerilogHDL
1.5
Introduction to Boolean algebra, Analysis and synthesis of digital logic
2-3 circuits: Basic logic function, combinational logic design, Universal logic Harris 2.1-2.9
gates, Minimization of combinational logic, k-map
Programming and structural and behavioral design of digital systems
4 using VerilogHDL, Verilog Timing analysis and test bench. Verilog Harris 4
synthesis with combinational logic
Harris 5.2-
5 ALU design (Adder, Subtractor, Comparator)
Floyd 6.1-6.3
Winter Vacation
6 Decoder, encoder, Multiplexer, demultiplexer Floyd 6.4-6.9
EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 1
Department of EEE, BUET
Class Test Announcement
• 21st December 2022 (Wednesday)
• Respective classrooms.
• A1, B1 and C1 will come in sharp 8am in their respective classes.
• A2, B2 and C2 will come at sharp 8:20am, and wait for the invigilator’s
instruction to enter the classroom
• Class Test Syllabus: 1st 4 weeks

EEE 303 – Digital Electronics
Boolean Algebra
Week 02
Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
Boolean Logic:
Introductions, Basic Gates
Lecture 02.1

Introduction to Logic: State and Output
• If a given switch is controlled

by an input variable x, then
we will say that the switch is
open if x = 0 and closed if x =
1. Such switches are
implemented with transistors.

Variable and States
• The output is defined as

the state (or condition) of
the light L. If the light is
on, we will say that L = 1.
If the light is off, we will
say that L = 0.
• Since L = 1 if x = 1 and L
= 0 if x = 0, we can say
that L(x) = x.
We say that L(x) = x is a
logic function and that x is
an input variable.
Logical AND Operation
Operation: A.B
Symbol

AND operation

Application of AND logic

Logical OR Operation
Operation: A+B
Symbol

OR operation

Application of OR logic

Logical NOT Operation
Operation:
Symbol

Application of NOT logic

NAND Operation
NOR Operation

Example of NAND

Example of NOR

XOR
Exclusive OR
XNOR

Application of XOR gate

Implementing Boolean Logic
• Integrated Circuits
• Programmable Logic

Implementation of Boolean Logic: Integrated Circuits
Standard Integrated circuits are available for

Use that has logic IC built in.
14 Pin Dual-Inline-Package (DIP) IC are

suitable to be plugged into a breadboard
Most commonly starts with 74 IC number

AND ICs
Available AND Gate ICs

NAND ICs
Available NAND Gate ICs

OR, NOR ICs

Logic IC family
Most common in lab

A 74HC IC will regard 2-6 V as logic 1, where as 74LS IC will recognize only above 4.5V as 1
So care should be taken while mixing them Source: Wikipedia
Implementation of Boolean Logic: Programmable Logic
• Programmable Logic Devices has internally gate arrays that can be connected
through programming.
• Useful for prototyping

Implementation of Boolean Logic: Programmable Logic
Programmable logic devices can be programmed to perform specified logic functions and
operations by the manufacturer or by the user. Many types of programmable logic are available,
ranging from small devices that can replace a few fixed-function devices to complex high-density
devices that can replace thousands of fixed-function devices. Two major categories of user-
programmable logic are
PLD (programmable logic device) and FPGA (field-programmable gate array)

SPLD (Simple Programmable Logic Device)
The SPLD was the original PLD and is still available for small-scale applications. Generally, an SPLD
can replace up to ten fixed-function ICs and their interconnections, depending on the type of functions
and the specific SPLD. Most SPLDs are in one of two categories: PAL and GAL.
A PAL (programmable array logic) is a device that can be programmed one time. It consists of a
programmable array of AND gates and a fixed array of OR gates, as shown in Figure 1–30(a).
A GAL (generic array logic) is a device that is basically a PAL that can be reprogrammed many times. It
consists of a reprogrammable array of AND gates and a fixed array of OR gates with programmable
ouputs,

Programmable AND Array
Most types of PLDs use some form of AND array. Basically, this array consists of AND gates and a matrix
of interconnections with a programmable link at each cross point.
Programmable links allow a connection between a row line and a column line in the interconnection matrix to
be opened or left intact. For each input to an AND gate, only one programmable link is left intact in order to
connect the desired variable to the gate input.

CPLD (Complex Programmable Logic Device)
CPLD is a device containing multiple SPLDs and can replace many fixed-function ICs. Figure 1–32 shows
a basic CPLD block diagram with four logic array blocks (LABs) and a programmable interconnection array
(PIA). Depending on the specific CPLD, there can be from two to sixty-four LABs. Each logic array block
is roughly equivalent to one SPLD

The Programming Process
An SPLD, CPLD, or FPGA can be thought of as a “blank slate” on which you implement a specified circuit or
system design using a certain process. This process requires a software development package installed on a
computer to implement a circuit design in the programmable chip.

FPGA (Field Programmable Gate Array)
An FPGA is generally more complex and has a much higher density than a CPLD.
The FPGA has a different internal structure (architecture). The three basic elements in an FPGA are the
logic block, the programmable interconnections, and the input/output (I/O) blocks. The distributed
programmable interconnection matrix provides for interconnection of the logic blocks and connection to
inputs and outputs

Programming Gate Array

Fuse vs Antifuse

EPROM

SRAM

Boolean Algebra:
Axioms
Lecture 02.2
Boolean Algebra
Found application in engineering
after almost 100 years
Introduced by George Boole In
1849
Axioms
Based on a set of rules derived
from a small number of basic
assumptions- Axioms
Think of Euclidean Geometry

Boolean Operators
• Addition
• Multiplication

Venn Diagram to Understand Logic

Introduction
A logic circuit is composed of:
• Inputs
• Outputs
• Functional specification
• Timing specification
functional spec
inputs outputs
timing spec

Circuits
• Nodes
• Inputs: A, B, C
• Outputs: Y, Z n1
A E1
• Internal: n1
B E3 Y
• Circuit elements C E2 Z
• E1,E2, E3
• Each a circuit

Types of Logic Circuits
• Combinational Logic
• Memoryless
• Outputs determined by current values of inputs
• Sequential Logic
• Has memory
• Outputs determined by previous and current values
of inputs
functional spec
inputs outputs
timing spec

Rules of Combinational Composition
• Every element is combinational
• Every node is either an input or connects
to exactly one output
• The circuit contains no cyclic paths
• Example:

Boolean Equations
• Functional specification of outputs in
terms of inputs
• Example: S = F(A, B, Cin)
Cout = F(A, B, Cin)
A
CL S
B
Cout
Cin
S = A  B  Cin
Cout = AB + ACin + BCin

Some Definitions
• Complement: variable with a bar over it
A, B, C
• Literal: variable or its complement
A, A, B, B, C, C
• Implicant: product of literals
ABC, AC, BC
• Minterm: product that includes all input variables
ABC, ABC, ABC
• Maxterm: sum that includes all input variables
(A+B+C), (A+B+C), (A+B+C)

Sum-of-Products (SOP) Form
• All Boolean equations can be written in SOP form
• Each row has a minterm
• A minterm is a product (AND) of literals
• Each minterm is TRUE for that row (and only that row)
• Form function by ORing minterms where output is 1
• Thus, a sum (OR) of products (AND terms)
0
1
0
1
Y = F(A, B) = AB + AB = Σ(1, 3)
Product-of-Sums (POS) Form
• All Boolean equations can be written in POS form
• Each row has a maxterm
• A maxterm is a sum (OR) of literals
• Each maxterm is FALSE for that row (and only that row)
• Form function by ANDing maxterms where output is 0
• Thus, a product (AND) of sums (OR terms)
0
1
0
1
Y = F(A, B) = (A + B)●(A + B) = Π(0, 2)
Boolean Equations Example
• You are going to the cafeteria for lunch
– You won’t eat lunch (E=0)
– If it’s not open (O=0) or
– If they only serve corndogs (C=1)
• Write a truth table for determining if you
will eat lunch (E). O C E
0 0 0
0 1 0
1 0 1
1 1 0

SOP & POS Form
SOP – sum-of-products
O C E minterm
0 0 O C
0 1 O C E = OC
1 0 O C = Σ(2)
1 1 O C
POS – product-of-sums
O C E maxterm
0 0 O + C
0 1 O + C E = (O + C)(O + C)(O + C)
1 0 O + C = Π(0, 1, 3)
1 1 O + C

Boolean Algebra
• Axioms and theorems to simplify Boolean equations
• Like regular algebra, but simpler: variables have only
two values (1 or 0)
• Duality in axioms and theorems:
• ANDs and ORs, 0’s and 1’s interchanged

Boolean Axioms
Number Axiom Name

A1 B = 0 if B ≠ 1 Binary Field
A2 0=1 NOT
A3 0•0=0 AND/OR
A4 1•1=1 AND/OR
A5 0•1=1•0=0 AND/OR
Dual: Replace: • with +

0 with 1

Boolean Axioms
Number Axiom Dual Name

A1 B = 0 if B ≠ 1 B = 1 if B ≠ 0 Binary Field
A2 0=1 1=0 NOT
A3 0•0=0 1+1=1 AND/OR
A4 1•1=1 0+0=0 AND/OR
A5 0•1=1•0=0 1+0=0+1=1 AND/OR

0 with 1

Boolean Theorems of One
Variable
Number Theorem Name
T1 B•1=B Identity
T2 B•0=0 Null Element
T3 B•B=B Idempotency
T4 B=B Involution
T5 B•B=0 Complements

0 with 1

Boolean Theorems of One
Variable
Number Theorem Dual Name
T1 B•1=B B+0=B Identity
T2 B•0=0 B+1=1 Null Element
T3 B•B=B B+B=B Idempotency
T4 B=B Involution
T5 B•B=0 B+B=1 Complements

0 with 1
T1: Identity Theorem
• B 1=B
• B+0=B
B
1 = B
B
0 = B

T2: Null Element Theorem
• B 0=0
• B+1=1
B
0 = 0
B
1 = 1

T3: Idempotency Theorem
• B B=B
• B+B=B
B
B = B
B
B = B

T4: Identity Theorem
• B=B
B = B

T5: Complement Theorem
• B B=0
• B+B=1
B
B = 0
B
B = 1

Boolean Theorems of Several Vars
Number Theorem Name

T6 B•C = C•B Commutativity
T7 (B•C) • D = B • (C • D) Associativity
T8 B • (C + D) = (B•C) + (B•D) Distributivity
T9 B• (B+C) = B Covering
T10 (B•C) + (B•C) = B Combining
T11 (B•C) + (B•D) + (C•D) = Consensus
(B•C) + (B•D)
How do we prove these are true?

How to Prove
• Method 1: Perfect induction
• Method 2: Use other theorems and axioms
to simplify the equation
– Make one side of the equation look like
the other

Proof by Perfect Induction
• Also called: proof by exhaustion
• Check every possible input value
• If the two expressions produce the same
value for every possible input
combination, the expressions are equal

Example: Proof by Perfect
Induction
Numbe Theorem Name
r
T6 B•C = C•B Commutativity
B C BC CB
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

# Theorem Dual Name
T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C) (B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) = (B+C) • (B+D) • (C+D) = Consensus
(B•C) + (B•D) (B+C) • (B+D)

0 with 1

# Theorem Dual Name
T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C) (B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) = (B+C) • (B+D) • (C+D) = Consensus
(B•C) + (B•D) (B+C) • (B+D)
Warning: T8’ differs from traditional algebra:

OR (+) distributes over AND (•)
Simplifying an Equation
Reducing an equation to the fewest number
of implicants, where each implicant has the
fewest literals
Recall:
– Implicant: product of literals
ABC, AC, BC
– Literal: variable or its complement
A, A, B, B, C, C
Simplifying the equation is also called minimizing the equation

Simplification methods
• Distributivity (T8, T8’) B (C+D) = BC + BD
B + CD = (B+ C)(B+D)
• Covering (T9’) A + AP = A
• Combining (T10) PA + PA = P
• Expansion P = PA + PA
A = A + AP
• Duplication A=A+A
• “Simplification” theorem PA + A = P + A
PA + A = P + A

Proving the “Simplification”
Theorem
“Simplification” theorem
PA + A = P + A
Method 1:

Proving the “Simplification” Theorem
“Simplification” theorem
PA + A = P + A

Simplifying Boolean Equations
Example 1:
Y = AB + AB

Example 1:
Y = AB + AB
Y=A T10: Combining
or
= A(B + B) T8: Distributivity
= A(1) T5’: Complements
=A T1: Identity

Example 2:
Y = A(AB + ABC)
= A(AB(1 + C)) T8: Distributivity
= A(AB(1)) T2’: Null Element
= A(AB) T1: Identity
= (AA)B T7: Associativity
= AB T3: Idempotency

Example 3:
Y = A’BC + A’ Recall: A’ = A
Note:
• A‘ is shorthand for A.
• But use the tick symbol (‘) only when typing.
• It’s easy to lose ticks (‘) when writing by hand!
• It is strongly recommended that you simplify
equations by writing by hand.

Example 3:
Y = A’BC + A’ Recall: A’ = A
= A’ T9’ Covering: X + XY = X
or
= A’(BC + 1) T8: Distributivity
= A’(1) T2’: Null Element
= A’ T1: Identity

Example 4:
Y = AB’C + ABC + A’BC
= AB’C + ABC + ABC + A’BC T3’: Idempotency
= (AB’C+ABC) + (ABC+A’BC) T7’: Associativity
= AC + BC T10: Combining

Example 5:
Y = AB + BC +B’D’ + AC’D’
Method 1:
Y = AB + BC + B’D’ + (ABC’D’ + AB’C’D’) T10: Combining
= (AB + ABC’D’) + BC + (B’D’ + AB’C’D’) T6:
Commutativity
T7: Associativity
= AB + BC + B’D’ T9: Covering
Method 2:
Y = AB + BC + B’D’ + AC’D’ + AD’ T11:
Consensus
= AB + BC + B’D’ + AD’ T9: Covering
= AB + BC + B’D’ T11: Consensus
Example 6:
Y = (A + BC)(A + DE)
Apply T8’ first when possible: W+XZ = (W+X)(W+Z)
Make: X = BC, Z = DE and rewrite equation
Y = (A+X)(A+Z) substitution (X=BC, Z=DE)
= A + XZ T8’: Distributivity
= A + BCDE substitution
or This is called
Y = AA + ADE + ABC + BCDE T8: Distributivity multiplying out
an expression to get
= A + ADE + ABC + BCDE T3: Idempotency sum-of-products
= A + ADE + ABC + BCDE (SOP) form.
=A + ABC + BCDE T9’: Covering
= A + BCDE T9’: Covering
Review: Canonical SOP & POS Forms
• SOP – sum-of-products
O C E minterm
0 0 0 O C
0 1 0 O C E = OC
1 0 1 O C = Σ(2)
1 1 0 O C
• POS – product-of-sums
O C E maxterm
0 0 0 O + C E = (O + C)(O + C)(O + C)
0 1 0 O + C
1 0 1 O + C = Π(0, 1, 3)
1 1 0 O + C

Multiplying Out: SOP Form
An expression is in sum-of-products (SOP)
form when all products contain literals
only.
• SOP form: Y = AB + BC’ + DE
• NOT SOP form: Y = DF + E(A’+B)
• SOP form: Z = A + BC + DE’F

Multiplying Out: SOP Form
Example:
Y = (A + C + D + E)(A + B)
Make: X = (C+D+E), Z = B and rewrite equation
Y = (A+X)(A+Z) substitution (X=(C+D+E), Z=B)
= A + XZ T8’: Distributivity
= A + (C+D+E)B substitution
= A + BC + BD + BE T8: Distributivity
or
Y = AA+AB+AC+BC+AD+BD+AE+BE T8: Distributivity
= A+AB+AC+AD+AE+BC+BD+BE T3: Idempotency
= A + BC + BD + BE T9’: Covering

Factoring: POS Form
An expression is in product-of-sums (POS)
form when all sums contain literals only.
• POS form: Y = (A+B)(C+D)(E’+F)
• NOT POS form: Y = (D+E)(F’+GH)
• POS form: Z = A(B+C)(D+E’)

Factoring: POS Form
Example 1:
Y = (A + B’CDE)
Make: X = B’C, Z = DE and rewrite equation
Y = (A+XZ) substitution (X=B’C,
Z=DE)
= (A+B’C)(A+DE) T8’: Distributivity
= (A+B’)(A+C)(A+D)(A+E) T8’: Distributivity

Factoring: POS Form
Example 2:
Y = AB + C’DE + F
Make: W = AB, X = C’, Z = DE and rewrite equation
Y = (W+XZ) + F substitution W = AB, X = C’, Z = DE
= (W+X)(W+Z) + F T8’: Distributivity
= (AB+C’)(AB+DE)+F substitution
= (A+C’)(B+C’)(AB+D)(AB+E)+FT8’: Distributivity
= (A+C’)(B+C’)(A+D)(B+D)(A+E)(B+E)+F T8’: Distributivity
= (A+C’+F)(B+C’+F)(A+D+F)(B+D+F)(A+E+F)(B+E+F) T8’: Distributivity

Boolean Algebra:
De Morgan’s Theorem
Lecture 02.3
•The complement of the union of two sets is the same as the
intersection of their complements
•The complement of the intersection of two sets is the same as the
union of their complements
27 June 1806 – 18 March 1871

Number Theorem Name

T12 B0•B1•B2… = B0+B1+B2… DeMorgan’s
Theorem
The complement of the product

is the
sum of the complements

DeMorgan’s Theorem: Dual
# Theorem Dual Name

T12 B0•B1•B2… = B0+B1+B2… = DeMorgan’s
B0+B1+B2… B0•B1•B2… Theorem
The complement of the product

is the
sum of the complements.
Dual: The complement of the sum

is the
product of the complements.
DeMorgan’s Theorem
• Y = AB = A + B A
B
Y
A
Y
B
• Y=A+B=A B A
B
Y
A
Y
B

DeMorgan’s Theorem Example 1
Y = (A+BD)C
= (A+BD) + C
= (A•(BD)) + C
= (A•(BD)) + C
= ABD + C

DeMorgan’s Theorem Example
2
Y = (ACE+D) + B

DeMorgan’s Theorem
A
• Y = AB = A + B B
Y
A
Y
B
A
• Y=A+B=A B B
Y
A
Y
B

Bubble Pushing
• Backward:
• Body changes
• Adds bubbles to inputs
A A
Y Y
B B
• Forward:
• Body changes
• Adds bubble to output
A A
Y Y
B B

Bubble Pushing
• What is the Boolean expression for this
circuit?
A
B
Y
C
D
Y = AB + CD

Bubble Pushing Rules
• Begin at output, then work toward inputs
• Push bubbles on final output back
• Draw gates in a form so bubbles cancel
A
B
C Y
D

Bubble Pushing Example
A
B
C Y
D

no output
A bubble
B
C Y
D

no output
A bubble
B
C Y
D
bubble on
A input and output
B
C Y
D

no output
A bubble
B
C Y
D
bubble on
A input and output
B
C Y
D
no bubble on
input and output
A
B
C Y
D
Y = ABC + D

From Logic to Gates
• Two-level logic: ANDs followed by ORs
• Example: Y = ABC + ABC + ABC
A B C
A B C
minterm: ABC
minterm: ABC
minterm: ABC

Circuit Schematics Rules
• Inputs on the left (or top)
• Outputs on right (or bottom)
• Gates flow from left to right
• Straight wires are best

Circuit Schematic Rules (cont.)
• Wires always connect at a T junction
• A dot where wires cross indicates a
connection between the wires
• Wires crossing without a dot make no
connection wires crossing
wires connect wires connect without a dot do
at a T junction at a dot not connect

Multiple-Output Circuits
• Example: Priority Circuit
A3 A2 A1 A0 Y3 Y2 Y1 Y0
Output asserted 0 0 0 0
corresponding to most 0
0
0
0
0
1
1
0
significant TRUE input 0
0
0
1
1
0
1
0
0 1 0 1
A3 Y3 0 1 1 0
0 1 1 1
A2 Y2 1 0 0 0
1 0 0 1
A1 Y1 1 0 1 0
1 0 1 1
A0 Y0 1 1 0 0
PRIORITY 1 1 0 1
1 1 1 0
CiIRCUIT
1 1 1 1

Multiple-Output Circuits
• Example: Priority Circuit
Output asserted A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
corresponding to most 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
significant TRUE input 0 0 1 1 0 0 1 0
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 0
A3 Y3 0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0
A2 Y2 1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0
A1 Y1 1 0 1 0 1 0 0 0
1 0 1 1 1 0 0 0
A0 Y0 1 1 0 0 1 0 0 0
PRIORITY 1 1 0 1 1 0 0 0
CiIRCUIT 1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

Priority Circuit Hardware
A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 A3 A2 A1 A0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
Y3
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 0 Y2
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
Y1
1 0 1 0 1 0 0 0
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 0 Y0
1 1 0 1 1 0 0 0
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

Don’t Cares
A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 0 0 A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 0 0 0
0 0 1 X 0 0 1 0
1 0 0 1 1 0 0 0 0 1 X X 0 1 0 0
1 0 1 0 1 0 0 0 1 X X X 1 0 0 0
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 0
1 1 1 0 1 0 0 0
1 1 1 1 1 0 0 0

Contention: X
• Contention: circuit tries to drive output to 1 and 0
• Actual value somewhere in between
• Could be 0, 1, or in forbidden zone
• Might change with voltage, temperature, time, noise
• Often causes excessive power dissipation
A=1
Y=X
• Warnings: B=0
• Contention usually indicates a bug.
• X is used for “don’t care” and contention - look at the
context to tell them apart.

Floating: Z
• Floating, high impedance, open, high Z
• Floating output might be 0, 1, or
somewhere in between
• A voltmeter won’t indicate whether a node is
floating
Tristate Buffer
E
A Y
E A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
Tristate Busses
Floating nodes are used in tristate processor en1
to bus
busses frombus
• Many different drivers

• Exactly one is active at once video en2
to bus
frombus
sharedbus
Ethernet en3
to bus
frombus
memory en4
to bus
frombus


EEE303-Week02 - Boolean Algebra

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EEE303-Week02 - Boolean Algebra

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Weekly Lecture Plan

Week Topic Textbook

EEE 303 – Digital Electronics Dr. Sajid Muhaimin Choudhury 2

Dr. Sajid Muhaimin Choudhury, Assistant Professor

Dr. Sajid Muhaimin Choudhury, Assistant Professor

• If a given switch is controlled

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• The output is defined as

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Standard Integrated circuits are available for

14 Pin Dual-Inline-Package (DIP) IC are

Most commonly starts with 74 IC number

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Available AND Gate ICs

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Available NAND Gate ICs

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Most common in lab

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Number Axiom Name

Dual: Replace: • with +

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Number Axiom Dual Name

Dual: Replace: • with +

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Dual: Replace: • with +