Scnlstle H TT vsevEnn F 4 Semester M.Tech, Degree Examination, Dec.2019/Jan.2020 = - ASIC Design Qomtax. Macks: 100 ‘Modulest 1 Esplin the flowing in brig With reve dagram, 3) Stand el ns AICS i) ate aay toed ASIC Chanute chane sud outed etary). mars) E14 ——b. Explanin del the eps involved in ASIC design (U0Marks) iG on fe 4] 2 2 expiants Bnetoning and liao of conventional Riple Cary Adder [RCA], wi a ‘evan aegis cel gram coma) BE b Balan Walle res mtr fiom) a u af Mogule3 H A P32 Stowitt Bene spa (vos) 4" ©. cata te pti! sage ett an se of teitoh fr the ct shown below in 5 Fp ose cess Fie) or 4 Explain be ACT logic module with the help of Shannon's expansion totem. (Marks) 'Explnin the Xilinx XC}O0).CLB with eovant diagram ‘aot 9 nora No. On apg our ners comput Modules Le Fe 5 a. Explain hirathital design wih suitable example oan 1 Bxplain vectored instances and buss for 16-bit D-itch and draw te dagram for 4-6 D-lathwith cardinals, ‘oma 10f218EVEI2 on 6 a Liststeps in ASIC physical dsign and describe goal ap objective of ath step. (Mars) ‘8 With relevant equation, explain KL algorthm Construst the connectivity matt forthe network shown in he Below Fig. Q6()- Also fade gain nthe network graph shown if i) Nodes | ad 6 ae swapped th Nodes 2and a suope 7a Bulan sein i raveepine ih es fing commas Eps cone of meee a dey in Nog iing wns on 1 4 Wits martin ctv pent ap lnent maiod apn ry: Bap the flbying 3° Phere ined oe, 2) Thang tenement met (oma Module-5 9 2 apy an ant oP REE ig xin he ing md in an SiG plo sgn ‘ronma bs Bene pol an tthe of gal eu cons) on 10 © tsphin ie fstad Dtsteigagrim 2 2) Awe aritn coma Eryn ew el pn ttn , * a Feo 2000 2of2