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‘Time
First Semester M.Tech. Degree Examination, Dec.2019/Jan.2020
VLSI Testing,
3s ‘Max. Marks: 100
Note: Aner FIVE ul questions, chosing ONE fll question fro tach modal
Modae-1
Explain reat and transit sek ON fi a CMOS wi ip «aoMay
Expan vros ype rigg fa wth example tomar)
on
‘Ws emporry uk? Fe ate diagram of Marko model With exlanain. (Mare)
xp simon process ib Mock gram. toss)
Exp the varus ped of sinuses ‘rowan
Moauies2
For Fig Qa) abn Bolen dite lesbos
1) Deewana on
i), Deerin part Boon sence or yt
¥. min
F
fi
y
: 7
Figgste osm)
Using Reed ~Siur Expansion ein, de st or feton F= WX + WY PY
tod iplemeyt the deign. weaver)
Epa Tee Level OR AND OR die wisSample ‘woman
on
Fd et pate i630, sing D—algri fr Fig 4.
\—_#
2
4
3
We ea & FE
Fig Quo conta
Define PODEM span the wring of PODEM. tesnin)
‘What th sien of FAN wth respest to PODEM? Explain FAN concep ih
cape eons)
Lor?rr
®
1SEVEM4
ules
List and explain various possible fulsin PLA. WrtePLA design fr f, =x, +x)x
and f “5s ‘U0Mars)
‘What i redundancy’? Explain the concept and classification of redundancy with example
tia)
or
Fora given stat table shown in Table Qa ind
1) Response fo 010 conion
3) Homing sequence
ii) Distinguishing sequence
[Preset ate |_InpotS]
x
a
¢
D
Table O67 ois)
Explain the vibe phases involved iyehecking experiment based en sequential eieut
sttcture. (@sMant)
‘Whats sfeonizing sequence? Find synclonizing sequence fr Table Q6(e)
‘Present state | _IapuUNS
Table OA (osnian)
Mosie-s
Define contrlbilty and observsbity ith rexpet to sequential iui testing, Explain
ww example eeu {08 Mars)
‘With diagram, explain the worn of erosscheck and oss check rit {06Mars)
Expliin Boundary sean achestre {06 Mars)
on
Explain clocked Hazy fle ltchos in USSD. cons
Ista the stata of parti sean. Desig pata sean fra comb national ge
oe)
‘Module:s
plain Patudo ~ Random pattern Geerator for BIST with example (costar
{stand explain various types of output response analy (dons)
) oR
‘Exp various es alors for RAM. omar)
Explain BIST stare for SRAM. ‘ontars)
20f2