CTS

vlsi-quest.blogspot.com/2017/11/interview-questions.html

What is useful skew and when we use it ?

If
there is a critical timing path and we are not able to meet timing on that path by the
different optimization technique. Than we take the help
of skew to meet the timing and
this we call it as useful skew. This technique generally we use in the timing critical paths
and when we are using this we should make sure that it is not affecting the other timing
paths.

How the useful skew can be achieved ?

We
can achieve the useful skew by using the macromodels. Let us consider there is a
timing path in which launch flop is FF1 and capture flop is FF2 and there is a timing slack
violation of -500 ps and it can only be achieved only through the useful skew. So at the clk
pin of FF1 we use macromodel of -0.5 ns, it means we are telling the tool that in the
launch path there is already a clock insertion delay of -0.5 ns. So while clock tree building
tool will not add enough buffers in the launch
path, but in actual there is no such insertion
delay of extra 0.5ns on the launch path. So by this technique we will end up with a
positive 0.5
ns slack and timing is met on that particular timing path.

What is preserve pin?

By using preserve pin the clock tree build beyond that pin is not disturbed and it is also
called as the auto macro model.

What is the trigger edge skew ?

It is the difference between the max rise delays.

What is the difference between the local skew and global skew ?

The
skew between two talking flops is called as local skew and the difference between the
max insertion delay and min insertion delay is called as global skew.

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Is there any changes occurs after CTS in timing point of view ? If yes what is the
reason ?

After
CTS timing changes occurs as skew comes into picture, if timing path exhibits
positive skew than it will be helpful for setup and if it is negative skew than it is helpful for
hold. During CTS as clock buffers and inverters are added, tool disturbs the other cells
and try to move them which can be one of the reason for timing degradation.

After CTS which cells placement status is fixed and why ?

After
CTS all the cells present in clock paths are fixed like flops, ICG's, clock buffers and
inverters, clock muxes etc. because if the cells in the clock path are moved than it may
result in the change of skew.

What is the main motive to build clock tree ?

To achieve minimu skew.

To achieve minimum insertion delay
To achieve low dynamic power consumption

During CTS what percentage of power is consumed and why?

Around
40% of the power is consumed during CTS because clock signal is the highest
switching signal in the design which results in more dynamic power consumption.

After CTS why we see false slacks in IN2REG and REG2OUT paths ? How we
overcome it ?

In
IN2REG and REGOUT paths latency is not mentioned on the input and output ports.
So in IN2REG we see huge positive slacks and in REG2OUT paths we see huge negative
slack. So by using the "set_clock_latency" latencies are applied properly.

For clock tree building why we prefer to use higher layer metals ?

As
we go to the higher layers the area capacitance reduces as height from the base
increases. Area capacitance and height are inversely proportional so it leads to less area
capacitance. Less capacitance will
results in less dynamic power consumption.

What is source latency and network latency ?

The
clock network delay from the top level clock port to the block level clock port we call it
as source latency and the network delay from the block level clock port to the flop clock
pin we call it as the network latency.

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What is CTS ? Why it is needed ?

Clock Tree Synthesis(CTS)

is a process in which all the clock nets are buffered with clock
inverters and clock buffers. It’s main motive is to achieve minimum skew, less insertion
delay and less dynamic power consumption.

What is an ideal/propagated clock ?

When clock is not seeing any load than we call it as the ideal clock and when clock tree is
build
the clocks are propagated and actual loads are seen.

From which stage do you see ideal / propagated clocks ?

Before clock tree building clock is ideal and once the clock tree is build the clock is
propagated

How do you reduce insertion delay ?

We can reduce the insertion delays by clock grouping and by setting the proper values to
max delay and min delay

Does CTS honor MCP & False Paths ?

Yes

What is Exclude Pin ?

If there is no need to minimize the skew than we put the exclude pin on that particular
flop clock pins.

What is Preserve Pin ?

Preserve pin is also called as automacro model. By defining preserve pin tool considers
the clcok tree build after that particular cell and dont disturb that clock tree path and also
tells the tool to build the
clock tree to the specified pin where the preserve pin is declared.

What is Leaf Pin ? 

When leaf pin is set tool builds the clock tree only to that particular point

What is Clock Group ?

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By adding clock groups we try to minimize the skew between 2 synchronous clocks

Difference b/w Clock tree and Clock Mesh ?

In clock tree depth

of clock buffers is unlimited and in clock mesh hardley one or two
clock cells are added before connecting to the sink pin.

What is the impact of Max Insertion Delay in CTS ?

Max insertion delay

is the natural insertion delay that is given by the top level guy for the
block levels and it indicates that the maximum this much inertion delay should be
achieved.

What is the impact of Min Insertion Delay in CTS ?

Minimum insertion delay can be changed by the block level guy based on how much skew
is targeted in the block level.

Types of Latency ?

source latency and network latency

What is Source & Network Latency ?

The insertion delay

from the chip level clock port to the block level clcok port is called
source latency and the isertion delay from the block level clock port to
the clk pin of the
flop is called as the
network latency

What is NDR ? Why do you use it ? Adv & Disadv of using it ?

NDR is the non default rules which are set by the block level or top level people for the
particular block or chip respectively. These are mainly use to avoid
the crosstalk effect on
the clk nets as clock
nets are the highest switching nets in the entire design. Advantage is
crosstalk effect is reduced and disadvantage is as the clock nets are routed with double
width and double spacing the no. of routing tracks are reduced and which leads to
congestion.

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Which layers you use for CTS ? Why ?

Generally top layers are used for CTS because area capacitance reduce with that and leads
to lower dynamic power consumption. 

What is the impact of Max Skew  in CTS ? Why is it needed ?

Max skew is nothing but the target skew that tool need to achieve while building the clock
tree 

What is Impact of Postive/Negative skew on hold ?

With positive skew hold timing degrades and with negative skew hold timing improves

What is Impact of Postive/Negative skew on Setup ?

With positive skew setup timing improves and with negative skew setup timing degrades

Why you want minimal skew in CTS ?

By achieving minimal skew it results in less switching as a result it leads to less power
consumption

What is Skew balancing ?

Skew balancing is done in synchronous clock groups to achieve lesser skew

What is Skewing ? useful Skew optimization in CTS ?

Skewing is a process to disturb the clcok paths for getting more skew. The approach in
which the critical timing paths timing is met by adding more positive
skew we call it as
useful skew.

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What is the impact of balancing clocks that are non-synchronous ?

In non-synchronous clock domains kew is not balanced as no data exchange is done in

that case

Impact of CTS on power ?

CTS consumes 40% of

the total power and it is because clock net is the highest switching
net in the design so it leads to more dynamic power consumption

How do you reduce clock power ?

Clock power can be reduced by routing the clock nets in the higher layers.

Where do you generally place clock gaters to reduce power ?

Clock gaters are generally placed near to the clock ports to reduce the power as clcok gater
will produce only the required clcok pulses

What is Clock Buffer ? How is it different from normal buffers ?

The buffers which are used in the clock paths are referred as the clock buffers. Clock
buffers are having sharp rise and fall delays.

Freq vs Setup & Hold ?

With increase in frequency setup timing becomes critical and hold is independent of
frequency

What is Virtual Clock ? Why it is used ?

Virtual
clcoks will not be having any physical clock ports and these are imaginary clocks.
To take into account the false slacks that we see in the IN2REG and REG2OUT paths we
define virtual clocks

What is Cloning ?

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For
dynamic power reduction we use ICG cells and output of that ICG is feed
to the flops
clock pins. If one ICG is used for gating than the density
of flops increases near to the ICG.
To avoid that we define the min and
max fanout of ICG, based on that

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