DATE: 1/08/16

EXP NO.: 1

LOGIC GATES
AIM: To design basic logic gates

TOOL USED: Xilinx Vivado, Digilent Nexys 4.

CODE:

module lab1_1basicgates(

input A,

input B,

output C,

output D,

output E,

output F,

output G,

output H

);

assign C=A&B;

assign D=A|B;

assign E=~(A&B);

assign F=~(A|B);

assign G=A^B;

assign H=~(A^B);

endmodule
TESTBENCH:

module lab1_1basicgates_tb( );

reg A,B;

wire C,D,E,F,G,H;

lab1_1basicgates dut(.A(A),.B(B),.C(C),.D(D),.E(E),.F(F),.G(G),.H(H));

initial

begin

A=0;B=0;

#10 A=0;B=1;

#10 A=1;B=0;

#10 A=1;B=1;

end

endmodule

RTL NETLIST:
SYNTHESIZED DESIGN:

SIMULATION: