FROM ACADEMIC SESSION [2022-23)

THIRD SEMESTER [B.TECH]

DIGITAL LOGIC AND COMPUTER DESIGN (ECC-207)
UNIT-I
Q1. Explain the simplification of switching ftunctions using Karnaugh
Map and Quine Mc-Clusky Methods. (2014)
Ans Karnaugh Map Simplifications: The karnaugh map is a graphical
representation that provides systematic method for simplifying and manipulating
Boolean expressions. This technique is the most extensively used tool for simplification
of Boolean functions. Fig. shows the 2 variable, 3 variable and 4 variable K maps.
For an n variable K-map 2 cells are required. Each cells corresponds to one of
the combination of minterms (or) maxterms ofn variables. There are 2n possible
combinations for n variables. For a 2 variable map, four (2) 4 cells are required.
Similarly for 3 variables, (2) 8 cells are required to construct the 3 variable map. Gray
code is used to identify the celis, the direct binary combinations of 2 variables is 00,
O1, 10, 1i. As a result of the coding, cells which have a common side correspondto
the combinations that differ by the value of just a single variable. The direct binary is
replaced by gray code (00, 01, 11, 10) to avoid error.
Cell designation

A
00 01
110 11
Three variabie K- map

BC BC
o 01 11 10 A 00 01 I 1 0
000 001 011 010

100 101 11 110

7 6
Four variable K- map

CD
CD
AB 00 01 1 10 AB 0001 I 10
00 0000 0001 00110010 00 0 2
O1 0100 0101 0110110 014 76
100101101 11111110 I1231514
10 1000 1001 1011 1010 10 8 110
Fig. 2,3 and 4 variable K-map and decimal equivalent.
Quine-MC Cluskey (Tabulation Method): K-maps are not suitable when the
number of variables involved exceeds four. It may be used with difficulty up to five and
 2021-3
IP. University-(B.Techl-Akash Book

above varinble
fo avoid this diffieulty, we use quine-Me Cluskey method
The
This method issuitable for problema where the number of variabies enceeds four
for simplification of Boolean function by using
Tabulation
lawing steps are followed
fol

method
all minterms in equivalent binary form.
Step 1. List
the minterms based on the number of 1'
Step 2. Arrange
differ by
each binary number from one group to other and if they
Step 3. Compare (3) mark
and copy the remaining term, Place tick
only one bit position putdash mark)
after each comparison.
and
the same process described in step 3 for the resultant column
Step 4. Apply
further elimination
these cyoles until a single pass through cycle jields no
continue
co

ilterals.
chart.
unticked prime implicant and form the prime implicant
Step 6. List the
in a coumn. The
implicant is represented in a row and each minterm
Each prime that make
are placed in each row to
show the comparison of minterms
cross mark (x)
from this chart we can simply the expression.
the prime implicant
x column and select the prime implicant
corresponding to that
i) Search for single
the star mark in front of it.
dot by putting minterm is
Search for multiple dot columns one by one. If the corresponding
(i) the minterms and go to next
muiti dot
include in the final expression ignoring
already
otherwise include the corresponding prime
implicant in the final expression.
column (2014)
Theorem
9.2. Explain De Morgan's important part of
Theorem: DeMorgan's theorem are very
Ans. DeMorgan's
two theorems.
Booleam algebra. DelMorgan suggested
the sum of the complements.
Theorem 1. The complement
of a product is equal to

for Demorgan's theorem 1

Table shows the truth tatle

AB-A-8
theorem 1.
Table. Truth table for Demorgan's

ABAB A.B B
o 01
1
o 10
0 01

variables combinations of variables.

to any number of
or
This law can be extended
For example
ABCD.. = A B+ ++

CD EFG
(AB)CD)(EFG).. AB =

complements.
Theorem 2. The complement of a sum
is equal to the product of the
second theorem
Table shows the truth table for Demorgan's

A+BA.B
 4-2021 Third Semester, Digital Logie and Computer Design

Table: Truth table for Demorgan's second theorem

BAB4+ B4.B
o 01
o1000

This law can be extended to any number of variables or combinations of variables

For example.
A+B+C+D+ = B. .D.
EFG+..
AB CD+ EFG+= AB.CD
9s. Draw the logic diagram of s-bit parity generator and respective truth
table. (2014)
Ans. A parity bit of a 0' or a 'l' is attached to the data bits such that total no. of 1's
in the vord is even parity and odd for odd parity. The parity bit can be attached to the
code group either beginning or at the end depending on system design.
3-bit Even Parity Generator: In even parity the added bit (aprity bit) will make
the number of l's an even. Table shows the truth table of a 3 bit even parity generator.
Table. Truth Table for 3-bit even parity generator

3-bit message Even parity bit

C

94. Solve the following equation using Boolean algebra: (2015)

ABC ABC+ ABC+ ABC
Ans. Given that ABC + ABC + ABC'+ ABC
BC (A+A') +A BC+ ABC'= BC + ABC+ ABC
BC +A (B C)
Q5. Simplify the given equation using K-map: (2015)
F=x+xy+*+*y7
Ans. Given that F = x'+xy + xz' + xy'?

It is 3-variable equation, hence

F
y27z yz Yz

F +y
 2021-6
LP.Universily-1B.Tech-Akash Books
(2016)
(a) Implement using 8:1 multiplexer
Q.4.
= Zm (2,4,5,7,10,14)
FA,B,C,D)
that F (A, B, C, D) = Zm (2, 4, 5, 7, 10, 14) we have to implement
Ans. Given then
x 1 MUX. Let A is used as an input and B,C,D are as selection lines,
in8
imp'ementation table is

0 2 3
A 8
11 11 12 13 14 15

81
-F (A,B.CD)
MUX

logic 1 Logic '0"

aCD
(2015)
in the given equation:
Q.7. Find essential prime implicant
F (WX,Y,Z) Em (0,2,4,5,6,7,8,10,13,15)
=

Ans. Given that F (W, X, Y, Z) Em (0, 2, 4, 5, 6,

= 7, 8, 10, 13, 15)

yZ
Wx
YZ

W
6
Wx
12| 15 14
wx
1
9
w 1

Essential prime implicants = 5

Q.8. Write short notes on

(i) Encoder (2015)
Ans. Encoder: An encoder is a combinational logic circuits. It is reverse of a
decoder function. If has 2n input lines and 'n' output lines. An encoderaccepts an active
decimal/octal digit and converts
evel on one of its inputs
representing a digit such as a

it to a coded
output.
 6-2021 Third Semester, Digital Logic and Computer Design

2n n lines output
2input
lines
Encoder

9.9 Convert the Hexadecimal number 68BE to Binary and then convert
to Octal.
Ans. Given hexadecimal number8is 68BE
0110 10001011110
To convert it into octal number, grouping starts from right to left in the form of
bit.
o110 100 0101
2 16
Octal representation = 64276
9.10 Subtract the following binary No's (2
10110-1011 i) 1100.10-111.01
Ans. ) 10110-1011 1011
) 110. 10-111.01 = 0101.01

Q11 Implement function Fla, b, e) ab+be using 4:1 Mux. (2015

Ans. Given that F
(a,b,c) ab+bc
=

ablc+)+(a+abc
+110 t101 to01
F (a,b,c) = m (1,5,6, 7)
Let a as an input and b and c as a select line. The implication table is shown below

A o O 2 3
A 4 O
01 AA

4x1 -F (a,b,c)
v
MUX

b
Q.12. With the help of equations explain 4 bit comparator. (2015)
Ans. Amagnitude comparator is a combinational circuit that compares
numbersA and B, and determines their relative magnitudes. Consider 2 numbers.two
A
and B with 4 digits each.
 LP.University-[B Techl-Akash Books 2021-7

A AAAA,

B B,B.B,B,
The 2 numbers are equal if all pairs of significant digits are equal ie. A, = B,, A,

B, A,
=
B, and A, B
The equality function of each pair of bits can be expressed logically with an
equivalence function.

x= A.B+A^ B;
i = 0,1,2,3
t
Where x, 1 only if the pair of bits in position i are equal ie., if both are l's or both
are 0's.

For the equality condition to exist, allx variables must be equal to 1. This dictates
an AND operation of all variables
3
(A-B) AA
The binary variable (A =B) is equal to 1 only if all pairs of digits of the two numbers

are equal.
of
To determine if A is greater than or less than B, insect the relative magnitudes
If the two digits
pairs of significant digits starting from the most significant position.
are equal, compare
the next lower significant pair of digits. This comparison continues
until a pair of unequal digits is reached.
(A B) = AB,+z,A,B,+x>AB, +137A,3,
(A <B) = A,B, + zA,B,+xpA,B, + F,A,B,

(A B)
A

A> B)

D
(A B)
(4 bit-comparator)
 and Computer Design
Third Semester,
Digital Logic
&-2021
following multiple
output combinational loi
Q.13. Implement the

(iii) F, m(0,1,5,6)(201)
using a 3-to-8 line Decoder?
m (2,4,6)
( =m (0,1,2,6) ii) F, =

Ans. Given that

(ii) F = Em(2, 4, 6)
() F = m (0, 1, 2, 6)

38
3x8 F1 Decoder 4
Decoder -F2
5

(ii) F = Em (0,1,5,6)

3x8
3 -F3
Decoder

9.14. Subtract 748 from 983 using *'s complement method. (2016)
Ans. Equating the number of digits 983-748
9's complement of 748 = (10--1)- 748 = 251
Minuend = 983

9's complement of 748 251

1234
Cary L1
235
Q.15. Simplify the expression using Boolean algebra: (2016)
AB+ (AC)+ ABC(AB+C)
Ans. Given that
AB+ (AC +AB C(AB C)
AB+AC+ABC =AB+ ABC

AB BC)+ AC A(B+C)+ : B+ BC B+C]

ABAC+A+C AB+ AC+ AC= AB+ 1=1 :A+A=1
Q.16. Give a Boolean expression for the following statement:
Y is a 1 only if A is al and B is a 1 or if A is a 0 or B is a 0 (2016)
Ans. Given that
Y l ifA =1, B=1
1 if A=0, B=0
 I.P. University-IB.Tech)-Akash Books 2021-9

Truth Table

A8Y YAB AB
0
1
0 1
B
1
2-input ANOR Gate
11 (2016)
1011 to (i) Excess 3; (i) Octal.
Q.17. Convert
Ans. Given that 1011
Excess 3 1110 =
(i)
(ii) Octal = 13
(2016)
Q.18. Design an 8:1 multiplexer using 4:1 multiplexer and gates.
Ans.8:1 MUX using 4:1 MUX
Truth table
Do
D SSS OutputY
D2 MUX-1
4x1 Y
Do

1 0 D
D 4x1 1 Ds
Ds MUx-2 1 1 0 Ds
D D

Q.19. Design a full adder using a 3:8 decoder and gates (2015),(2016)

Ans. For Full adder, we have

Sum Em (1,2,4,7)
and Carry = Em (3,5,6,7)

Sum
(MS8)
38
Decoder

(LS8) C Cary

Enable
 and Computer Design
Semester, Digital Logic
Third
10-2021 using K-map:
funetion

Q.20. Simplity the

Boolean

(0, 2, 6)
(2016)
11, 16) +Sd
FA, B, C, D)
= m (1, 3, 7,
function is
Ans K-map for the given
CD
11 10

00AB 1 1

01 6

11 AB 14
13 15
12
10 AB 9 11 10

CD

F AB+ +CD

Q21. Comvert (444.456)* to an

octal number. (2016)
Ans Given that (444.456)

8444
8 55 44
5

(444) (674),
Real part Fraction part Real part
0.456x6 3 648 3

0.648x8 = 5 184 5

0.184x8 1 472 1

0.472x8 3 776
(0.456) (0.3513),
(444.456), (674.3513),
22. Convert (A6BF5),. to binary. (2016)
Ans. Given that (A6BP5),
To convert it into binary, write down separate binary no. for each
(1010 0110 1011 1111 0101),
Q.23. Simply the expression y = Em. (3, 4, 5, 7, 9, 13, 14, 15) using k-map
method. (2016)

Ans. Given the four variable expression, we know that

 2021-11
L.P. University-(B Tech|-Akash Books

FCD
AB
C
00
00 AB

01

11 AB
15 14
12 12
10 A
10

CD
Y = AB A D+ ACD+ ABC

operation of single bit magmitude

Describe the circuit and (2016)
Q.24.
comparator.
whiech compares
is a combination logic cireuit
Ans. One bit magnitude comparator
code and gives three outputs.
the two inputs in the binary
Truth Table of 1-bit comparator
Comparator Outputs
Comparator Input A<B
B A>B A-B

1
0

0 0

1 1
(A> B) = AB

(A B) = AB+ AB = AOB

(A <B) = AB

AE

A B

D-AA<8
 Digital Logic and Computer Design
12-2021 Third Semester,
complem
Q.25. Add - 10 with -10 using
8-bit arithmetie 2's
omplement method?
Ans. (10)0 (00001010),
(2017)
2's complement of (--10)
= (11110110),

01 10
-10)2 1111
11 11 0110
()-10) (+)

11 10 1 100

Carry be ignored
(11101100), » 2's complement of addition of- 10 and-10 in 2s complement f
rm.
F(A, B, C, D) =X(0, 1,2,5, 7,8, 9, 10, 14, 15). Find all the prime implios..
Q.26. ts,
SOP expression.
essential prime implicants and minimal
(2017)
Ans. FA, B, C, D) X0, 1, 2, 5, 7, 8, 9, 10, 14, 15)
=

00 01 11 10
CD
00

01

11

11
Minimal SOP expression.
F BC+ABD+ABC+BCD
There is no essential prime implicants in the given above output expression. All the
minterms in the SOP expression is prime implicants.
9.27. Realize full adder circuit using minimum number of two input NAND
gates only. (2017)
Ans.

D- Sum

B
D-
Cin Cout

Q.28. Signals A,B, C, D and are available. Using a single 8 to 1 MUX and a
other gates. Implement the Boolean function f(A, B,
C, D) BC + ABD + =
A
(2017)

Ans. f(A, B, C, D) =
BC+ ABD +
 2021-13
I.P. University-1B.Tech)-Akash Books

B D Outputs
A
0 0
0

0
2
0
3
4

5
1
6
1
1
1 0 0
8
9
1
10
0 1
11
12
13 1

14 1
1 1 1
15

D 8 8 8 8 8

D 0

B C

8:1 F (output lines)

MUX

Q.29. Consider two bit number X and Y. X consists of X,X, and Y consists of
Y,Y. Design a circuit with three outputs Z, Z, and Z, such that: (2017)
(i) Z, 1 when X <Y (ii) Z, = 1 when X = Y (iii) Z, = 1 when X>Y
 Digital Logic and Computer Design
14-2021 Third Semester,
comparator.
Ans. Truth table for 2- Bit Magnitude
Outputs
Inputs
XX Y,YZ)
X,X,Y,Y XX= Y,YoZ) X,XY,YZ)
0 0
0 0 0 0
0
0 0 0 1
0 01 0
o 01 1
0 1 0 0
01 0 1
0 1 1 0
0 1 11
0 0
1 0 0
010 1
1 1
1

Expression for (Z,)

Z, +X7Y, +xX7Y, +XX,Y¥
X,®Y XX®Y) YY 00 01
Similarly, Z I¥o XY1 +X,¥1¥o xx.
00+
1
11 10

01

10

=D

=D
 2021-15
IP. University-|B.Techl-Akash Books
2017)
is the ASCII code a 7 bit code?
Q.30. Why Inter change (ASCII)
pronounced
Information
code for
The American standard code. Since the
Ans.
numeric code. This is
basicalily a 7-bit
'ASKEE' is a widely used alpha 27 128, the ASCII
created with 7-bits is
=
as
that can be
different bit patterns characters of the alphabet
number of c a s e and upper
case
both the lower decimal digits.
can be
used to encode addition to the 10
a s well, in
and some special symbols small computer
(52 symbols) terminals that
interface with
for printers and
It is used.extensively
systems. name them?
of the Boolean expression
What are the two basic form (2017
Q.31.

of the Boolean expression are

Ans. Two basic form
(POS)
i) Of Product (SOP)
Sum
(i) Product Of Sum
minimum number of NAND gate only.
Realize EX-OR gate using (2017)
Q.32.

Ans.

A D Output A B

it with NOR
Boolean expression and implement
Q.33. Simplify the given
(2017)
gate circuit only F AB+ ABD + ABD ACD + ABC
=

Ans.
F = AB+ ABD+ AB+ AD+

AB
00 01 11 10
CD

01 1
11

10

F A+ BC+ACD5
Q.33. What are the essential prime implicants? (2017)
Ans. Each square or rectangle made up of the bunch of adjacent minterms is called
a subeube. Each of these subcubes is called a prime implicants (PI). The PI which
contains at atleast one 1 which cannot be covered by any other Pl is calied an essential
prime implicant (EPI).
9.34. Minimize the following function using K-map (2017)
) F = Zm (1, 2, 6, 8, 9, 10)
ii) F = Em (2, 4, 6, 7, 9, 12) +d(0, 1, 6)
 Logic and Computer Design
16-2021 Third Semester, Digital

8, 9, 10) ii) F, = m(2, 4, 5,7,9, 12)+ d(0,

Ans. (i) F, Em (1, 2,6,
=
1,6)
AB
CD 00 01 11
00 01 11 CD 10
AB
00 o0
01
o01||

10
10
F BCD +ABD F AB +BCD +AD +BCD
Q.35. Obtain the decimal equivalent of the given hexadecimal Di
er
(3A2F) (2017)
3 16+ 10 » 16° +2 x 16+ 15 x 16-2
Ans (3A. 2F), = x

= 48+10++
16 256
58+0.125+0.058 =(58.183),
Q.36. Implement the following Boolean function using 8:1 MUX.
(2017)
FA, B,C, D) = Sm (0, 1, 2, 4,6, 9, 12, 14).
Ans. FA, B, C, D) = Em(0, 1, 2, 4, 6, 9, 12, 14)

Logic Table

Logic 1 0

8:1
D
MUX
Logic 0

Logic A B C

Logic Diagram
Q.37. Explain in brief the working of BCD to seven segment desoder.
(2017)
Ans. Seven segment displays
are used to give a visual indentification of the output
states of digital ICs such as counters,
registers etc. These outputs are usually in 10u
bit BCD Binary Coded Decimal

Form and thus not suitable for driving seven

segment displays. A special decoue
is designed to drive from BCD code to 7-segment
display, it is called BCD to 7-segmen
decoder. This shows the segments activated during each
digit display.
 2021-17
I.P. University-[B.Tech-Akash Books

Table
Segment Activaud
Duplay
Duit
2
a,h,c, d,e,

b,e

a,b,d,e.

3
a, b,c,d.g

6, c.f.

a,c,d,

a,,d,e,

, ,e

a,b,c, d,e,f.s

9 a, b,c,a.t.&

From the table we can determine the truth table for BCD to 7 segment decoder/
driver. This truth table is formed for common cathode 7-segment display. If 7-segment
display is common mode, the segment driver output must be active LOW to glow the
segment. In case of common cathode type 7-segment display, the segment driver must
be active high to glow the segment. Table shows the truth table for BCD to 7-segment
decoder/driver with common cathode display.
 Digital Logic
and Computer Design
Semester,
Third
18-2021 7-segment display.
cathode
common

table
Table truth
7-Segment
BCD input C
Dat C
B
1
0 0
1
0
0 1 1
2 0
1
0 0
0
1
0
0 1 0
1 0

1 1 1 1
0
1 1 0
0

1101, 1110, 1111. so place X

X Dont
Don't care
codes are 1010, 1011, 1100,
The unused BCD
cells.
condition for these corresponding

K-map Simplifcation
Forb
For a
CD
CD AB 000 01 11
10
AB 00 01 11 10

00
oo
0
01
11 11 x X

10

a A CBD B0 b B CÖ CO

For For d
CD CD
00 01 11 10 AB 00 01 11 10
00

01 01

11 X
XXIx 11

1o
c 8 CD d B0 Cð + BËD BCA
 I.P. University-|B.Tech|-Akash Books 2021-19

Fort
Fore CO For 9
CD CD
11 10 AB 0G 01 10 11 0
AB 00 01 00 01
00 0
001
01 01

11X 11

1=A CD B BO
gA BT BC co

decoder/
shows the logic diagram of BCD to 7-segment display
Logic diagram: Fig.
driver.
8

80
D

CD

BCD

BC
BC

BO

Flg. Logie diagram for BCD to 7-Segment, decoder display

 Digital Logic and Computer Design
20-2021 Third Semester,
circuit using minimum number. of NAND ga
Q.38. Realize the half adder
only.
Ams

A -s

o 0 0

S AB, C AB

.39. Add (s),, + (34),, using BCD codes. (2018)

Ana. (97) + (34)0

BCD representation (97) 1001 0111

(34)0011 0100
1001 0111
0011 0110
1100 1011 No. is invalid BCD code
To make it valid BCD code add
(0110),
1 1
1100 1011
+0110 0110
10011 0001
(O001 0011 0001)ecD
Q40. Realize F XY'+XZ+ YZ using minimum number of two inputN
gates (2018

Ans. F X+ z +Y}
Take bar on above expression.
 2021-21
LP. Uaiversity-1B.Tech-Akash Book

X-L

z-

Y-
Z

X + Z+ YZ

-(R.v)(x.2)(9+2)
(2018)
941. The minimal sum of produet is given by
P AC+AD+BD
Pind eanonieal 8.0.P and canonical P.O.S

Ans P AC+AD + BD, Minimal sum of product form

c o e

00 01 11 10

00
01

Canonical 8OPform= ABD+ ABCD+ ABD+ + ABD +

ABCD+ + ABCD+ ABcD
Canonieal POs form = (4 + B+C+ D).(A ++C+ D).(A + B++D).
(A+B++D).{ B++ D).{ B++ D)
Q43. Simplify FA, B, C) Em (0, 1,2, 5, 6, ) using -M method. (2018)
Ana FA, B, C) = Em (0, 1, 2,5, 6, 7) Using Q.M. method

Variables
GroUp Mintem 3 c
0

1
1 0
1 1
 Digital Logic and Computer Desion
Third Semester,
22-2021
P.I
Vanables
B C 1 2 56
Group
Matched pair
0 AB 0,1 x
0, 1
0
0 AC 0,2 X
0,2 0
BC
1,5
0
BC
1,5
2,6
AC
2,6
2 5,7 5,7
AB
6,7 11 6,7
Fig.

In this particular question,

there is no EPI, so all are PI.
circuit diagram of 3-bit 1's complin
Q43. Draw and explain the ment add
subtractor.
subtraction operations are combined into
20
Ans. Here the addition and
This is done by including an X-OR gate ne cir-
with one common binary adder. with
adder. The mode input M controls
the operation. When M 0, the circuit each
an C
f =

a substractor. Each X-OR gate receiven

and when M 1, the circuit becomes
=

and one of the inputs of B. when M = 0, we have B 0 = B. The full adder

value of B, theinput carry is O and the circuit performs A + B. when Mreceives
1 sha
BO1 and C, = 1. The B inputs are complemented and a l is added through the:
the ing
carry. The circuit performs the operation A plus the 2's complement of B.

B
M

C FA
CIn
FAg FA2

Logie diagram of a 3-bit Binary Adder/Subtractor

Q44. Implement three input X0R gate using 2:1 MUX and basic gat-
(201
Ans. Truth Table for 3-input XOR gate
F ABeC

Inputs Output
0
C F
0
0 0 1
F,
0
0 F.
 2021-23
L.P. University-[B.TechJ-Akash Books

0
0 0

F
S, and
inputs as a select lines means A represent S, B represent
Lets treat these
C represent S,

So
2
S
F2 1
2 -F

Fs2 1
21
2x1
S
fA, B, C, D) r(0, 1, 2, 4, 5, 8,9,
Using K-map simplify expression, Y
= =

Q.45.
(2018)
15)
Ans. Y fA, B, C, D) =r(0, 1, 2, 4, 5, 8, 9, 15)

CO00
A O0L 01 11 10

oo
01 o 0
11

1
Y (A+ C(B+C)(A + B+D)( ++ + D)
Q46. How many combinations are there for output logic 1 of 2-bit
comparator, if output Y is logic 1 whenever 2-bit input A is greater than 2-bit
input B? (2018)
Ans.

Inputs Output
ABB,| A>B

0
0 0
0| 0
1| 0

1 0

0 1 1|
 Computer Design
Third Semester, Digital Logic and
24-2021
0
0
1011
11 0
0
0 111
0 00
01

10
101

111
combinations to satisfy the condition.
have six possible
According this table
we

to Gray
Converter (2015),201
important a Binary
Q47. Desim and converter: This
code converter combination
code
Ans. Binary code
to gray code of code converter
to Gray code. The input
convert binary
circuit is designed to code.
converter is Gray
code of code
binary. The output
Truth Table
Gray Codde
Binary Code

C B G,G G, G
D 0
0
0
0
0
0

0 0
1 0
0

0
0

0 0

1 0 1 0
0
0 0
0 0

0 0

0 1 0

0
0
 L.P. Univereity-1B.Tech-Akash Books
2021-25
K-Map Simplißication
Expreeslon For G Expresslon tor G,
0111 12 DCCo01 1110
0005 2

2
108 P21 d

Expression for G Expreeslon for G

oo01 11
COTTT3T} 01 11 10
01 ,
3)
112 5 01
al 108 1
is 10 r io
T.

GDC D =C® D
We get the simplified boolean expression for the eode converter of Binary of Binary
to Gray code
G, B -B®A
G, = CB+ B= C®B

G, D+DC-C®D
G = D

P 1g the above expression we can construct the binary to gray code converter
as foli see Fig.).
Logie Diagran
B Ao Binary code

G GSmy code
Ng. Logie cireuit for binary to gray code converter
948. Implement the logie expression using 4:1 MUX,F Em (1, 3, 5, )
(2018)
Ans, F Em (1,3,5, 7)
 Design
26-2021 Third Semester, Digital Logic and Computer

S
A B

0 FC D 4x 1 MUJX
0
1 F C D2
0 S, So
FC
0 A

L F-C
(2018)
Q49. Design a n even parity bit generator circuit.
Ans
Even-Parity
Raw Data
Data (to be
(to be transmitted)
tansmitted)

Even parity

Fig. Even Parity generator

Error in the data can be detected using XOR gates. Binary data may be corrupted

during transmission and processing.

that alter some of the '1' in
corruption may be due susceptive to noise
can
This data
such errors. Detection of such
to zeros or zeros' or in to 1' s. It is important to detect
errors can be done by using additional bit called Parity bit' that is to be added before
bit will be used to check
transmitting the original data. At the receiving side, the parity
for any errors and then the additional bit will be truncated before processing the data.
Q50. Perform the following operations: (2018)
) BC5,-A3B, ) 23,+45, i ) 10110,*1101,
Ans. () (B C 516 (0) (2 3)8 (1) 10110
x1101
(A 3B)18 45 10110
1 8A 70 00000x
10110 xx
10110 x xx
100011110