MC33272A, MC33274A,

NCV33272A, NCV33274A

Single Supply,
High Slew Rate,
Low Input Offset Voltage
Operational Amplifiers http://onsemi.com

The MC33272/74 series of monolithic operational amplifiers are MARKING

DUAL DIAGRAMS
quality fabricated with innovative Bipolar design concepts. This dual
8
and quad operational amplifier series incorporates Bipolar inputs
along with a patented Zip−R−Trim element for input offset voltage PDIP−8 MC33272AP
reduction. The MC33272/74 series of operational amplifiers exhibits P SUFFIX AWL
CASE 626 YYWWG
low input offset voltage and high gain bandwidth product. 8
Dual−doublet frequency compensation is used to increase the slew rate 1 1
while maintaining low input noise characteristics. Its all NPN output 8
stage exhibits no deadband crossover distortion, large output voltage SOIC−8 33272
8 D SUFFIX ALYWx
swing, and an excellent phase and gain margin. It also provides a low
1 CASE 751 G
open loop high frequency output impedance with symmetrical source
1
and sink AC frequency performance. x = A for MC33272AD/DR2
= N for NCV33272ADR2
Features
QUAD
• Input Offset Voltage Trimmed to 100 mV (Typ) 14
PDIP−14
• Low Input Bias Current: 300 nA
P SUFFIX
MC33274AP
AWLYYWWG
• Low Input Offset Current: 3.0 nA CASE 646
• High Input Resistance: 16 MW 14 1

• Low Noise: 18 nV/ √ Hz @ 1.0 kHz 1 SOIC−14

D SUFFIX
• High Gain Bandwidth Product: 24 MHz @ 100 kHz 14
CASE 751A
1
• High Slew Rate: 10 V/ms
14 14
• Power Bandwidth: 160 kHz
MC33274ADG NCV33274AG
• Excellent Frequency Stability
AWLYWW AWLYWW
• Unity Gain Stable: w/Capacitance Loads to 500 pF
1 1
• Large Output Voltage Swing: +14.1 V/ −14.6 V
• Low Total Harmonic Distortion: 0.003% TSSOP−14
14
• Power Supply Drain Current: 2.15 mA per Amplifier DTB SUFFIX
CASE 948G
• Single or Split Supply Operation: +3.0 V to +36 V or
1
±1.5 V to ±18 V 14 14
• ESD Diodes Provide Added Protection to the Inputs MC33 NCV3
274A 3274
• NCV Prefix for Automotive and Other Applications Requiring ALYWG ALYWG
Unique Site and Control Change Requirements; AEC−Q100 G G
Qualified and PPAP Capable 1 1
• Pb−Free Packages are Available A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

July, 2013 − Rev. 14 MC33272A/D
 MC33272A, MC33274A, NCV33272A, NCV33274A

PIN CONNECTIONS

DUAL QUAD
CASE 626/751 CASE 646/751A/948G

Output 1 1 8 VCC Output 1 1 14 Output 4

2
-
7 Output 2
Inputs 1 +
2 13
3 6 Inputs 1 - -
- Inputs 4
+ Inputs 2 3 + 1 4 + 12
VEE 4 5

VCC 4 11 VEE
(Top View)
5 10
+ +
Inputs 2 - 2 3 - Inputs 3
6 9

Output 2 7 8 Output 3

(Top View)

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC to VEE +36 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ +150 °C
Storage Temperature Tstg −60 to +150 °C
ESD Protection at Any Pin Vesd V
− Human Body Model 2000
− Machine Model 200
Maximum Power Dissipation PD Note 2 mW
Operating Temperature Range MC33272A, MC33274A TA −40 to +85 °C
NCV33272A, NCV33274A −40 to +125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).

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 MC33272A, MC33274A, NCV33272A, NCV33274A

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V) 3 |VIO| mV
(VCC = +15 V, VEE = −15 V)
TA = +25°C − 0.1 1.0
TA = −40° to +85°C − − 1.8
TA = −40° to +125°C (NCV33272A) − − 2.5
TA = −40° to +125°C (NCV33274A) − − 3.5
(VCC = 5.0 V, VEE = 0)
TA = +25°C − − 2.0
Average Temperature Coefficient of Input Offset Voltage 3 DVIO/DT mV/°C
RS = 10 W, VCM = 0 V, VO = 0 V, TA = −40° to +125°C − 2.0 −
Input Bias Current (VCM = 0 V, VO = 0 V) 4, 5 IIB nA
TA = +25°C − 300 650
TA = Tlow to Thigh − − 800
Input Offset Current (VCM = 0 V, VO = 0 V) |IIO| nA
TA = +25°C − 3.0 65
TA = Tlow to Thigh − − 80
Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) 6 VICR V
TA = +25°C VEE to (VCC −1.8)
Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kW) 7 AVOL dB
TA = +25°C 90 100 −
TA = Tlow to Thigh 86 − −
Output Voltage Swing (VID = ±1.0 V) 8, 9, 12 V
(VCC = +15 V, VEE = −15 V)
RL = 2.0 kW VO + 13.4 13.9 −
RL = 2.0 kW VO − − −13.9 −13.5
RL = 10 kW VO + 13.4 14 −
RL = 10 kW VO − − −14.7 −14.1
(VCC = 5.0 V, VEE = 0 V) 10, 11
RL = 2.0 kW VOL − − 0.2
RL = 2.0 kW VOH 3.7 − 5.0

Common Mode Rejection (Vin = +13.2 V to −15 V) 13 CMR 80 100 − dB

Power Supply Rejection 14, 15 PSR dB
VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V 80 105 −
Output Short Circuit Current (VID = 1.0 V, Output to Ground) 16 ISC mA
Source +25 +37 −
Sink −25 −37 −
Power Supply Current Per Amplifier (VO = 0 V) 17 ICC mA
(VCC = +15 V, VEE = −15 V)
TA = +25°C − 2.15 2.75
TA = Tlow to Thigh − − 3.0
(VCC = 5.0 V, VEE = 0 V)
TA = +25°C − − 2.75
3. MC33272A, MC33274A Tlow = −40°C Thigh = +85°C
NCV33272A, NCV33274A Tlow = −40°C Thigh = +125°C

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 MC33272A, MC33274A, NCV33272A, NCV33274A

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Slew Rate 18, 33 SR V/ms
(Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) 8.0 10 −

Gain Bandwidth Product (f = 100 kHz) 19 GBW 17 24 − MHz

AC Voltage Gain (RL = 2.0 kW, VO = 0 V, f = 20 kHz) 20, 21, 22 AVO − 65 − dB
Unity Gain Bandwidth (Open Loop) BW − 5.5 − MHz
Gain Margin (RL = 2.0 kW, CL = 0 pF) 23, 24, 26 Am − 12 − dB
Phase Margin (RL = 2.0 kW, CL = 0 pF) 23, 25, 26 fm − 55 − Deg
Channel Separation (f = 20 Hz to 20 kHz) 27 CS − −120 − dB
Power Bandwidth (VO = 20 Vpp, RL = 2.0 kW, THD ≤ 1.0%) BWP − 160 − kHz
Total Harmonic Distortion 28 THD %
(RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) − 0.003 −

Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz) 29 |ZO| − 35 − W

Differential Input Resistance (VCM = 0 V) Rin − 16 − MW
Differential Input Capacitance (VCM = 0 V) Cin − 3.0 − pF
Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) 30 en − 18 − nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz) 31 in − 0.5 − pA/ √ Hz

VCC

- +
Vin Vin

+
Sections VO
B C D

VEE

Figure 1. Equivalent Circuit Schematic

(Each Amplifier)

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 MC33272A, MC33274A, NCV33272A, NCV33274A

2400 5.0
MAXIMUM POWER DISSIPATION (mW)

IO INPUT OFFSET VOLTAGE (mV)

2000 VCC = +15 V
3.0
MC33272P & MC33274P VEE = -15 V
VCM = 0 V
1600
1.0 3
MC33274D 1
1200 2 2
1
-1.0 3
800 1. VIO > 0 @ 25°C
MC33272D
2. VIO = 0 @ 25°C
-3.0 3. VIO < 0 @ 25°C
400

V,
P(MAX),

0 -5.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180 -55 -25 0 25 50 75 100 125
D

TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 2. Maximum Power Dissipation Figure 3. Input Offset Voltage versus
versus Temperature Temperature for Typical Units

400 600
350 VCC = +15 V
500
IB, INPUT BIAS CURRENT (nA)

IB, INPUT BIAS CURRENT (nA)

VEE = -15 V
300 VCM = 0 V
400
250

200 300

150
VCC = +15 V 200
100 VEE = -15 V
TA = 25°C 100
I

I

50

0 0
-16 -12 -8.0 -4.0 0 4.0 8.0 12 16 -55 -25 0 25 50 75 100 125
VCM, COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Bias Current versus Figure 5. Input Bias Current
Common Mode Voltage versus Temperature
ICR INPUT COMMON MODE VOLTAGE RANGE (V)

VOL OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)

VCC 180
VCC -0.5 VCC

VCC -1.0 160

VCC -1.5
VCC -2.0 140

VCC = +15 V
VCC = +5.0 V to +18 V VEE = -15 V
VEE +1.0 120 RL = 2.0 kW
VEE = -5.0 V to -18 V
VEE DVIO = 5.0 mV f = 10 Hz
VEE +0.5 DVO = -10 V to +10 V
VO = 0 V
V,

A,

VEE 100
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage Figure 7. Open Loop Voltage Gain
Range versus Temperature versus Temperature

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 MC33272A, MC33274A, NCV33272A, NCV33274A

V sat , OUTPUT SATURATION VOLTAGE (V)

40 VCC
Source
TA = 25°C
VO, OUTPUT VOLTAGE (Vpp )

VCC -1.0 TA = -55°C

30
RL = 10 kW TA = 125°C
VCC -2.0 TA = 25°C
20 RL = 2.0 kW
VEE +2.0 Sink TA = 25°C
TA = -55°C
10
VEE +1.0 TA = 125°C
VCC = +5.0 V to +18 V
VEE = -5.0 V to -18 V
0 VEE
0 5.0 10 15 20 0 5.0 10 15 20
VCC, VEE SUPPLY VOLTAGE (V) IL, LOAD CURRENT (±mA)
Figure 8. Split Supply Output Voltage Swing Figure 9. Split Supply Output Saturation
versus Supply Voltage Voltage versus Load Current
V sat , OUTPUT SATURATION VOLTAGE (V)

VCC 15

V sat , OUTPUT SATURATION VOLTAGE (V)

TA = 125°C
VCC
VCC -4.0 14.6 TA = 125°C
TA = 55°C VCC = +5.0 V to +18 V
RL to Gnd TA = 25°C
VCC -8.0 14.2
VEE = Gnd
TA = 55°C
VCC -12

+0.2 8.0 TA = 25°C TA = 125°C VCC = +15 V

TA = 125°C RL to VCC
TA = +25°C TA = -55°C VEE = Gnd
+0.1 4.0
TA = -55°C RFdbk = 100 kW
Gnd
0 0
100 1.0 k 10 k 100 k 1.0 M 10 100 1.0 k 10 k 100 k
RL , LOAD RESISTANCE TO GROUND (kW) RL, LOAD RESISTANCE TO VCC (W)
Figure 10. Single Supply Output Saturation Figure 11. Single Supply Output Saturation
Voltage versus Load Resistance to Ground Voltage versus Load Resistance to VCC

28 120
CMR, COMMON MODE REJECTION (dB)

VCC = +15 V
24 100 VEE = -15 V
VO, OUTPUT VOLTAGE (Vpp )

TA = -55°C VCM = 0 V
20 TA = 125°C
80 DVCM = ±1.5 V

16
60
12 VCC = +15 V -
DVCM ADM DVO
VEE = -15 V
40 +
8 RL = 2.0 kW
AV = +1.0
DVCM
4 THD = ≤1.0% 20 CMR = 20Log X ADM
TA = 25°C DVO
0 0
1.0 k 10 k 100 k 1.0 M 1 0M 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 12. Output Voltage versus Frequency Figure 13. Common Mode Rejection
versus Frequency

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 MC33272A, MC33274A, NCV33272A, NCV33274A

120 120
+PSR, POWER SUPPLY REJECTION (dB)

-PSR, POWER SUPPLY REJECTION (dB)

TA = 125°C VCC = +15 V DVCC = ±1.5 V
VEE = -15 V VCC = +15 V
100 100
DVCC = ±1.5 V VEE = -15 V
TA = -55°C
80 80
TA = -55°C

60 VCC 60 VCC
- -
ADM DVO ADM DVO
40 40 TA = 125°C
+ +
VEE VEE
20 DVO/ADM
20 DVO/ADM
+PSR = 20Log -PSR = 20Log
DVCC DVEE
0 0
10 100 1.0 k 10 k 100 k 1 .0 M 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 14. Positive Power Supply Rejection Figure 15. Negative Power Supply Rejection
versus Frequency versus Frequency
SC OUTPUT SHORT CIRCUIT CURRENT (mA)

60 11
VCC = +15 V
VEE = -15 V 10 TA = +125°C
CC SUPPLY CURRENT (mA)
50
VID = ±1.0 V 9.0
Sink RL < 100 W TA = +25°C
40 8.0
Source Sink TA = -55°C
30 7.0
Source 6.0
20
5.0
I,

10
4.0
|I|,

0 3.0
-55 -25 0 25 50 75 100 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
TA, AMBIENT TEMPERATURE (°C) VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 16. Output Short Circuit Current Figure 17. Supply Current versus
versus Temperature Supply Voltage

1.15 50
GBW, GAIN BANDWIDTH PRODUCT (MHz)

VCC = +15 V
SR, SLEW RATE (NORMALIZED)

- VEE = -15 V
1.1 VO
+ 40 f = 100 kHz
DVin 2.0kW 100 pF RL = 2.0 kW
1.05 CL = 0 pF
30
1.0
VCC = +15 V 20
0.95 VEE = -15 V
DVin = 20 V
10
0.9

0.85 0
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 18. Normalized Slew Rate Figure 19. Gain Bandwidth Product
versus Temperature versus Temperature

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 MC33272A, MC33274A, NCV33272A, NCV33274A

25 80 25 80
20 100 20 100

φ, EXCESS PHASE (DEGREES)

Gain
15 120 15 120

φ, PHASE (DEGREES)
1A
A V, VOLTAGE GAIN (dB)

A V, VOLTAGE GAIN (dB)

140 TA = 25°C 140
10 Phase 10
CL = 0 pF
5.0 160 5.0 160
0 180 0 2A 180
-5.0 VCC = +15 V 200 -5.0 1B 200
-10 VEE = -15 V 220 -10 1A - Phase V = 18 V, V = -18 V 220
RL = 2.0 kW CC EE
-15 TA = 25°C 240 -15 2A - Phase VCC = 1.5 V, VEE = -1.5 V 2B 240
1B - Gain VCC = 18 V, VEE = -18 V
-20 260 -20 2B - Gain V = 1.5 V, V = -1.5 V
CC EE
-25 280 -25
100 k 1.0 M 10 M 100 M 100 k 1.0 M 10 M 100 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 20. Voltage Gain and Phase Figure 21. Gain and Phase
versus Frequency versus Frequency
VOL OPEN LOOP VOLTAGE GAIN (dB)

20 100 12 0
120 Gain Margin

m OPEN LOOP GAIN MARGIN (dB)

φ m, PHASE MARGIN (DEGREES)

10 10
10 140 φ EXCESS PHASE (DEGREES)
1A VCC = +15 V
160 VEE = -15 V
2A 8.0 20
180 VO = 0 V
0
VCC = +15 V 6.0 - 30
VEE = -15 V 200
1B Vin VO
-10 Vout = 0 V 220 +
TA = 25°C 4.0 2.0 kW CL 40
240
1A - Phase (RL = 2.0 kW) 2B
260
A,

-20 2A - Phase (RL = 2.0 kW, CL = 300 pF) 2.0 50

1B - Gain (RL = 2.0 kW)
A,

280
2B - Gain (RL = 2.0 kW, CL = 300 pF) Phase Margin
-30 0
3.0 4.0 6.0 8.0 10 20 30 1.0 10 100 1000
f, FREQUENCY (MHz) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Open Loop Voltage Gain and Figure 23. Open Loop Gain Margin and Phase
Phase versus Frequency Margin versus Output Load Capacitance

12 60
CL = 10 pF
m OPEN LOOP GAIN MARGIN (dB)

CL = 10 pF
φ m, PHASE MARGIN (DEGREES)

10 50
CL = 100 pF
8.0 CL = 100 pF 40 CL = 300 pF

6.0 CL = 300 pF 30
CL = 500 pF
4.0 CL = 500 pF 20

VCC = +15 V
A,

2.0 VCC = +15 V 10 VEE = -15 V

VEE = -15 V
0 0
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 24. Open Loop Gain Margin Figure 25. Phase Margin versus Temperature
versus Temperature

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 MC33272A, MC33274A, NCV33272A, NCV33274A

15 60 160
Gain Margin Driver Channel

CS, CHANNEL SEPERATION (dB)

φ m , PHASE MARGIN (DEGREES)
12 50 150 VCC = +15 V
VEE = -15 V
Phase Margin
m GAIN MARGIN (dB)

RL = 2.0 kW
9.0 40 140 DVOD = 20 Vpp
VCC = +15 V TA = 25°C
6.0 VEE = -15 V 30 130
RT = R1+R2
VO = 0 V
3.0 TA = 25°C 20 120
A,

-
0 R1 VO 10 110
Vin +
R2
0 100
1.0 10 100 1.0 k 10 k 100 1.0 k 10 k 100 k 1.0 M
RT, DIFFERENTIAL SOURCE RESISTANCE (W) f, FREQUENCY (Hz)
Figure 26. Phase Margin and Gain Margin Figure 27. Channel Separation
versus Differential Source Resistance versus Frequency

1.0 50
THD, TOTAL HARMONIC DISTORTION (%)

AV = +1000 VCC = +15 V

O OUTPUT IMPEDANCE ()

VEE = -15 V
Ω
AV = +100 40 VO = 0 V
TA = 25°C
0.1
30
AV = +10
AV = 1000
20
0.01
AV = +1.0 AV = 100
|Z|,

10 AV = 10 AV = 1.0
VO = 2.0 Vpp VCC = +15 V
TA = 25°C VEE = -15 V
0.001 0
10 100 1.0 k 10 k 100 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 28. Total Harmonic Distortion Figure 29. Output Impedance versus Frequency
versus Frequency
pA/ √ Hz )
nV/ √ Hz )

n INPUT REFERRED NOISE CURRENT (

50 2.0
n INPUT REFERRED NOISE VOLTAGE (

Input Noise Current Circuit

+ 1.8
40 VO 1.6 +
- RS VO
1.4 -

30 Input Noise Voltage 1.2

Test Circuit (RS = 10 kW)
1.0
20 0.8
0.6
VCC = +15 V
10 0.4 VCC = +15 V
VEE = -15 V
VEE = -15 V
TA = 25°C 0.2 TA = 25°C
0 0
10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k
i,
e,

f, FREQUENCY (Hz) f, FREQUENCY (Hz)

Figure 30. Input Referred Noise Voltage Figure 31. Input Referred Noise Current
versus Frequency versus Frequency

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 MC33272A, MC33274A, NCV33272A, NCV33274A

60
VCC = +15 V
VEE = -15 V
50

PERCENT OVERSHOOT (%)

RL = 2.0 kW
TA = 25°C
40

30

20

10

0
10 100 1000
CL, LOAD CAPACITANCE (pF)
Figure 32. Percent Overshoot versus
Load Capacitance
O OUTPUT VOLTAGE (5.0 V/DIV)

O OUTPUT VOLTAGE (5.0 V/DIV)

VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW CL = 100 pF
CL = 100 pF
TA = 25°C

VCC = +15 V
VEE = -15 V
AV = +1.0
RL = 2.0 kW
V,

V,

TA = 25°C CL = f

t, TIME (2.0 ms/DIV) t, TIME (2.0 ns/DIV)

Figure 33. Non−inverting Amplifier Slew Rate Figure 34. Non−inverting Amplifier Overshoot
for the MC33274 for the MC33274

VCC = +15 V
O OUTPUT VOLTAGE (50 mV/DIV)

VCC = +15 V
O OUTPUT VOLTAGE (5.0 V/DIV)

VEE = -15 V
VEE = -15 V AV = +1.0
AV = +1.0 RL = 2.0 kW
RL = 2.0 kW CL = 300 pF
CL = 300 pF TA = 25°C
TA = 25°C
V,

V,

t, TIME (2.0 ms/DIV) t, TIME (1.0 ms/DIV)

Figure 35. Small Signal Transient Response Figure 36. Large Signal Transient Response
for MC33274 for MC33274

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 MC33272A, MC33274A, NCV33272A, NCV33274A

ORDERING INFORMATION
Device Package Shipping†
MC33272AD SOIC−8
MC33272ADG SOIC−8 98 Units / Rail
(Pb−Free)

MC33272ADR2 SOIC−8
MC33272ADR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)

MC33272AP PDIP−8
MC33272APG PDIP−8 50 Units / Rail
(Pb−Free)

NCV33272ADR2* SOIC−8
NCV33272ADR2G* SOIC−8 2500 / Tape & Reel
(Pb−Free)

MC33274AD SOIC−14
MC33274ADG SOIC−14 55 Units / Rail
(Pb−Free)

MC33274ADR2 SOIC−14
MC33274ADR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC33274ADTBR2G TSSOP−14
(Pb−Free)

MC33274AP PDIP−14
MC33274APG PDIP−14 25 Units / Rail
(Pb−Free)

NCV33274AD* SOIC−14
NCV33274ADG* SOIC−14 55 Units / Rail
(Pb−Free)

NCV33274ADR2* SOIC−14
NCV33274ADR2G* SOIC−14
(Pb−Free) 2500 / Tape & Reel
NCV33274ADTBR2G* TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC33272A, MC33274A, NCV33272A, NCV33274A

PACKAGE DIMENSIONS

PDIP−8
P SUFFIX
CASE 626−05
ISSUE N

NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW

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 MC33272A, MC33274A, NCV33272A, NCV33274A

PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D A 2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
14 8 E AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
H 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
1 7 LEADS UNCONSTRAINED.
c
NOTE 8 b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
NOTE 5 CORNERS).
A2
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
NOTE 3
A −−−− 0.210 −−− 5.33
L A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.35 0.56
SEATING
PLANE b2 0.060 TYP 1.52 TYP
A1 C 0.008 0.014 0.20 0.36
C M D 0.735 0.775 18.67 19.69
D1 D1 0.005 −−−− 0.13 −−−
e eB E 0.300 0.325 7.62 8.26
END VIEW E1 0.240 0.280 6.10 7.11
14X b
e 0.100 BSC 2.54 BSC
NOTE 6
0.010 M C A M B M eB −−−− 0.430 −−− 10.92
SIDE VIEW L 0.115 0.150 2.92 3.81
M −−−− 10 ° −−− 10 °

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 MC33272A, MC33274A, NCV33272A, NCV33274A

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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14
 MC33272A, MC33274A, NCV33272A, NCV33274A

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
ISSUE K

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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15
 MC33272A, MC33274A, NCV33272A, NCV33274A

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K

ÉÉÉ
ÇÇÇ
MILLIMETERS INCHES
−V− K1 DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
J J1

ÇÇÇ
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE

SOLDERING FOOTPRINT
7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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16