European University of Bangladesh

Department of Electrical and Electronic Engineering (EEE)

Faculty of Engineering
Full Module Specification
Course Name Digital Logic Design
Course Code EEE- 302
Course Teacher Omar Saif, Lecturer, Dept. of EEE
Module Title/Topic Digital Logic Design
Module Number: 1 to 12
Module Duration: 1 week
Academic Year: 2018
Semester: Spring
Counseling Hour: Saturday, Sunday, Tuesday, Wednesday 9.00 am
to 2.00 pm and Thursday 2.00pm to 7 pm
Module Credit 3 Credit hours
Pre Requisites : Electronic Devices
Co Requisites : Digital Logic Design Lab
Grading : As outlined in the University policy
Teaching Methodology Class room lecture, Multimedia
Presentation ,Discussion, Group study,
Assignment, Class test, Viva voce etc.
Method of Evaluation Attendance = 20
Continuous Assessment = 20
Mid-term = 30
Final = 30
TOTAL = 100
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Course Contents:

Week Module Topics/Module/Chapter Quiz 1 after end of

Module 1  Introduction to various types week 2
1
of Numbering System
Module 2  Introduction to Digital
Design
2
Module 3  Universal Property of NAND
and NOR gate
Week Topics/Module/Chapter Quiz 3 after end of
Module 4  Boolean Operations and week 8
3
Expression
Module 5  Rules of Boolean Algebra
Module 6  Boolean Analysis of Logic Quiz 4 after end of
4
Circuits week 11.
Module 7  Standard Forms of Boolean
5
Expression
6 Module 8  The KARNAUGH MAP
Midterm
Module 9  Simplification using
7
KARNAUGH MAP
8 Module 10  Adders and Subtractors
9 Module 11  Decoder, Encoder, MUX and
10 DEMUX
11 Module 12  Latches and Flip flops
12

Final Exam
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 1
Number system:
A number can be represented with different base values. We are familiar with the numbers in the base
10 (known as decimal numbers), with digits taking values 0,1,2,…,8,9.
A computer uses a Binary number system which has a base 2 and digits can have only TWO values: 0
and 1. A decimal number with a few digits can be expressed in binary form using a large number of
digits. Thus the number 65 can be expressed in binary form as 1000001. The binary form can be
expressed more compactly by grouping 3 binary digits together to form an octal number. An octal
number with base 8 makes use of the EIGHT digits 0,1,2,3,4,5,6 and 7. A more compact
representation is used by Hexadecimal representation which groups 4 binary digits together. It can
make use of 16 digits, but since we have only 10 digits, the remaining 6 digits are made up of first 6
letters of the alphabet. Thus the hexadecimal base uses 0,1,2,….8,9,A,B,C,D,E,F as digits. To
summarize
Decimal: base 10
Binary: base 2
Octal: base 8
Hexadecimal: base 16

Decimal, Binary, Octal, and Hex Numbers

Conversion of binary to decimal ( base 2 to base 10)

Each position of binary digit can be repla`ced by an equivalent power of 2 as shown below.

Thus to convert any binary number replace each binary digit (bit) with its power and add up.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Example 1: convert (1011)2 to its decimal equivalent Represent the weight of each digit in the given
number using the above table.

Now add up all the powers after multiplying by the digit values, 0 or 1
(1011)2
= 23×1 + 22×0 + 21 × 1 + 20 × 1
=8+0+2+1
= (11)10

Conversion of decimal to binary (base 10 to base 2)

Here we keep on dividing the number by 2 recursively till it reduces to zero. Then we print the
remainders in reverse order.
Example 2: convert (68)10 to binary
Solution:

We stop here as the number has been reduced to zero and collect the remainders in reverse order.
Answer = (1 0 0 0 1 0 0)2

Conversion of binary fraction to decimal fraction

In a binary fraction, the position of each digit (bit) indicates its relative weight as was the
case with the integer part, except the weights to in the reverse direction. Thus after the
decimal point, the first digit (bit) has a weight of ½, the next one has a weight of 1/4,
followed by 1/8 and so on.
The decimal equivalent of this binary number 0.1011 can be worked out by considering
the weight of each bit. Thus in this case it turns out to be

= (1/21) × 1 + (1/22) ×0 + (1/23) × 1 + (1/24) × 1+ (1/25) × 0+ (1/26) × 0+ (1/27) × 0.

= (1/2) × 1 + (1/4) × 0 + (1/8) × 1 + (1/16) × 1+ (1/32) × 0 + (1/64) × 0+ (1/128) × 0.
= 0.5 + 0.125 + 0.0625
= 0.6875
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Conversion of decimal fraction to binary fraction
To convert a decimal fraction to its binary fraction, multiplication by 2 is carried out repetitively and
the integer part of the result is saved and placed after the decimal point.
The fractional part is taken and multiplied by 2. The process can be stopped any time after the desired
accuracy has been achieved.

Example: convert (0.68)10 to binary fraction.

0.68 * 2 = 1.36 integer part is 1
0.36 * 2 = 0.72 integer part is 0
0.72 * 2 = 1.44 integer part is 1
0.44 * 2 = 0.88 integer part is 0

The digits are placed in the order in which they are generated, and not in the reverse order. Let us say
we need the accuracy up to 4 decimal places. Here is the result.
Answer = 0. 1 0 1 0…..
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Binary Coded Decimal (BCD)

The conversion between decimal and binary can become very long and complicated for large
numbers. In BCD each digit of a decimal numbers represented by its binary equivalent.
For example:

Note: In BCD, 4 bits are always used for each decimal digit.
Note: BCD numbers are from decimal 0 to 9. From (0000) to (1001) are valid numbers for BCD

Decimal BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

For example of an invalid number in BCD: as (1100)2 is invalid in BCD it will show error value.

.
Advantage of BCD: conversion is easy and easy to handle
Disadvantages of BCD: Inefficient, uses more bits than straight binary coding.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Gray Number:
Gray Number Table:
Decimal Binary Gray
0 0000 000
1 0001 001
2 0010 011
3 0011 010
4 0100 110
5 0101 111
6 0110 101
7 0111 100

Note: a) for Binary to Gray conversion the MSB won‟t change.

b) MSB + Next bit = 2nd bit after MSB [for example shown above MSB=1,
2nd bit in Gray is 1+ 0(2nd bit in Binary) = 1 [2nd bit for Gray)

Example: convert (11101)2 to Gray numbers:

Solution: so (11101)2 = (10011) Gray
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Binary to gray Converter:
Binary code (of any length) is converted to a Gray Code, it‟s a simple process requiring EX-ORing of
2 bits & saving the resultant bit in a new place.
B(1), B(2), B(3) & B(4) collectively denotes the 4 bit binary, of which B(1) is the MSB. G(1), G(2),
G(3) & G(4) collectively denotes the 4 bit gray code.

Example: convert (10011)Gray to binary numbers:

Solution: So, (10011) Gray=(11101)2
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Gray to Binary Converter:

Possible Questions:
1. Write the octal decimal numbers and hexadecimal number from decimal number 0 to 15.
2. Convert the following binary numbers to decimal numbers:
a) (11100111)2
b) (011100111100)2
3. Convert the following binary values to decimal equivalent.
a) 0.110011 b) 0.111001
4. Convert the following decimal value to binary equivalent
a) 60
b) 0.635
c) (70.68)10
d) (825.042)10
5. Find the 1‟s and 2‟s complement of the following binary numbers
a) 1110011
b) 1010111001
6. Convert the following Decimal numbers to BCD:
a) 83 b) 285 c) 193 d) 683
7. Convert the following decimal number to Gray: a) 86 b) 25
8. Convert the following gray numbers to binary: a) 10101100 b) 1110011

End of Module 1
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 2
Digital Signal:
Digital Signal is the combination of discrete signal. A digital quantity is one having discrete sets of
values.
Advantages of Digital system:
 Digital data can be processed and transmitted more efficiently are reliably than analog data
 Digital data can be stored more compactly and reproduced with greater accuracy and clarity
than is possible when it is in analog form
 Noise does not affect digital data nearly as much as it does analog signals
Binary Digit:
The two digits in the binary system 1 and 0 are called bit which is a construction of the words
binary digit.
Introduction to Digital Design:
Digital electronics involves circuits and systems in which there are two possible states
These states are represented by two different voltage levels: A HIGH and a LOW voltage level.
Logic levels:
The voltage used to represent a “1” or a “0” are called logic level.
HIGH= Logic 1 ; LOW: Logic 0;
When on state ------ Logic 1 [Voltage level : 3.5- 5V]
When off state---- Logic 0 [Voltage level: 2.5 to 0v]
In between 2.5- 3.5 V is the Invalid state.
Logic Gates:
In most digital circuits logic gates are the fundamental building blocks from which all other logic
circuits and digital system are constructed. The logic circuits are the circuits which are used to
implement or perform logic functions. There are three types of Logic gates, they are:

1. Basic Logic Gate

a) NOT Gate
b) AND Gate
c) OR gate
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

2. Universal Logic Gate:

a) NAND Gate
b) NOR Gate
3. Exclusive logic gate
a) XOR Gate
b) XNOR Gate

Descriptions of Logic Gates:

Basic Logic Gates:
1. NOT GATE:
The “NOT” gate changes the input logic level to the opposite logic level i.e. inverts the logic level.

2. AND Gate:
The AND gate operation produces a HIGH output if and only if all the inputs are HIGH.

3. OR Gate:
The OR gate operation produces a HIGH output only when any of the inputs are HIGH.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

The Universal Gates:

1. NAND Gate:
“NAND gate is a “NOT-AND” gate. The NAND gate operation produces a LOW output only
when both the inputs are HIGH

2. NOR Gate:
NOR gate is “NOT-OR” gate. The NOR gate operation produces a HIGH Output only and only if
both the inputs are LOW.

Exclusive Gate:
1. XOR Gate:
The XOR gate operation produces HIGH output only when Inputs are at different logic levels.

2. XNOR Gate:
The XNOR gate operation produces HIGH output only when the inputs are at same logic
level.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible Questions:
1. What is digital signal? Write down the advantages of digital signal.
2. What is logic gate? Write down the names of different types of logic gates.
3. What are the basic logic gates? Write down the names with logic expression, logic symbol, and
truth table.
4. What are the universal and exclusive logic gates? Write down the names with logic expression,
logic symbol, and truth table.

End of Module 2
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Module 3
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible questions:
1) Design the following Boolean expression using only NAND gate:
a) AB+CD
b) AB+BC+AC
c) ̅̅̅̅
d) A ̅ ̅
2) Design the following Boolean expression using only NOR gate:
a) AB+CD
b) AB+BC+AC
c) ̅̅̅̅
d) A ̅ ̅
End of Module 3
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 4
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible Questions:
1. Write down the Laws of Boolean Algebra.
2 Write down the Rules of Boolean Algebra.
3. What do u understand of Boolean Addition and Multiplication.

End of Module 4
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 5

Prove of the rules of Boolean Algebra:

Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible Questions:
1. Prove the following expression with proper logic diagram and truth table:
a) A+AB=A
b) A+ ̅ =A+B
c) (A+B)(A+C)=A+BC
2. Use DeMorgan‟s Theorem to the following expression:

End of Module 5
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 6
Boolean Analysis of Logic Circuits:
A logic Circuit can be described by a Boolean expression:

So the Boolean expression for the logic circuit is A (B+CD).

Constructing Truth Table for the Logic Circuit:
Now from the Boolean Expression, It can be observed that the output will be HIGH (1) when A=1
and (B+CD) = 1; Now first finding the combinations when B+CD=1
Conditions B+CD=1:

So when A=1, B+CD=1 we get the high output for the corresponding logic gate and for the rest of
the combinations, A (B+CD) =0
Truth Table:
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Standard forms of Boolean Expression:

Two standard forms of Boolean Expression:
1. The Sum of Products (SOP) [minterm]
2. The Product of Sum (PSO) [maxterm]

Example of SOP: AB+BC+AC ; ABC+ ̅ ̅ ̅ ̅ ̅

Example of POS: (A+B+C)(A+ ̅ ̅ ) ; (A+B)(A+ ̅

Possible Question:
1. Simplify the following Boolean expression and draw the logic circuit for both the equations:
a) [A ̅ ( ̅̅
b) [ ̅ ̅ ( ̅̅
2. Find the truth table from the following Logic expression:
a) AB+BC
b) (A+B)(A+C)+CD

End of Module 6
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 7
Example: Converting the following Boolean Expression to SOP form: a) AB+B(C+DE+EF);
b) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(̅̅̅̅̅̅̅̅̅̅
Solution:
a) AB+B(C+DE+EF) = AB+BC+BDE+BEF [Ans.]
b) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
( = ̅̅̅̅̅̅̅̅̅̅
( .̅ [ ̅̅̅̅̅̅̅ ̅ ̅]
= (A+B). ̅
= ̅ ̅ [Ans.]
The Standard SOP form: ̅ ̅̅ ̅
Example: Convert the following Boolean Expression into standard SOP form. Also find the truth
table from the Standard SOP. Also fine the Standard POS equation it, ̅ ̅̅ ̅
Solution: ̅ ̅̅ ̅
= ̅ ( ̅ + ̅ ̅( ̅ ̅
= ̅ ̅ ̅ + ̅̅ ̅̅̅ ̅
= ̅ ̅ ̅ + ̅ ̅( ̅ ̅̅( ̅ ̅ ̅
= ̅ ̅ ̅ + ̅̅ ̅̅ ̅ ̅̅ ̅ ̅ ̅ ̅̅ ̅
Binary Representation of the SOP function is :
= ̅ ̅ ̅ + ̅̅ ̅̅ ̅ ̅̅ ̅ ̅ ̅ ̅̅ ̅
= 1011 1010 0011 0001 0010 0000 1101
In SOP, the standard terms shows a HIGH at output. so these combinations will so HIGH
output and the rest of the input combinations will show LOW output.

A B C D output
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
So the standard SOP can be represented by ∑ (0, 1, 2, 3, 10, 11, 13

Now converting to Standard POS, Y= π (4, 5, 6, 7, 8, 9, 12, 14, 15)

So Yπ = (A+ ̅ (A+ ̅+C+ ̅ ) (A+̅ + ̅ +D) (A+ ̅ + ̅ + ̅ ) ( ̅+B+C+D) ( ̅+B+C+ ̅ )
(̅+̅+C+D) ( ̅+̅+ ̅ +D) ( ̅+ ̅+ ̅ + ̅ )

EXAMPLE: Determine the Truth table from the following standard POS:
(A+B+C) (A+ ̅+ ̅ ) (A+̅+C) ( ̅+̅+C); Also find the truth table from the Standard POS. Also fine
the Standard SOP equation.

Solution:
Finding the truth table from the POS, as POS term shows Zero for output. So,
(A+B+C) (A+̅+ ̅ ) (A+̅+C) ( ̅ + ̅ (̅+̅+C)
000 0 1 1 0 1 0 1 0 1 1 1 0
Truth Table:
A B C Output
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

So, form the truth table, Standard SOP expression is: ̅ ̅C + A̅ ̅ + ABC

Possible Questions:
1. Converting the following Boolean Expression to SOP form:
a) ̅̅̅̅
( C) + (A+̅ ̅ + AB
b) ( ̅ ( ̅+C+ ̅ )(A+̅+D)
2. Convert the following Boolean Expression into standard SOP form. Also find the truth table
from the Standard SOP. Also fine the Standard POS equation,
̅ ̅̅ ̅ ̅ ̅̅ ̅
3. Determine the Truth table from the following standard POS:
( ̅ ( ̅+C+ ̅ )(A+̅+D); Also find the truth table from the Standard POS. Also fine the
Standard SOP equation.

End of Module 7
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 8
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible Questions:
1. Using Karnaugh map find out the simplified SOP expression from the given expression:

2. Using Karnaugh Map find out the simplified SOP expression from the given expression:
Y = ∑(0,5,7,8,10,13,15)

End of Module 8
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 9
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Possible Questions:
1. Using Karnaugh map find out the simplified POS expression from the given expression:

2. Using Karnaugh Map find out the simplified POS expression from the given expression:
Y = π (0, 5, 7, 8, 10, 13, 15)
3. Convert the following POS expression to Simplified SOP expression. :

Y= (A+ ̅ + C+ D) ( ̅ ̅ ) (A+ ̅ ̅ ̅ ) (A+̅ ̅ ) ( ̅+̅ ̅ )

( ̅+ ̅ ) (̅ + ̅ ̅)

End of Module 9
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 10
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Full Adder Circuit

Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

So,

D= + + +

=z( )+ ( )

=z( y) + (x y)

= ( y z
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Bo= + + +

=z( )+ (z + )

=z( y) +

Possible Questions:
1. Design a Half Adder with necessary truth table, Logic Diagram, and derive Equation of Sum
and Carry.
2. Design a full Adder with necessary truth table, Logic Diagram, and derive Equation of Sum
and Carry.
3. Design a Half Subtractor with necessary truth table, Logic Diagram, and derive Equation of
difference and borrow.
4. Design a full Subtractor with necessary truth table, Logic Diagram, and derive Equation of
difference and borrow.

End of Module 10
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 11

Decoders:
The basic function of a decoder is to detect the presence of a specified combination of bits (codes)
on its input and to indicate the presence of that code by a specified level.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Combination logic circuit (3 to 8 line decoder using 2 to 4 line decoder
with enable bit):
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

Encoder:
An encoder is a device or circuit that converts information or combination of bits to a simpler code
and form.

4 to 2 line encoder:
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block diagram of
4 to 2 Encoder is shown in the following figure.

At any time, only one of these 4 inputs can be „1‟ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below.

From Truth table, we can write the Boolean functions for each output as
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the four inputs with two
bits.

Octal to Binary Encoder:

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to binary
encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is shown in
the following figure.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

At any time, only one of these eight inputs can be „1‟ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.

From Truth table, we can write the Boolean functions for each output as
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Multiplexers:
Multiplexer is a combinational circuit that has maximum of 2n data inputs, „n‟ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines. Since there are „n‟ selection lines, there will be 2n possible combinations of zeros
and ones. So, each combination will select only one data input. Multiplexer is also called as Mux.

2-to-1 Multiplexer:
A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y.
Depends on the select signal, the output is connected to either of the inputs. Since there are two
input signals only two ways are possible to connect the inputs to the outputs, so one select is needed
to do these operations.

The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector switching the
inputs are produced at outputs, i.e., D0, D1 and are switched to the output for S=0 and S=1
respectively. Thus, the Boolean expression for the output becomes D0 when S=0 and output is D1
when S=1.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
From the truth table the Boolean expression of the output is given as

From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented using
logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR gate. When
the select line, S=0, the output of the upper AND gate is zero, but the lower AND gate is D0.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
4-to-1 Multiplexer:
A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0 and S1 and a
single output line Y. The select lines S1 and S2 select one of the four input lines to connect the
output line. The particular input combination on select lines selects one of input (D0 through D3) to
the output.

The truth table of a 4-to-1 multiplexer is shown below in which four inputs.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
To get the total data output from the multiplexer, all these product terms are to be summed and then
the final Boolean expression of this multiplexer is given as

From the above expression of the output, a 4-to-1 multiplexer can be implemented by using basic
logic gates. The below figure shows the logic circuit of 4:1 MUX which is implemented by four 3-
inputs AND gates, two 1-input NOT gates, and one 4-inputs OR gate.

Demultiplexers:
The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the
MUX, demux is a one-to-many circuit. With the use of a demultiplexer, the binary data can be
bypassed to one of its many output data lines. Demultiplexers are mainly used in Boolean function
generators and decoder circuits. Different input/output configuration demultiplexers are available in
the form of single integrated circuits (ICs).

1-to-2 Demultiplexer:
A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The signal on
the select line helps to switch the input to one of the two outputs. The figure below shows the block
diagram of a 1-to-2 demultiplexer with additional enable input.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
In the figure, there are only two possible ways to connect the input to output lines, thus only one
select signal is enough to do the demultiplexing operation. When the select input is low, then the
input will be passed to Y0 and if the select input is high then the input will be passed to Y1.

The truth table of a 1-to-2 demultiplexer is shown below in which the input is routed to Y0 and Y1
depends on the value of select input S. In the table output Y1 is active when the combination of
select line and input line are active high, i.e., S F = 11. Therefore, the output Y1 = SF and similarly
the output Y0 is equal to S .
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

From the above truth table, the logic diagram of this demultiplexer can be designed by using two
AND gates and one NOT gate as shown in below figure. When the select lines S=0, AND gate A1
is enabled while A2 is disabled.

1-to-4 Demultiplexer:
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four outputs (Y0
to Y3). The input data goes to any one of the four outputs at a given time for a particular
combination of select lines.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer

The truth table of this type of demultiplexer is given below. From the truth table it is clear that,
when S1=0 and S0= 0, the data input is connected to output Y0 and when S1= 0 and s0=1, then the
data input is connected to output Y1.

From the table, the output logic can be expressed as min terms and are given below.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by using four 3-
input AND gates and two NOT gates as shown in figure below. The two selection lines enable the
particular gate at a time.

Possible Questions:
1. Design a 2-to-4 or 3-to-8 line decoder with enable bit with proper diagrams and truth table.
2. Design a 3-to-8 line decoder using only 2-to-4 line decoders with enable bit.
3. Define the function of 4-to2 line encoder.
4. Design an octal to binary Encoder.
5. Define the functions of 4-to-1 line multiplexer or 1-to-4 line demultiplexer.

End of Module 11
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Module 12
Latches and Flip-Flops:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by
signals applied to one or more control inputs and will have one or two outputs. It is the basic
storage element in sequential logic. Flip-flops maintain their state indefinitely until an input pulse
called a trigger is received. When a trigger is received, the flip-flop outputs change state according
to defined rules and remain in those states until another trigger is received.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Some various types of Latches:

SR Latches:
An SR latch (Set/Reset) is an asynchronous device: it works independently of control signals and
relies only on the state of the S and R inputs. In the image we can see that an SR latch can be
created with two NOR gates that have a cross-feedback loop. SR latches can also be made from
NAND gates, but the inputs are swapped and negated. In this case, it is sometimes called an SR
latch.

Gated SR latch:
The gated SR latch is a simple extension of the SR latch which provides an Enable line which
must be driven high before data can be latched. Even though a control line is now required, the SR
latch is not synchronous, because the inputs can change the output even in the middle of an enable
pulse.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
D Latch:
The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that
removes the possibility of invalid input states. Since the gated SR latch allows us to latch the output
without using the S or R inputs, we can remove one of the inputs by driving both the Set and Reset
inputs with a complementary driver: we remove one input and automatically make it the inverse of
the remaining input.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
Types Of flip flop:
Some various types of flip-flop circuits are as follows:
-flop circuit

1. RS or SR flip flop:
“A circuit containing cross coupled connection, which is used to remain a memory state stable by
using asynchronous sequential circuits, is called direct-coupled or RS flip flop.” Each flip flop has
two inputs and two outputs. The inputs are denoted by R and S and outputs are denoted by Q and
Q‟. These circuits can be implemented through “NOR” and “NAND” gate.

Memory State:
In above circuit when two inputs are given as S=0 and R=0 then the memory remains stable.
Re-set state:
When inputs are given as S=0 and R=1, then the output comes Q=0 AND Q‟=1. (“WHEN Q‟
comes 1 this state is called RE-SET state”)
Set state:
When inputs are given as S=1 and R=0, then the output comes Q=1 AND Q‟=0. (“WHEN Q comes
1 this state is called SET state”)
Not allowed state:
When the outputs come against the inputs then this state is called not allowed.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
2. Clocked SR Circuit:
“A circuit which is used to remain a memory stable by using “clock signals” is called clocked SR
circuit.”
Clock Signal:
“Is used to perform any process in a circuit is called Clock signal.” Basically clock signals are
electrical pluses which are in the form of 1 or 0.
Note: A process is performed only when it is in the form of “1”
EXPLANATION OF Clocked SR Circuit:
Memory State:
In above circuit when two inputs are given as CLK=0, S=0 and R=0 then the memory remains
stable.
Re-set state:
When inputs are given as clk=1, S=0 and R=1, then the output comes Q=0 AND Q‟=1.
(“WHEN Q‟ comes 1 this state is called RE-SET state”)
Set state:
When inputs are given as cl1=1, S=1 and R=0, then the output comes Q=1 AND Q‟=0.
(“WHEN Q comes 1 this state is called SET state”)
Not allowed state:
When the outputs come against the inputs then this state is called not allowed.
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
3. D Flip-Flop:
A circuit which is used to remove Clocked SR Circuit‟s “not allowed state” more circuit‟s stability
is called D flip flop. A circuit using Inverter is basically a SR circuit, which reduces the no. of
inputs from two to one. It also called D-Latch. It is basically modification of SR clocked circuit by
using 5 gates. NAND gates 1 and 2 form a basic Flip-flop and gates 3 and 4 modify it into a clocked
RS flip-flop.

Explanation of D flip flop:

This circuit is being constructed by using “Inverter with R”.
Memory state:
When Cp=0 and D=don‟t care condition then memory stays stable.
Re-set state:
When inputs are given as Cp=1, D=0, then the output comes Q=0 AND Q‟=1.
(“WHEN Q‟ comes 1 this state is called RE-SET state”)
Set state:
When inputs are given as Cp=1, D=1, then the output comes Q=1 AND Q‟=0.
(“WHEN Q comes 1 this state is called SET state”)
Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
4. JK Flip-Flop:
“A JK flip-flop is a refinement of RS flip-flop circuit in that the determinate state of RS type is
defined in the JK type. Means J and K behave like S and R to set and clear the flip-flop.”
Note: The letter j is used for set and the letter K is used for Reset.
Note: It is also used for removing not allowed state for memory state.
A clocked JK flip-flop circuit is shown in the bellow diagram.

Working principle of JK flip-flop:

Memory state:

When Clk=0 and J and K=don‟t care conditions then memory stays stable.

When Clk=1 and both J and K are 0, then memory also stays stable.

Set state:

When inputs are given as Clk=1 and J=1 and K=0, then the output comes Q=1 AND Q‟=0.

(“WHEN Q comes 1 this state is called SET state”)

Re-set state:

When inputs are given as Clk=1 and J=0 and K=1, then the output comes Q=0 and Q‟=1.

(“WHEN Q‟ comes 1 this state is called RESET state”)

Digital Logic Design [EEE-302] Prepared by: Omar Saif, Lecturer
5. T-Flip Flops:
The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the
frequency of the signal to the T input. It is useful for constructing binary counters, frequency
dividers, and general binary addition devices. It can be made from a J-K flip-flop. The T flip-flop
can be constructed using a D flip-flop with the two outputs Q and Q' feedback to the D input
through a multiplexer that is controlled by the T input as shown in Figure

Possible Questions:
1. Write down the difference between latches and flip flops.
2. Explain different types of lathes with circuit diagram.
3. What is clock signal?
4. Explain the function of different types of flip flops.

Reference Book:

1. Thomas L. Floyd, “Digital Fundamentals” 9th edition, Prentice Hall

2. M.Morris Mano, “ Digital Logic and Computer design” 4th edition Prentice Hall

End of Module 12