simplifying Learning

CM O S I C L ay o u t D e s i g n C o u r s e O u t l i n e
To proliferate the cutting edge technologies to Indian Engineers
with detailed overview, imparting in-depth skills to make Indian
engineers ready for tomorrow’s Semiconductor Industry.

Tr a i n i n g o n
CMOS IC
Layout
Design

At XXXXXXXXX
Team is highly skilled at :

 CMOS Layout
 Analog Layout
 Standard Cell Layout Design
 Memory Layout technology
consulting
 Physical Design
 Physical Verification
 STA etc .,. technology
5432 Any Street West co n s u l t i n g
Townsville, State 54321
555.543.5432 ph
555.543.5433 fax
www.yourwebsitehere.com
 Training solutions that work for your Career Development.
N U R T U R I N G M I N D S T O G R E AT TA L E N T S - R E A D Y F O R C O R E S E M I C O N I N D U S T R Y

Accumsan epulae accumsan inhibeo dolore populus praesent.

Molior vicis feugiat valetudo quadrum quidem C US TO M S O L U T I O N S
nisl ea paulatim lorem ipsumes. Enim iriure accumsan epulae accumsan inhibeo
dolore populus praesent. Molior vicis feugiat

flexible training model for today’s engineers valetudo quadrum quidem nisl ea paulatim.

on Custom IC Layout Design W E B S O L UT I O NS

T RA I NI NG SO LU TI O NS Vulputate iaceo, volutpat eum mara ut
C O U RS E O U TL I N E E N TE RP R I S E M A N A G E M E NT
• CMOS CUSTOM LAYOUT. Course structure involves revisiting the topics accumsan nutus. Aliquip exputo abluo, aliquam
Uxor iaceo at minim letatio lenis esca abluo.
needed for impoving the skill-set required for suscipit euismod te tristique volutpat immitto
Sed sed dolore esca similis vel esse iriure,
• PHYSICAL DESIGN.
entering core semiconductor industry. voco. Torqueo, qui lorem ipso utinam immitto
lenis utinam adsum indoles, esca. Cui
• DESIGN VERIFICATION. vero sino lorem dolor ipso.
appellatio facilisi, aliquip capto vel regula
Revisit the basics of Electronics gemino luptatum singularis vero, elit, cui,
• PHYSICAL VERIFICATION
Electric Circuits Basics suscipit. Nimis nisl eros ulciscor volutpat vel. E B U S I NE S S S O L U T I O N S
. Basic MOSFET Working Ullamcorper in ille consequat, quis, jugis Vulputate iaceo, volutpat eum mara ut
CMOS Inverter Design dolore tego venio similis tincidunt abluo capi. accumsan nutus. Aliquip exputo abluo, aliquam
CMOS Fabrication Process Flow Jus, at eu acsi, abbas letatio ut eum odi. suscipit euismod te tristique volutpat immitto
IC Design Flow voco. Torqueo, qui lorem ipso utinam immitto
Custom Layout Considerations vero sino valle mitra espa nillan.
CMOS Failure Mechanisms
Project 1 : Design Standard Cell Library
Analog Layout Concepts
Project 2 : Design an OTA
Project 3 : Implementation of Comparator

W E ’ V E W O R K E D W I T H A DI V E R S E C U S TO ME R B A S E. H O W C A N W E H E L P Y O U ?
At Dolore ut bene ratis duis gilvus jugis hendrerit suscipit regula populus. Quae ludus os qui eu, gemino aliquip conventio.