Power Electronics Drives U2

UNIT 2 i
Semiconductor power devices
Unit 2
TEL 202/05
Power Electronics and Drives
Semiconductor
Power Devices
ii WAWASAN OPEN UNIVERSITY
TEL 202/05 Power Electronics and Drives
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Dr. Magdalene Goh Wan Ching
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Associate Professor Cheong Kuan Yew, Universiti Sains Malaysia
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UNIT 2 iii
Contents
Unit 2 Semiconductor Power
Devices
Unit overview 1
Unit objectives 1
2.1 Power devices 3
Objectives 3
Introduction 3
Power diodes 3
Breakdown voltage 5
Depletion layer boundary control 7
Conductivity modulation 8
Current-voltage characteristic 9
Switching characteristic 11
Insulated gate bipolar junction transistor 13

Characteristic of IGBT 13
MOS-controlled thyristor 16
Turn-on and turn off of MCT 18
Switching time of MCT 18
Power MOSFET 19
Current-voltage characteristic 21
Switching characteristic 23
Other power MOSFET structures 28
Silicon carbide power MOSFETS 29
Static-induction transistor 30
Suggested answers to activities 32

iv WAWASAN OPEN UNIVERSITY
2.2 Thyristor 33
Objectives 33
Introduction 33
Shockley diode 34
Operation 35
Silicon-controlled rectifier 38
On-off control of current 42
Half-wave power control 43
Lighting system to power interruptions 44
Silicon-controlled switch 45
DIAC and TRIAC 47

DIAC 47
TRIAC 49
Suggested answers to activities 53
Summary of Unit 2 55
Suggested answers to self-tests 57
References 61
Glossary 63
UNIT 2 1
Unit Overview
In this unit on semiconductor devices, you will learn two main sections which are
power device and thyristor. In each topic, you need to study and achieve what have
been specified in the learning objectives via tutorials, learning activities and self-tests.
In section one on power devices, you will learn and achieve the ability and confidence
to distinguish the difference between a power device and a normal small signal
amplifier device; describe different types of power devices; describe the dc and
switching characteristics of power diode, insulated gate bipolar junction transistor,
power MOSFET, and silicon carbide power device; and study the other configuration
of power MOSFETs for solving turn-on resistance issue.
Unit Objectives
By the end of Unit 2, you should be able to:
1. Distinguish the difference between a power device and a normal small signal
amplifier device.
2. Describe different types of power devices.
3. Describe a thyristor being a four-layer device.
4. Distinguish different types of thyristor devices such as Shockley diode,

silicon-controlled rectifier, DIAC and TRIAC devices.
5. Use thyristor device in power control circuit design.

2 WAWASAN OPEN UNIVERSITY
UNIT 2 3
2.1 Power Devices

Objectives
By the end of this section, you should be able to:
1. Distinguish the difference between a power device and a normal small signal
amplifier device.
2. Describe different types of power devices.
3. Describe dc and switching characteristics of a power diode, an insulated

gate bipolar junction transistor, a power MOSFET, and a silicon carbide
power device.
4. Solve turn-on resistance issue of power MOSFETs with other configurations.
Introduction
A small piece of silicon chip measuring 5.0 mm × 4.3 mm can be used to fabricate
a power device capable of handling 70 A current and 100 V blocking voltage
or designed to handle 6,500 V blocking voltage and 1,000 A current. These are
achievable via the bipolar technology in the insulated gate bipolar junction transistor
and MOS technology in power vertical MOSFET device.
Power devices including diodes, have more complicated structure, operation and
characteristics than their low power version of devices. The complication comes
from the modification of the low power version of device in such that the diode is
made suitable for high power applications. The modification is essentially generic
in nature, which contains an additional drift layer of certain pre-defined thickness
to the low power version device's structure.
Power diodes
The design structure of a pn power diode is shown in Figure 2.1. Unlike the low
power diode, there is an additional drift layer or at time called epitaxial layer or epi.
The reason it is being called epitaxial layer is because it is a doped crystalline silicon
layer being added on top of n+ substrate layer (cathode) using epitaxial fabrication
process. The thickness (Wd) of this layer will determine the breakdown voltage (VB)
of the diode. However, too thick the epitaxial level would end with too much power
dissipation, which is not good for the diode. The cross sectional area of the diode
will determine the amount of carrying current. Power diode that has cross sectional
area of several square centimeters can carry several thousand amperes of current.
The current-voltage (I-V) characteristic of a power diode is more or less the same
as its low power counterpart except that at the forward bias region, the current
grows linearly rather than exponentially. The large current in a power diode creates
Ohmic drop in epitaxial layer that has masked the exponential current-voltage
characteristic of the diode. Figure 2.2 shows the I-V characteristics of a power diode.
VB denotes the breakdown voltage and its switch on voltage (threshold voltage) is
approximately 1.0 V.
Anode
oxide oxide
p+ 10µm
n− epitaxial Wd
n+ substrate 250µm
Cathode
Figure 2.1 Power diode made from pn junction
1
Ron
VB
V
1.0V
Figure 2.2 The current-voltage characteristics of a pn junction power diode
The epitaxial layer is a lightly doped n− type layer. It has doping concentration lower
than the p+ anode layer or n+ cathode layer. The gradient of I-V characteristics curve is
the conductance of the diode, which is the inverse of turn-on resistance of the diode.
UNIT 2 5
Activity 2.1
What is the difference between a low power and high power diode?
Breakdown voltage
Let's discuss the breakdown voltage (VB) of power diode. There are basically two
types of breakdown voltage (VB) to be considered for the power diode, which are
non-punchthrough and punchthrough breakdown voltages.
For non-punchthrough type of breakdown, the depletion thickness of breakdown

is thinner than the width (Wd) of the drift layer. After ignoring the small value
built-in potential (Vbi) and applying the assumption that the doping concentration
of drift layer is much less than the p+ layer, the breakdown voltage (VB) shall follow
equation (2.1), which is
e SE 2Crit
VB = (2.1)
2qND
where Ecrit is critical electric field of breakdown, which is depending on the doping
concentration, type of pn junction, and semiconductor material. Take for example,
if the doping concentration of a silicon abrupt junction is 1014cm−3, the critical
electric field of breakdown is 2.8 × 105 V/cm. ND is the doping concentration of
drift layer, in which it is usually in the order of 1014cm−3. eS is the permittivity of
semiconductor. q is electronic charge that has value 1.602 × 10−19 C.
For punchthrough breakdown type, the depletion thickness of breakdown extends

to cover the width (Wd) of the drift layer. At this breakdown condition, further
applying the reverse voltage would not cause the depletion to further increase
because the large doping concentration in n+ layer effectively blocks further growth
of the depletion layer. As shown in Figure 2.3 (b), the electric field profile across the
n− epi drift layer can be represented into two portions, one before punchthrough
as E2 and one after punchthrough as E1. Before punchthrough, the electrical field
is constant throughout the n− epi drift layer and after punchthrough, the electrical
field is linearly decreased from the p+ side to n+ side of the power diode.
Wd
n− epi
p+ n+
or drift region
(a) Profile of power diode
Electric
Field
E1
E2
x
0 Wd
(b) Electric field profile of power diode at non-punchthrough and

punchthrough conditions
Figure 2.3
For the case of depletion width is beyond the thickness of drift layer, the electric
field E1 component causes ionization of donor carrier in drift layer. Thus, it follows
Poisson’s equation whereby the maximum electric field occurred at p+ side i.e., at x
= 0 and it is equal to
qNDWd
E1 = (2.2)
eS
where ND is the doping concentration of drift layer and eS is the permittivity of

silicon. The electrical potential (V1) in this electric field (E1) is equal to area of the
qNDW 2d
triangle, which is equal to V1 = . The electrical potential (V2) is the area of
2eS
rectangle, which is V2 = E2Wd.
When the power diode junction having both breakdown and punchthrough, the
critical electric field Ecrit = E1 + E2 and the breakdown voltage VB is equal sum of V1
and V2. Substituting E2 = Ecrit − E1 into V2 = E2Wd, then V2 = (Ecrit − E1)Wd.
qNDW 2d
VB = EcritWd − E1Wd + (2.3)
2eS
qNDW 2d
= EcritWd −
2eS
UNIT 2 7
The high resistivity of drift layer of the punchthrough structure has no significant
effect on the operation of the diode because conductivity modulation that occurs
during on-state operation short out the n− epi drift layer. The shorter drift region
permits lower on-state voltage as compared with the non-punchthrough type of
same breakdown voltage and carrier lifetime.
Depletion layer boundary control
During the diffusion process of fabrication step, the lateral diffusion is faster than the
vertical diffusion, thus, the curvature of the doped anode can be extended under the
isolation whereby it will reduce the breakdown voltage of the diode if the curvature
is too small. Experiment study done using a cylindrical pn diode has shown that if
the radius of the curvature is less than six times the thickness of the depletion layer,
the breakdown voltage of the diode will be reduced. The reduction in breakdown
is caused by the electrical field in depletion thickness near the curvature becomes
spatially non-uniform and has largest magnitude where the radius of curvature is the
smallest. We shall discuss two approaches that are used to overcome this problem.
A method used to control the radius of the curvature is via the use of electrically
floating field plates shown in Figure 2.4. The field plates act as an equi-potential
surface. By proper placement, they can redirect the electric field lines and prevent
the radius of depletion layer from getting too small.
Field plates
Depletion region
p+
Depletion region
n− epi
Figure 2.4 Use of field plates to control the depletion layer boundary
Another method to control the depletion layer is the use of guard ring as shown in
Figure 2.5. The depletion layers of the guard rings merge with the growing depletion
layer of the reverse biased pn junction, which prevent the radius of the curvature
from getting too small.
Guard ring Guard ring
p p
p+
Depletion region
n− epi
Figure 2.5 A pn junction using p-type guard rings to improve the breakdown voltage
Conductivity modulation
When the power diode is in forward bias mode, power is dissipated in the low
conductivity n− epi drift layer. However, during “on state”, the conductivity of the
drift layer is modulated to a value, which is much higher than the value when it is
not in “on state”. This is due to high injection of excess minority carrier into the
drift layer, both from the p+ anode into drift layer and attraction of electron from
n+ cathode. The high injection of the carrier such that the change in hole doping
concentration (δp) is much higher than the not on-state doping concentration of
n− epi layer (nno) i.e., δp >> nno, can increase the doping concentration in n− epi drift
layer from the order of 1014cm−3 to 1016cm−3. This scenario will happen if the width
(Wd) of n− epi drift layer is shorter than the diffusion length of the minority carrier,
which is hole in this case. This would effectively reduce the resistance of the n− epi
drift layer. Thus, it reduces the power dissipation. Figure 2.6 shows the doping
profile of the power diode during forward bias mode. The doping concentration
of the n− epi drift layer has been changed from nno to approximately equal to Na.
n− n+
p+
p(x) = n(x)
= Na = 1016 cm−3
nno = 1014 cm−3

np(x)
Pno = 106 cm−3 Pn(x)
npo Pno
Wd x
Figure 2.6 The doping profile of power diode during forward bias
UNIT 2 9
Activity 2.2
State the reason why the conductivity of epi-layer of the power diode
becomes higher during the operation of power diode.
Current-voltage characteristic
The current in the n− epi region during the forward bias mode shall follow equation
(2.4).
q(µ n + µ p)NaAVd
In−epi ≈ (2.4)
Wd
where Vd is the voltage across the n− epi drift layer. µn and µp are the mobility of
electron and hole respectively. Na is the modulated doping concentration of hole.
A is the cross sectional area. This current (In−epi) is approximately equal to the rate
of excess carrier charge injected into n− epi layer, which is
qAWdNa Q−
In−epi ≈ ≈ n epi (2.5)
t t
where t is the average diffusion time of the excess carrier. Equating equations (2.4)
and (2.5), it yields equation for voltage across the n− epi layer (Vd), which is
W 2d
Vd ≈ (2.6)
(µn + µp)t
where µn and µp are respectively equal to the mobility of electron and hole.
Combining equation of the normal diode I-V equation with equation (2.4), would
yield the I-V characteristic equation for the power diode. The total voltage drop
across the diode is Vp_diode = VR + Vd.
If the doping concentration (Na) of drift region is greater than Nb = 1017 cm−3, the
doping concentration of n+ region, Auger recombination, which states diffusion time
t0
equal to t = would reduce the lifetime t of diffusion. This would
1 + (δp)
2
Nb
subsequently increase the voltage drop across the drift region. As the injected carrier
density is approaching Nb, the mobility of the carrier is also greatly reduced due to
more scattering effect, which follows equation (2.7).
µ0
mn + mp = (2.7)
NA
1+
NB
t0
Substituting equation t = into equation (2.5), it would yield current
(δp)
1+
2
Nb
density (Jn−ep) in equation (2.8).
Jn−ep =
In− epi
A
=
qAWdNa
t0
N2
1 + 2a
Nb ( ) (2.8)
Substituting equation (2.8) into equation (2.4) would yield
( )( )
2
Jn− epiWd W 2d J2n− epiW 4d
Vd + Vd − = (2.9)
qµ 0N b µ 0t 0 q 2µ 30N 2bt 0
As the concentration in the drift region Na approaches Nb, which is in order of 1017
cm−3, voltage drop across the drift region (Vd) will become larger than the term
W 2d
so that Vd can be approximately equal to
µ 0t 0
3
J− W 4
√
Jn− epiWd
Vd ≈ + 2n epi3 2 d (2.10)
qµ 0N b q µ 0N bt 0
As shown in equations (2.4) and (2.10), for large current, the drift region is Ohmic
like the voltage drop across. Thus, the voltage drops across the power diode can be
equal to
Vp_diode = VR + RonI (2.11)
where I is the current flows in the diode.
Analysis on the I-V characteristic so far has indicated several factors determining
losses in the turn-on state losses. If the diffusion time of the minority carrier can be
made large so that the diffusion length is compatible with the width (Wd) of the n−
epi drift layer then the voltage drop across drift (Vd) can be small and independent
of the current. Larger breakdown voltage (VB) requires larger width (Wd). However,
UNIT 2 11
the turn-on loss of a bipolar device can be estimated from the current density that
can flow in the drift region of the device as the function of breakdown voltage
(VB). From equation (2.1) and the maximum electric field at junction, which is
qNDWBreak
Ecrit = , and width of breakdown (Wbreak) in equation (2.12) can be
eS
obtained.
2VB
WBreak = (2.12)
ECrit
When breakdown occurs, WBreak is equal to Wd. Substituting equation (2.12) into
equation (2.4), it would yield minority current density J(minority) as in equation (2.13).

q(µ n + µ p)Na Vd ECrit
J(minority) ≈ (2.13)
2VB
Likewise, the majority current density J(majority) in the n− epi drift region is equal to
qµ nNDVd
J(majority) = (2.14)
Wd
Taking WBreak as equal to Wd in equation (2.12) and substitute it with equation

(2.1) for ND into equation (2.14), it would yield breakdown voltage (Vd), which is
e SE2Crit
VB =
2qND
µ ne SVd E 3Crit
J(majority) = (2.15)
4V 2B
Equations (2.13) and (2.15) show that as the breakdown voltage (VB) increases, the
current carrying density decreases. However, majority carrier device like MOSFET
suffers more than minority carrier device like bipolar junction transistor. This is
also the reason why bipolar junction transistor is used as the choice for large block
voltage device.
Switching characteristic
Since power device is a high current device, the switching characteristic shall be the
rate of change voltage dV/dt with response to the rate of change of current dI/dt.
Its timing diagram is shown in Figure 2.7.
There are four portions of the diagram that need to be discussed. As soon as the
diode is switched from reverse bias to forward bias mode, the large depletion layer
begins to collapse. Soon after the discharge, at the beginning of timing portion t1,
the majority carrier injection across the junction begins. There is an overshoot of
the voltage during time frame t2. This is because the large voltage drop across the
non-conductivity modulated drift region and inductance of wire. As soon as the

conductivity of the drift region is modulated, the forward voltage drop across the
diode shall be Von.
diF diR
Irrtrr
dt IF dt Qrr =
2
0.25 Irr
0 time
Irr
t3 t4 t5
VFP
trr
Von
0 time
VR
Vrr
−VR t5
S=
t1 t2 t4
Figure 2.7 Timing diagram of a power diode
During the transition from forward bias mode to reverse bias mode i.e., when diR/dt
is negative, at time frame t3, the excess minority carrier has to be annihilated. As long
as there is excess carrier in drift region and due to small ohmic change, the voltage
of the diode drops slightly at this time frame. Time frame t4 and t5 is time reverse
recovery time. When the current turns negative, the excess carrier sweep out proceed
for a time t4, which is called storage time until the junction becomes reverse biased.
At this time, the diode voltage goes negative and rapidly acquires substantial value
as the depletion region from the junction expands into the drift region toward each
other. At this time, the negative diode current demanded by the stray inductance
of the external circuit cannot be supported by the excess carrier because there are
too few remains. From the time frame t5, the diode current ceased to become zero.
The sum of time interval t4 and t5 is termed as reverse recovery time (trr). This is an
important parameter of diode. Other specifications usually mentioned for diodes
are reverse recovery time (trr) charge Qrr and S factor - snappiness, which is defined
as the ratio of t5 and t4 time. From Figure 2.7, the reverse recovery current can be
written as
diR di t
Irr = t4 = R · rr (2.16)
dt dt S + 1
UNIT 2 13
Insulated gate bipolar junction transistor

Insulated gate bipolar junction transistor (IGBT) comes from its operation based on
an internal interaction between an insulated gate field effect transistor and a bipolar
junction transistor. The structure, both the vertical and lateral structures of IGBT
are shown in Figure 2.8. IGBT can be viewed as a silicon control rectifier (SCR)
with a MOSFET connecting the cathode n+ region and to n− base. It can also be
viewed as a dual MOS transistor with additional pn junction with the drain region.
Gate Gate
Metal or
Cathode Poly Si Cathode Anode
Metal
Contact Gate Oxide
n+ n+
p−
p p xn
xn
n− n−
p− substrate p
Anode
(a) Vertical structure (b) Lateral structure of an n-channel IGBT
Figure 2.8
Characteristic of IGBT
The bulk of the device is the n− layer, which is the drain of the dual MOS (DMOS)
transistor, as well as the base of the pnp bipolar transistor. It is lightly doped and is
wide in order to support a large blocking voltage. Like the case of power diode, its
conductivity is modulated by injection of majority carrier during biasing. This is
the reason why the device is at time named as conductivity modulated field effect
transistor (COMFET). The characteristic of IGBT is shown in Figure 2.9.
IA
p-i-n
pnp transistor
VG > 0
VAK = breakdown
VG = 0
VAK = 0
Figure 2.9 Output characteristic of an n-channel IGBT
The characteristic can be divided into three modes. When the voltage drop between
anode and cathode (VAK) is between 0.0 V to 0.7 V of emitter-base voltage, the
IGBT can be represented by DMOS transistor in series with a p-i-n diode, which
is shown in Figure 2.10.
Anode
p-i-n
Gate
MOSFET
Cathode
Figure 2.10 Equivalent circuit of n-channel IGBT at VAK between 0.0 V to 0.7 V
UNIT 2 15
In this mode the voltage drop cross the DMOS is negligible, the p-i-n diode is under
forward bias and the current conduction is via recombination of excess carrier and
hole in n−-region. Thus, the anode current (IA) follows as
IA ≈
4AqniDa
xn
exp
2KT( )
qVAK
(2.17)
where k is Boltzmann constant and Xn is the depletion thickness in the channel. Da

is ambipolar diffusion coefficient which is defined as
2DpDn
Da ≈ (2.18)
Dp + Dn
The characteristic of mode is shown in the linear region of Figure 2.9.
The second mode is when voltage drop across anode and cathode VAK is more than
0.7 V. The mode is represented by the equivalent pnp transistor circuit shown in
Figure 2.11(a). Figure 2.11(b) shows the equivalent circuit IGBT comprising the
parasitic thyristor.
Cathode Cathode
Body
spread
Ih resistance
Gate Gate
JMOS npn IMOS
Ih
MOSFET MOSFET
pnp pnp
Drift Drift
resistance resistance
IA IA
Anode Anode
(a) (b)
Figure 2.11 Equivalent circuit of pnp transistor mode of IGBT
The characteristic of this mode represents the characteristic of a pnp bipolar junction
when the gate voltage (VG) determines the base current. Thus, the anode current
(IA) can be represented by equation (2.19).
IA = (1 + b)IMOS (2.19)
Where b is the current gain and IMOS is the MOS current. Since the dimension of
the base is large which is n−-region, the beta value of the pnp transistor is small and
the base transport factor B can be approximated as equal to current gain a which
is approximately equal to
1
a≈B≈ (2.20)
cosh
() Wb
Ln
B is the base transport factor, a is the current gain, and Ln is the diffusion length
of minority electron.
The third mode is pnpn with gate voltage VG = 0. When the anode-cathode voltage
is larger than the breakover voltage, the characteristic latches onto a low-resistance
state, similar to that of the silicon controlled rectifier (SCR).
Activity 2.3
Describe how an IGBT can be switched-on?
MOS-controlled thyristor
MOS-controlled thyristor (MCT) was a device invented by Harris Semiconductor. It
is a thyristor with two MOSFETs built into the gate structure with one MOSFFET
used to turn the device called ON-FET and one used to turn-off the device called
OFF-FET. There are two types of MCT namely p-channel MCT and n-channel
MCT. p-channel MCT has the ON p-channel, whilst n-channel MCT has the
ON n-channel. MCT has the combine characteristic of low on-state losses and
large current capability of thyristor with the fast switching speed of MOSFET
for turning-on and turning-off. The cross sectional view of the p-channel MCT is
shown in Figure 2.12.
UNIT 2 17
Anode
SiO2 SiO2
Gate Gate
ON-FET n +
n + ON-FET
OFF-FET p+ OFF-FET
p p
p−
n+
Cathode
Figure 2.12 Cross sectional view of a p-channel MOS-controlled thyristor
The complete p-channel MCT or n-channel MCT is usually composed of many

thousands of the small MCT structure fabricated on the same silicon wafer and all
the MCT structures are connected in parallel.
The equivalent circuit of p-channel MCT is shown in Figure 2.13. It has a pnpn
thyristor, an n-channel OFF-MOSFET and p-channel ON-MOSFET.
Anode
Gate
OFF-MOSFET pnp ON-MOSFET
npn
Cathode
Figure 2.13 Equivalent circuit of p-channel MOS-controlled thyristor
MCT has the characteristic similar to the gate of thyristor GTO (gate turn off )
which resembles the characteristic of silicon controlled retifier SCR.
GTO has anpn >> apnp which shall mean it has thicker n-base or incoporates an
anode-to-base short to reduce apnp. The characteristic curve is shown in Figure 2.14.
IA
Forward
Conducting
Region
IH
VAK
VH VBR(F)
Reverse Forward
Blocking Blocking
Region Region
Figure 2.14 Characteristic curve of p-channel MOS-controlled thyristor
Turn-on and turn off of MCT
When the gate voltage is positive, the n-channel OFF-MOSFET is in inversion mode
whilst the p-channel ON-MOSFET in accumulation mode. Thus, the thyristor is
switched off. When the gate voltage is negative, the n-channel OFF-MOSFET is
in accumulation mode whilst the p-channel ON-MOSFET is in inversion mode.
Thus, the thyristor is switched on.
During switch off means the n-channel OFF-MOSFET is conducting. To ensure

that the thyristor is in off mode, the voltage drop between the drain and source of
the n-channel OFF-MOSFET should be less than 0.7 V, which is the emitter-to-
base forward voltage of pnp transistor. Otherwise, latch-up would occur that would
damage the thyristor due to high anode-to-cathode voltage difference.
Activity 2.4
What is the purpose of ON-FET and OFF-FET of a p-MCT device?
Switching time of MCT
The MCT can switch quite rapidly from off to on and from on to off with typical
switching of approximately 1.0 µs. The switching time for n-channel MCT is shown
in Figure 2.15.
UNIT 2 19
Gate-Cathode
Voltage
V Tn
time
V TP
tdoff
Gate-Cathode
Voltage
time
tfi
Anode
Current
tA
tri
10%
time
tdon
Figure 2.15 Switching waveform of an n-channel MCT
Two switching times are used to characterise the turn-on waveform of MCT. The
turn-on time (tdon) is basically set by how fast substantial injection of excess carriers
into the bases of the transistors can occur. Once there are substantial numbers of
excess carrier in the base regions, the regenerative action of thyristor can begin.
Towards the end turn-on delay time (tdon), the anode current rises rapidly. The time
taken to reach maximum anode current is termed rise time (tri). The turn-off of the
MCT has the typical characteristic of a hard-switched device and the waveforms are
characterised by turn-off delay time (tdoff ) and current fall time (tf i).
Power MOSFET
Power MOSFET has the vertically oriented four-layer structure of alternating p-type
and n-type layer as shown in Figure 2.16. It has a double diffused p-body regions,
heavily doped source and drain regions, and epitaxial drift layer that determine the
reverse breakdown voltage. An applicable power MOSFET is doped with many
thousands of this device structure connected parallel on the silicon wafer.
Gate Polysilicon
Oxide Gate Source metal
Source
n+ n+
p p
p Well
+
p+ Well
n− Epi layer
n+ substrate
Drain metal
Drain
Figure 2.16 An n-channel power vertical diffusion MOSFET structure
It has two parasitic components, which are a bipolar junction transistor and diode,
which can be used as the half bridge and full bridge converter. The bipolar junction
transistor is formed from n+-source-p-body-n−-epi layer, whilst the diode is formed
from p+-well-n−-epi/n+-drain. There is also a parasitic JFET formed between p-body
and n−-epi. To prevent switching-on of the parasitic bipolar junction transistor, the
emitter and base of the device are shorted by the source metal in fabrication.
There is an overlapping of metal across the n−-epi layer. This serves two purposes.
During inversion of the p-body, it forms accumulation layer under the n−-epi layer,
which modulates the conductivity and reduces the switch-on resistance. Figure 2.17
illustrates the switching on accumulation at the SiO2-n−-epi interface. During the
switch-off, it forms field plate preventing the radius of depletion curvature from being
too small that reduces the breakdown voltage of the device. Figure 2.18 illustrates
the depletion boundary during switch off.
Oxide
n+ poly
n+ n+
n− -epi
Figure 2.17 The switching on accumulation at the SiO2-n−-epi interface

UNIT 2 21
Source metal
Oxide
n+ poly
n+ n+
p p
p+ Well p+ Well
Depletion
Boundary
n− Epi layer
n+ substrate
Drain metal
Figure 2.18 The switching off depletion boundary of power MOSFET
Current-voltage characteristic
The current-voltage (I-V) characteristic of power MOSFET has the characteristic

like the normal MOSFET. The gate is used to control the flow of current from
drain-to-source. In power MOSFET, the gate is used to control the power delivery
to the load. The I-V characteristic curve is shown in Figure 2.19.
IDS
VDS ≤ VGS − Vt VDS ≥ VGS − Vt
Linear Saturation Region
Region VGS 4
4
3 VDS = VGS − Vt
VGS 3
VGS 2
1
VGS 1
VDS
0 1 2 3 4 5 6 7 8 9 BVDSS
VGS ≤ Vt(cutoff )
Figure 2.19 IDS versus VDS characteristic of power MOSFET
When the power MOSFET is biased by a large gate-to-source voltage (VGS), the
device will be driven into linear or ohmic region. The power MOSFET is in linear
or ohmic region when it satisfies the condition as shown in equation (2.21).
VDS ≤ VGS − Vt (2.21)
where Vt is the threshold voltage of MOSFET and VDS is the voltage between drain
and source of MOSFET. When this condition is satisfied, the power dissipation
across drain-to-source regions is at minimum although the drain-to-source current
(IDS) is large.
When the gate-to-source voltage (VGS) is larger than the threshold voltage (Vt)
and small value of drain-to-source voltage (VDS), the thickness of inversion layer is
uniform through the channel. This is because the source-to-channel voltage (VCS)
is almost constant throughout the channel. Thus, the oxide voltage (Vox), which is
equal to (VGS − VCS) is constant. The illustration is shown in Figure 2.20.
Source metal
Oxide
n+ poly
L
n +
Depletion Layer
Inversion Layer
Figure 2.20 Uniform depletion and inversion layers of power MOSFET
As the drain-to-source voltage (VDS) increases which shall mean drain-to-source

current IDS increases, the variation of source-to-channel voltage (VCS) is significant
which has VCS = 0 at source and VCS = VDS at the end of the channel. Oxide voltage
(Vox) also decreases from source to end of channel. Thus, the inversion layer is
spatially non-uniform from source to the end of channel as shown in Figure 2.21.
Since there is thinning of depletion thickness at the end of channel, this shall mean
that VGS − VDS shall be reduced to Vt and consequently there is no inversion at the
end of channel and forced the device into linear region. This is not an expected
condition. However, owing to high electrical field at the end of channel, the electron
would be driven to its saturation velocity. Consequently, an extra VDS voltage would
extend the narrow depletion layer towards source. Thus, the device would maintain
in saturation region rather than forced into linear region.
UNIT 2 23
Source metal
Oxide
n+ poly
L
n +
Depletion Layer
Inversion Layer
Figure 2.21 Spatially non-uniform depletion and inversion layers of power MOSFET
Switching characteristic
Before we consider the switching characteristic of MOSFET, let's look at the

capacitance of the device, which is shown in Figure 2.22.
Cgs
Cgd n+
p
Cds
n−
n+
Figure 2.22 Capacitances of power MOSFET
As shown in the figure, there is a number of capacitance, which is basically fixed

or variable depending on the depletion thickness. Not including in the figure are
capacitance of drain-to-source (Cds) and capacitance (Cn−/n+)of n−-drift and n+-drain
region in which its magnitude is very small.
The transient response equivalent circuit for cut-off/active region, ohmic region and
the variation of gate-to-drain capacitance (Cgs) to drain-to-source voltage (VDS) are
shown in Figure 2.23.
Drain Drain
Cgd Cgd
Gate IDS = f(VGS) Gate rDS(on)
Cgs Cgs
Source Source
(a) cut-off/active region (b) ohmic region
Cgd
Cgd2
Ideal
Actual
Cgd1
VDS
VGS = VDS 200 V
(c) Cgs capacitance versus VDS voltage
Figure 2.23 The transient response equivalent circuit of power MOSFET
The switching time is the response time of the conducting channel for a given drain-
to-source-voltage (VDS) with respect to the change in the gate-to-source voltage (VGS).
There are four switching time parameters namely, on delay time (tdOn), rise time
(tr), off delay time (tdOff ), and fall time (tf ) as illustrated in Figure 2.24.
VDS
90%
10%
VGS
tdon tr tdoff tf
Figure 2.24 The typical switching time waveform of power MOSFET

UNIT 2 25
The gate charge waveform and drain-to-source voltage waveform for switch on and
switch off conditions are shown in Figure 2.25.
Voltage Voltage
VDS VDS
RG(Cgd2 + Cgs)
RG(Cgd1 + Cgs)
VGS
VIN RG(Cgd2 + Cgs) VIN RG(Cgd1 + Cgs)
VGS
t0 t1 t2 t3 t0 t1 t2 t3
time time
(a) (b)
Figure 2.25 The gate charge waveform and drain to source voltage waveform for (a)
switch-on and (b) switch-off conditions
The delay on time (tdOn) is represented by the time interval between t0 and t1 as
shown in Figure 2.25 (a) where it is the time taken for the gate-to-source voltage
(VGS) to rise to threshold voltage Vt. Thus, tdOn depends on input gate impedance
(RG) and input capacitance (CISS), which can be represented by a RC network
charging principle given by
tdOn = RG(Cgs + Cgd)ln

( VIN
VIN − Vt ) (2.22)
where Vin is the magnitude of the input voltage, and Vt is the threshold voltage, RG
is the input gate resistance, Cgs and Cgd are gate-to-source capacitance and gate-to-
drain capacitance at zero bias voltage respectively. During this time interval, the gate
voltage (VGS) rises exponentially following expression
[
VGS(t) = VIN 1 − exp −
( t
RG(Cgs + Ccd) )] .
Time interval (t1 − t2) represents the fall time (tf ) as shown in Figure 2.25 (b) where
it is the time taken for the drain-to-source voltage (VDS) to rise from minimum to
maximum value. It can be obtained from the expression given by
R G C g d + (VL − VF)
tf = (2.23)
I DS
Vt +
gm
where Cgd is the gate-to-drain capacitance, Cgs is the gate-to-source capacitance, IDS
is the drain to source current, gm is the transconductance, VF is the turn-on voltage
drops of the power MOSFET and VL is voltage drop across stray inductance (Ls).
During this interval, the drain-to-source voltage
(VDS) is VDS(t) = VF +
1
R GCgd ( I
Vt + DS t.
gm )
The time interval (t1 − t2) of Figure 2.25 (a) represents the rise time (tr), which
has the same expression as the tf except the denominator needs to change to
IDS
Vt − since it is the time interval for the gate-to-source voltage to raise from the
gm
value Vt to the value VIN. During this interval, the drain-to-source current (IDS)
{ [
follows expression IDS(t) = gm(VGS − Vt) = gm VIN 1 − exp −
( t
R G( C gs + C cd) )] }
− Vt .
The time interval (t0 − t1) of Figure 2.25 (b) represents off delay time (tdOff ). It
is the time taken to discharge the gate from its threshold voltage (Vt) to zero volt.
Using the discharge mode of RC network, tdOff is represented by the expression
( )
V IN
tdOff = RG(Cgs + Cgd)1n (2.24)
IDS
Vt +
gm
where Cgs and Cgd are gate-to-source capacitance and gate-to-drain capacitance at
zero voltage.
During this interval, the time dependent gate-to-source (VGS(t)) follows expression
VGS(t) = Vt +
IDS
gm [ (
= VIN exp −
t
R G(C gs + C gd)
. )]
The time interval (t2 − t3) of Figure 2.25 (a) represents the time taken to charge the
gate to the applied gate voltage (VIN) after the drain-to-source voltage (VDS) drops
to its minimum value. The expressions used to calculate the time interval follows
equation (2.25).
UNIT 2 27
(VS − VF )RG C g d
(t2 − t3) = (2.25)
[ ( )]
VG − Vt +
gm

I DS
where VS is the maximum drain-to-source voltage and VF is the turn-on voltage

drop of the power MOSFET.
[ ]
During this interval, the drain voltage [V DS(t)] decreases linearly following
expression V DS(t) = V L −
( )
VIN − Vt +
I DS
gm
t , where V L is the voltage drops
R GC gd
accross the inductive load RL.
The time interval (t2 − t3) of Figure 2.25 (b) represents the time for the remaining
portion of the gate-to-source voltage to be discharged. If the stray inductance
LS is small, the drain voltage can be assumed to remain relatively constant, then
the gate-to-source voltage V GS at this internal shall follow expression
(
VGS(t) = Vt +
IDS
gm ) (
exp −
t
RG(Cgs + Cgd) ) and the corresponding drain current IDS
shall be IDS = (IL + gmVt)exp −

( t
RG(Cgs + Cgd) )
− gmVt.
The expression for the time interval (t2 − t3) shall be
(t2 − t3) = RG(Cgs + Cgd)1n

( IL
gmVt
+ 1
) (2.26)
The time intervals (t0 − t3) of Figure 2.25 (a) and (t0 − t3) of Figure 2.25 (b) are
known as turn-in time (tOn) and turn-off time (tOff) respectively.
Other power MOSFET structures
Besides the vertical diffusion power MOSFET structure, other MOSFET structures
are available. They are aimed to reduce the switch-on resistance (Ron), improve the
current carrying capability, improve switching time, and reducing the significance of
parasitic component such as JFET that effects switching time. Some of such design
structures are Trench V-Groove MOSFET and Truncated V-Groove MOSFET
shown in Figure 2.26 and Figure 2.27 respectively. Perhaps, it is worth to mention
that UMOS is another power MOSFET structure, which is shown in Figure 2.28.
Source Gate Source
Oxide
n+ n+
p-body p-body
n− Epi layer
n+ substrate
Drain
Figure 2.26 An n-channel Trench V-Groove MOSFET
Gate
Gate
n+ n+
Oxide
p-body p-body
n− Epi layer Channel
n+ substrate
Drain
Figure 2.27 An n-channel Truncated V-Groove MOSFET

UNIT 2 29
Gate
Source Source
Gate
N+ N+
P-base Poly P-base
N−
N+
Drain
Figure 2.28 An n-channel UMOSFET
Silicon carbide power MOSFETS

The on-resistance of silicon power MOSFET devices is mainly depending on the
on-resistance of the drift region. Based on the concept of punchthrough, the on-
resistance (Ron) of the MOSFET follows expression
Wd
Ron = = 5.93 × 10−8 V 25
B (2.27)
eµnND
Taking ND = 1.0 × 1016cm−3 for p-channel device type and Wd is the thickness of the
Wd
drift region. For n-channel, the on-resistance follows expression R on =
eµnND
= 1.63 × 10−8 V B25. Based on the expression, one can see that on-resistance is depending
on breakdown voltage (VB). For breakdown voltage above 200 V, the ideal on-
resistance for n-channel silicon MOSFET is greater than 1 × 10−2 ohm-cm2. This
shall mean that the turn-on voltage drop is exceeding 1.0 V. One way to overcome
the problem is to reduce the current density but this will require large cross sectional
area, which is not cost effective.
From the physics point of view, the material that has higher critical breakdown electric
field would have lower on-resistance. This can be shown from the punchthrough
equation and the avalanche breakdown critical electric field equations, which are
e SE 2Crit 2VB
ND = and Wd = . Based on these two equations, the on-resistance of the
2qVB ECrit
MOSFET shall be
Wd 4V 2B
Ron = = (2.28)
qµnND eSE3Critµn
where the denominator eSECrit3

µn is known as Baliga’s figure of merit for unipolar power
devices. By using the material such as silicon carbide, it has this figure of merit 200
times larger than silicon. The MOSFET can have large breakdown voltage and yet
low on resistance. Another good material is gallium arsenide that has 12.7 times
Baliga’s figure of merit of silicon.
Static-induction transistor
The static-induction transistor is basically a JFET or MESFET. The static-induction
transistor (SIT) was introduced by Nishizawa et al. in 1972. The transistor features
non-saturating I-V characteristics with increasing drain voltage because the barrier
for carriers is lowered by electrostatic induction from the drain. It was used to power
amplifiers in the mid-1980s. The common structures of static-induction transistor
are shown in Figure 2.29. The most critical parameters in an SIT are the spacing
between gates 2a and the channel doping level ND. Most of the SITs are designed
by choosing the doping concentration such that the depletion regions from the
gates do not merge and there exists a narrow, neutral channel opening with zero
gate bias. The structures also show that the gates are formed by pn junctions, but
the SIT operations can be generalised to include metal Schottky or metal-insulator-
semiconductor MIS gates. In the case of metal gates, the device will be similar to
a permeable-base transistor. The main difference then will be the device operation
regime, not the structure. Most SITS reported are made on a silicon substrate, with
gallium arsenide (GaAs) being the next choice of material for higher-speed operations.
Gate Source Gate Insulator Source

n +
n +
n+ n+
p+ p+
2a
p+ 2a p+
n Gate n Gate
n+ n+
Drain Drain
(a) Planar gate (b) Recessed gate
Figure 2.29 Structures of static-induction transistor

UNIT 2 31
Summary
In this section on power devices, you have studied and achieved

the learning objectives pertaining to distinguishing the difference
between a power device and a normal small signal amplifier device;
describing different types of power devices; describing dc and
switching characteristics of a power diode, an insulated gate bipolar
junction transistor, a power MOSFET, and a silicon carbide power
device; and solve turn-on resistance issue of power MOSFETs with
other configurations.
Self-test 2.1
A power silicon diode has breakdown voltage of 2,500V. Calculate

the doping concentration of n− epi layer. What is the minimum
thickness of the n− epi layer if the diode is non-punchthrough type?
Self-test 2.2
If a power has an n−-epi layer with doping concentration of 1.0 ×

1014 cm−3, and thickness of 50 × 10−4 cm, what is the breakdown
voltage of this diode?
Self-test 2.3
The gate-to-source capacitance, gate-to-drain capacitance, and

gate resistance of a power MOSFET are 2.0fF, 5.0fF, and 5.0MΩ
respectively. It operates at input voltage 5.0V and has threshold
voltage of 2.0V. Calculate the delay on time of this MOSFET.
Suggested answers to activities
Feedback
Activity 2.1
High power diode contains an additional drift layer of certain pre-

defined thickness to the low power version device’s structure. This
additional layer would determine the breakdown voltage of the
power diode. High power diode can withstand high current flow
and is normally large structure as compared to low power diode.
Activity 2.2
The conductivity of epi-layer of the power diode becomes higher

during operation. This is because due injection of the majority
carrier from the p+ and n+ region of the diode into it that has changed
the concentration of carrier to a higher value in the epi-layer.
Activity 2.3
The IGBT is switched on by a MOS gate that inverts either p-type

or n-type semiconductor separating the epi-layer with the cathode.
Once the IGBT is switched on, it has the characteristic of p-i-n
diode.
Activity 2.4
MOS-controlled thyristor MCT is a device that has two MOSFETs

built into the gate structure with one MOSFFET used to turn-on
the device called ON-FET and one used to turn-off the device
called OFF-FET.
UNIT 2 33
2.2 Thyristor
Objectives
By the end of this section, you should be able to:
1. Describe a thyristor being a four-layer device.
2. Differentiate types of thyristor devices such as Shockley diode, silicon-

controlled rectifier, DIAC and TRIAC devices.
3. Use thyristor device in power control circuit design.
Introduction
Thyristor is a power device, which is also four-layer device. The four layers are
pnpn junctions. There are several devices in this family namely Shockley diode,
silicon-controlled rectifier SCR, silicon-controlled switch SCS, DIAC, TRIAC,
gate turn-off switch (GTO), light-activated silicon-controlled rectifier (LASCR),
unijunction transistor and etc. The characteristics of these devices are that they act as
open circuit capable of withstanding certain voltage until they are triggered. When
triggered on, they become low-resistance high current devices even when the trigger
is removed and they remain on until the current is reduced to the holding current
level or they are triggered off.
The middle n-layer of the thyristor is lightly doped that has concentration in the
region from 1013 cm−3 to 5 × 1014 cm−3. The middle p-layer is moderately doped that
has doping concentration around 1017cm−3. The cathode, which is made of n-type, is
heavily doped that has doping concentration in 1019 cm−3 region, whilst the anode,
which is made of p-type is moderately doped with doping concentration 1017 cm−3.
The doping concentration profile of the thyristor is shown in Figure 2.30.
p+
n+ p p
1019cm−3 1017cm−3 1017 1019

cm−3 cm−3
n −
1013 −1014 cm−3
Figure 2.30 Doping profile of the thyristor

Application of thyristor includes controlling the amount of ac power to a load.

Examples are used in lamp dimmer, motor speed control, ignition system and
charging circuit.
Activity 2.5
What is a thyristor?
Shockley diode
The construction and schematic of a Shockley diode are shown in Figure 2.31.
Anode (A) Anode (A)
p
J1
n
J2
p
J3
n
Cathode (K)
Cathode (K)
(a) Basic construction (b) Symbol
Figure 2.31 Construction and schematic of Shockley diode
Shockley diode can be represented by an equivalent circuit of two bipolar junction

transistors connected as shown in Figure 2.32, where one is a pnp and the other is
an npn type.
UNIT 2 35
A IA = IE1
Q1
IC2 = IB1
IC1 = IB2
ICB01
+
Q2 ICB02
−
IK = IE2
K
Figure 2.32 The equivalent circuit of Shockley diode
The middle pn layer is shared by transistors Q1 and Q2, which forms their base and
collector and each transistor has its own emitter, which is the upper and bottom layer.
Operation
When a positive voltage is applied to the anode of the device with respect to the
cathode, the emitter-to-base of transistor Q1 and base-to-emitter of transistor Q2 are
in forward-biased mode, whilst the common collector-to-base of both transistors is
reverse-biased mode. Let’s consider the case of low forward-bias voltage. Since the
current is expected to be low, thus, ICBO becomes significant. It should be considered
in the current calculation.
For transistor Q1, the emitter current IE1 is IE1 = IB1 + IC1 + ICBO1, where ICBO1 is the
open base reversed saturation current between collector and emitter of transistor Q1.
Since IC1 = a1IE1, therefore IB1 = IE1( 1 − a1) − ICBO1.
The anode current (IA) is also equal to IE1. Thus,
IB1 = IA(1 − a1) − ICBO1

IB1 + ICBO1
IA = (2.29)
(1 − a1)
For transistor Q2, IE2 = IC2 + IB2 − ICBO2, which yields IC2 = a2IE2 + ICBO2
The cathode current (IK) is also equal to IE2. Thus,
IC2 = a2IK + ICBO2

Since IC2 = IB1,
a2IK + ICBO2 = (1 − a1)IA − ICBO1
Since IA = IK, IA[(1 − a1) − a2] = ICBO1 + ICBO2
After rearranging the equation, the anode current (IA) becomes

ICBO1 + ICBO2
IA = (2.30)
1 − (a1 + a2)
In the structure like the silicon control rectifier (SCR), whereby there is a gate
control, equation (2.30) shall be modified to include the gate current contribution,
which shall be
a2IG + ICBO1 + ICBO2
IA = (2.31)
1 − (a1 + a2)

For low anode current level, both a1 and a2 are very small. Thus, at low bias voltage
level, the anode current (IA) is close to the sum of collector-to-base reverse biased
current of the transistors. This also shows that Shockley diode is in OFF-state or
forward-blocking region since the anode current is OFF-state current.
The forward-blocking region of Shockley diode is a region of high forward resistance.

Ideally it should have infinite resistance. The region exists for anode-cathode voltage
VAK ranging from zero to forward-break over voltage VBR(F).
As the anode-to-cathode voltage VAK increases, the anode current IA, a1, and a2 are
increasing gradually. The current will significantly increase. At the point when the
sum of a1 and a2 becomes one. This is also the point where VAK = VBR(F).
The increase of anode-to-cathode voltage reduces the depletion thickness at junction

J1 and J3 and increase the depletion thickness at junction J2. The thickening of the
depletion at junction J2 increases the base transport factor, which in terms increases
a value. There is also conductivity modulation during stage. The concentration of
middle layers is modulated to the level close to the concentration of layers connecting
the anode and cathode.
As anode-cathode voltage equals to forward-break over voltage V BR(F) i.e.,

VAK(on) = VBR(F), the transistors become saturated due to breakdown of reverse biased
pn junction of middle layers. Thus, it causes the anode-to-cathode voltage (VAK(on))
during the break over to drop to the values shown in equation (2.32).
VAK(on) = VJ1 − VJ2 + VJ3 + Vn− (2.32)
where VJ’s is forward bias junction voltage, which has value range from 0.7V to 0.9V
and Vn− is the voltage across junction J1 and J2, which has a few tenths of a volt.
UNIT 2 37
VAK(on) can also be estimated to be equal to VBE2 + VCE1(sat), a value, which is smaller
than VBR(F). Figure 2.33 shows the characteristics and its ON/OFF states. Figure 2.34
shows the calculation for the values of anode current (IA) at ON-state and OFF-state.
IA
Forward
Conducting
Region
IH
VAK
VH VBR(F)
Reverse Forward
Blocking Blocking
Region Region
Figure 2.33 Shockley diode characteristic curve
ICBO1 + ICBO2 VBias − VA

IA = IA =
1 − (a1 − a2) RS
RS RS
+ +
VBias VAK = VA VBias
VAK < VBR(F) − −
(a) OFF-state (b) ON-state
Figure 2.34 OFF/ON states of a Shockley diode biased with dc voltage
(VBIAS − VA)
At ON-state, the anode current is approximately equal to IA = ,
RS
where VA is the ON forward voltage of Shockley diode. VBias is the biasing voltage,
VA is the voltage at anode, and RS is the resistance.
Once the Shockley diode is in ON-state, it will remain in ON-state until the anode
current IA is reduced below the holding current (IH). When anode current (IA) falls
below IH, the diode will rapidly switch back to the OFF-state and enter into the
forward-blocking region.
The value of anode current (IA) at the point where the device switches from forward-
blocking region - OFF-state to forward-conduction region - ON-state, is called
switching current (IS). This value of current is always less than the holding current
(IH) at forward blocking region.
An application of Shockley diode is used to design relaxation oscillator, which has

its circuit shown in Figure 2.35 (a). When the switch S is closed, the capacitor
C charges through resistor R until its voltage reaches forward-break over voltage
(VBR(F)). At this voltage point, Shockley diode is in forward conducting region. The
capacitor is then discharged through the low forward resistance RF of Shockley diode.
Discharging occurred until the current falls below the holding current IH. When
the anode current IA falls below the holding current IH, Shockley diode switches to
forward-blocking region. The capacitor begins to charge again from voltage (V).
The process repeats continuously and its waveform is shown in Figure 2.35 (b).
Since the value of series resistance (R) is much greater than the forward conducting
resistance of Shockley diode RF, the charging time is longer than discharging time.
S VC
+ VBR(F)
V C
− RF
t
0
(a) Relaxation oscillator (b) Waveform
Figure 2.35 Shockley diode relaxation oscillator
Silicon-controlled rectifier
The silicon control rectifier (SCR) is another four-layer pnpn device similar to
Shockley diode. However, SCR has three terminals instead of two. It has an extra
gate terminal, which is connected to the p-region of the middle pn layers. The basic
construction and schematic symbol are shown in Figure 2.36.
UNIT 2 39
Anode (A) A
n
Cathode
gate (G) p
n G
Cathode (K)
Figure 2.36 Construction and schematic of SCR
The equivalent circuit of a SCR is shown in Figure 2.37. Its structure is like the
Shockley diode except there is a gate connected to the p-region. It is like Shockley
diode, SCR has two states i.e., ON and OFF-states.
A Anode
p
Q1
G p
Gate Q2
n
K Cathode
Figure 2.37 An equivalent circuit of SCR
When the gate current (IG) is 0 A i.e., the gate voltage (VG) is equal to 0 V. The
device is at OFF-state. The resistance between anode and cathode is very high,
which is approximately like an open circuit. When the anode voltage is higher than
the cathode voltage and a positive pulse voltage of more than 0.7 V is applied to
the gate, both transistors turn on sequentially. The gate pulse turns on transistor
Q2 and provides the connecting path for base current of transistor Q1 IB1 to turn
on transistor Q1. These actions would turn both transistors into saturation. Even if
the triggering pulse is removed, the SCR will remain at ON-state. The illustration
of how to operate SCR is shown in Figure 2.38.
+V +V +V +V
RA RA RA R
IA
IA = 0 IB1
Q1 A Q1 A
OFF ON
K K
IB2
VC = 0 Q2 Q2
IC = 0 OFF ON
IG
IK
+V
(a) SCR off (b) Triggered

RA
IA +V
IB1
Q1
ON RA
IC = 0 IB2
Q2 A
ON
IK K
(c) SCR on
Figure 2.38 The circuits illustrate how to operate SCR
It is like Shockley diode. An SCR can be turned-on without gate triggering by

increasing anode-to-cathode voltage (VAK) to a value exceeding the forward-breakover
voltage (VBR(F)). As shown in Figure 2.39, the forward-break over voltage decreases
as gate current (IG) increased. Higher value of gate current (IG) can be used to obtain
a low forward breakover voltage (VBR(F)). It shall mean that gate current (IG) can be
used to vary forward breakover voltage (VBR(F)).
There is a reverse-biased region like a normal reverse-biased pn junction. Its working

principle is self-explanatory.
UNIT 2 41
IA
IH0 IG2 > IG1 IG1 > IG0

IG0 = 0
IH1
IH2
VF
IR 0 VBR(F2) VBR(F1) VFR(F0)
Figure 2.39 SCR characteristic for various gates current (IG)
From the characteristic curve, one will also notice that the holding current is higher
for higher forward-break over voltage and lower gate current.
In order to turn-off SCR, the anode current (IA) must be below the holding current
(IH). Listed here are two ways to turn-off an SCR namely anode current interruption
as shown in Figure 2.40 and forced commutation as shown in Figure 2.41.
+V +V
IA = 0
RA
RA
IA < IH
G G
(a) (b)
Figure 2.40 SCR turn-off by anode interruption: (a) shut-off and (b) force to zero
+V +V
S S
+ − + −
RK RK
(a) (b)
Figure 2.41 SCR turn-off by forced commutation
SCR has many applications in the area of power control and switching application.
A few are discussed here.
On-off control of current
SCR can be used as ON and OFF control of current. The illustration is shown in
Figure 2.42.
+V
RL
S2
RG
+ S1
Figure 2.42 An SCR used as ON-OFF control of current

UNIT 2 43
Activity 2.6
An SCR in its forward-block region has anode voltage VA = 30 V,

gate current IG = 1.0 µA, ICBO1 = ICBO2 = 50 nA. If a1 = 0.5 and
a2 = 0.3 under those conditions, find the anode current (IA) and
dc resistance (Rdc) of the SCR.
Half-wave power control
The half-wave power control application of SCR is shown in Figure 2.43. In this
application, SCR is used to control the triggering angle θf by adjusting the value of
R2. Since the voltages at gate are VG1, VG2, and VG3 such that VG1 > VG2 > VG3. This
implies that the gate current is such that IG1 > IG2 > IG3 and break over voltage of
SCR shall be VBR(F)1 < VBR(F)2 < VBR(F)3. The triggering angle θf shall increase as break
over voltage increases and average power delivered to the load shall be decreased
accordingly.
R1
Vp
A
RL iL
θf = 0° 180° R2
Trigger
B
VG1
(a) 180° conduction
Trigger R1
Vp A
RL iL
θf = 45° 135° R2
B
VG2
(b) 135° conduction

Trigger
R1
Vp A
RL
iL
θf = 90° 90°
R2
B
VG3
(c) 90° conduction
Figure 2.43 Operation of firing phase angle control from half-wave power SCR
When the SCR conducts, the peak load current (Ip) is

Vp − VAK
Ip = (2.33)
RL
where Vp is the amplitude of input ac voltage, RL is the load, and VAK is the forward
voltage drop across the SCR, which can be approximately equal to 1.0 V.
The average current (IAvg) and rms current are

Ip
IAvg = (1 + cosθf ) (2.34)
2p
√ ( )
Ip θf sin 2θf
Irms = 1− + (2.35)
2 180 2p
where θf is the trigger angle.
Lighting system to power interruptions
The use of SCR for lighting system control is illustrated in Figure 2.44 (a). When
ac power is present, the cathode and anode of SCR are almost at the same potential
and the gate current is not zero.
When there is no ac power, as shown in Figure 2.44 (b), the anode voltage of SCR is
higher than the voltage at cathode. Thus, SCR will be switched to forward conducting
region triggered by the gate current. The backup battery shall supply the power to
the load. When ac power resumes, the SCR is forced commutation off and moved
into forward blocking region.
UNIT 2 45
R1 D3
D1 OFF +6 V
120 V
rms 6.3 V +
−
6.3 VG
V D2 R3
R2 +
6V
−
(a) ac power on
R1 D3
D1 ON
0V rms 0V
C
0V
D2 R3
R2 +
6V
−
(b) Back-up battery power (ac power off )
Figure 2.44 Automatic backup lighting system
Silicon-controlled switch
The silicon-controlled switch (SCS) has the same construction like the SCR except it
has two gate terminals namely cathode gate and anode gate as shown in Figure 2.45.
Anode (A) Anode (A)
Anode gate
Anode gate (GA)
p
(GA)
n
p Cathode
Cathode gate
gate n (GK)
(GK)
Cathode (K)
Cathode (K)
Figure 2.45 Silicon controlled switch (SCS)

The silicon controlled switch (SCS) can be turned-on or off by either gate terminal
as illustrated in Figure 2.46. To turn off SCS, it needs to reduce its anode current
to below holding current (IH).
+V +V
RA RA
A A −
Q1 GA Q1 + GA
on off
GK Q2 GK I=0 Q2
on off
K K
(a) Turn on: Positive pulse on (b) Turn off: Positive pulse on
GK or negative pulse on GA GA or negative pulse on GK
Figure 2.46 Operation of silicon controlled switch (SCS)
Bipolar junction transistor can be used to reduce holding current (IH) as illustrated
in Figure 2.47. Figure 2.47 (a) illustrates that the SCS can be switched off by setting
the voltage at the base of transistor Q to be at zero volt. Alternatively, as illustrated
in Figure 2.47 (b), the SCS can be switched off by directing the current to transistor
Q by switching it so that the anode current will be below hold current (IH).
+V +V
Q RA
Q on
Q off RA
Q on
Q
Q off
(a) Series switch turns off SCS (b) Shunt switch turns off SCS
Figure 2.47 Bipolar junction transistor switch used to control holding current (IH) of SCS
UNIT 2 47
Activity 2.7
Using the series switch turns off SCS method shown in Figure 2.47
(a), calculate the minimum voltage required to be connected to the
base of transistor Q so that the SCS can maintain in switch-on mode.
DIAC and TRIAC

Both DIAC and TRIAC are four layer devices. They can conduct in both directions.
TRIAC has a gate whereas DIAC has no gate.
DIAC
DIAC is diode ac. Its construction and symbol are shown in Figure 2.48.
A1 A1
n
p
n
p
n
A2 A2
Figure 2.48 Construction and symbol of DIAC
The equivalent circuit and characteristics of DIAC are shown in Figure 2.49 and
Figure 2.50 respectively.
A1
Q3
Q1
Q4
Q2
A2
Figure 2.49 Equivalent circuit of DIAC
IF
IH
−VBR(R)
VF
0 VBR(F)
−IH
Figure 2.50 Characteristics curve of DIAC
The bias condition of DIAC is shown in Figure 2.51. In both cases, the absolute
voltage of voltage V has to be more than the VBRF(F) of the DIAC.
UNIT 2 49
R R
A1 A1
−
+
V V
+
−
A2 A2
(a) Positive bias (b) Negative bias
Figure 2.51 The bias condition for DIAC
TRIAC
TRIAC is triode ac. It is like DIAC except it has gate terminal. TRIAC can be
switched on by a pulse of gate current and does not necessarily require break over
voltage (VBR(F)). TRIAC can be viewed as two SCRs connected in parallel in opposite
direction with a common gate terminal. Unlike the SCR, TRIAC can conduct in
both directions once the gate is triggered.
The basic construction and symbol of TRIAC are shown in Figure 2.52.
A1
A1
n n
p
n
p
n n G
Gate
A2
A2
Figure 2.52 Construction and symbol of TRIAC
The characteristic curve of TRIAC is shown in Figure 2.53. It has the same pattern
characteristic curve like the SCR with extra characteristic curve at negative bias
region.
IA
IG2 > IG1 IG1 > IG0

IH0 IG0 = 0
IH1
−VBR(F ) − VBR(F ) − VBR(F ) IH2
0 1 2
VA
VBR(F2) VBR(F1) VBR(F0)
−IH2
−IH1
−IH0
−IG0 −IG1 −IG2
Figure 2.53 Characteristic curve of TRIAC
The operation of the TRIAC is shown in Figure 2.54. It can be switched-on using
a positive voltage pulse. The direction of current flow depends on the voltage at
node A1 and A2. If the voltage at node A1 is larger than the voltage at node A2, then
the current will flow from node A1 to node A2. Likewise, if the voltage at node A2
is larger than voltage at node A1, then current will flow from node A2 to node A1.
+V +V
R A1
Q3
A1 Q1
G
G
A2
Q2 Q4
A2
(a) (b) Q1 and Q2 on
A1
R
Q3
A1 Q1
G G
A2
Q2 Q4
A2
+V
(c) (d) Q3 and Q4 on
Figure 2.54 The bilateral operation of TRIAC

UNIT 2 51
Like the SCR, TRIACs are also used to control average power to a load by the method
of phase control. The TRIAC can be triggered such that the ac power is supplied to
the load for a controlled portion of each half-cycle.
During each positive half-cycle of ac, the TRIAC is off for a certain interval, called
the delay angle and then it is triggered on and conducts current through the load
for the remaining portion of the positive half-cycle, called conduction angle. Similar
action occurs on the negative half-cycle except that of course, current is conducted
in the opposite direction through the load. An example is shown in Figure 2.55.
D1 RL
Trigger point
A1 VR
L
Vin
t
θf
R G
Trigger point
D2
A2 (adjusted by R)
C
(a) Circuit diagram (b) Waveform
Figure 2.55 TRIAC phase-control circuit
The average current (Iavg) of the DIAC and TRIAC is equal to zero since the positive
and negative cycles cover the same area of current waveform. However, the rms
1 p I2 p
current Irms is Irms =
√ ∫(IP sin φ)2dφ = I2rms = p ∫(sin φ)2dφ. Thus, it is equal to
p θf p θf
[( )]
p
I2p p I2 1
I2rms = ∫(1 − cos 2φ)dφ = I2rms = p φ − sin 2φ . Therefore, the rms current
2p θf 2p 2 θf
(Irms) is equal to
√( )
Ip θf sin 2θf
Irms = 1− + (2.36)
√2 180° 2p
It can also be shown that the triggering angle (θf) is equal to
|
θf = 90° − tan−1
1
wRC
V
|| (
+ sin−1 BR(F)
VC(p) )| (2.37)
where VC(P) is the peak voltage across capacitor C. The peak voltage across capacitor
Vp
1
is equal to VC(P) = ·
√( )
2
wC
1
2
R+

wC
Summary
This section covered the learning of thyristor. You should have

achieved the learning objectives on describing a thyristor being
a four-layer device; differential types of thyristor devices such as
Shockley diode, silicon-controlled rectifier, DIAC, and TRIAC
devices; and use thyristor device in power control circuit design.
Self-test 2.4
Describe the characteristic curve of thyristor shown below.
IA
On
IH
Off
VAK
VBR(F)
UNIT 2 53
Self-test 2.5
In reference to the circuit shown in Figure 2.55, determine the

triggering angle, the conduction angle, and percentage of the power
delivered to the load given that C = 0.22 µF, R = 22.0 kΩ, and
VBR(F) = 25 V, Vin = 220 rmsV, and frequency of ac is 50 Hz. The
load consists of ten 100 W light bulbs connected in parallel.
Suggested answers to activities
Feedback
Activity 2.5
Thyristor is a four layer pnpn device which has characteristic of

ability to withstand a certain level of applied voltage called forward
break over voltage before it is turned on. It can also be turned on by
voltage triggering. Once it is turned on, it becomes a high current
low resistance device. It will remain on unless it is triggered off or
its anode current is below the holding current.
Actitivity 2.6
The anode current is

a 2IG + ICBO1 + ICBO2 0.3(1.0µA) + 50nA + 50nA
IA = = = 2.0 µA.
1 − (a1 + a2) 1 − (0.5 + 0.3)
The dc resistance (Rdc) is 30V/IA = 15.0 MΩ.
Activity 2.7
The minimum voltage to be connected to the base of the SCS is

Vmin = VBE of transistor Q + IARA + VAK. IA is anode current, RA is
anode resistance, and switch-on VAK is anode to cathode voltage
of SCS.
UNIT 2 55
Summary of Unit 2
Summary
In this unit on semiconductor devices, you have learnt two main

topics which are power device and thyristor. In each section, you
have studied and achieved what have been specified in the learning
objectives via tutorials, learning activities, and self-tests.
In section one on power devices, you have learnt and achieved the
ability and confidence to distinguish the difference between a power
device and a normal small signal amplifier device; describe different
types of power devices; describe the dc and switching characteristics
of power diode, insulated gate bipolar junction transistor, power
MOSFET, and silicon carbide power device; and study the other
configuration of power MOSFETs for solving turn-on resistance
issue.
In section two on thyristors, you have studied and achieved the

ability to describe a thyristor being a four-layer device; distinguish
different types of thyristor devices such as Shockley diode, silicon-
controlled rectifier, DIAC, and TRIAC devices; and use thyristor
device in power control circuit design.
UNIT 2 57
Suggested Answers to Self-tests
Feedback
Self-test 2.1
e SE 2Crit
The doping concentration of diode follows equation ND = .
2qVB
According to the data shown and the known doping concentration
range of the power diode, the critical electrical field should be
in 2.0 × 105 V/cm. Thus, the doping concentration shall be
11.7 × 8.854 × 10−14 × (2 × 105)3
ND = = 5.17 × 1013cm−3.
2 × 1.602 × 10−19 × 2500
Knowing the doping concentration, the minimum thickness of
non-punchthrough condition diode follows equation

2 × 11.7 × 8.854 × 10−14
√ √
2eS
WD = VR = 2500 = 250.0µm.
qND 1.602 × 10−19 × 5.17 × 1013
Self-test 2.2
qNDW 2D
The breakdown voltage follows equation VR = .
2eS
The permittivity of silicon is eS = Kse0 = 11.7 × 8.854 × 10−14F/cm
1.602 × 10−19 × 1.0 × 1014 × 502 ×10−8
= = 193.3 V.
2 × 11.7 × 8.854 × 10−14
Self-test 2.3
The delay on time can be calculated using equation
tdOn = RG(Cgs + Cgd)1n

( VIN
VIN − Vt )
= 5.0 × 106(2.0fF + 5fF)1n ( )
5.0
5−3
= 32.1ns.
Self-test 2.4
The characteristic curve of thyristor has three regions namely

forward blocking region, forward conducting region, and reverse
blocking region. Reverse blocking region has the characteristic of
a reversed bias pn junction whereby its current is independent of
anode-cathode voltage and there is a breakdown region. In the
forward blocking region, the current of thyristor is very small whilst
its resistance is very high. The forward blocking region has the
characteristics of a forward bias pn junction whereby its current is
large and resistance is low.
Self-test 2.5
The peak voltage VP = 311.1V. The power of the load is 1,000W.

1
The impedance of the capacitor is χC = = 14468.6Ω.
wC
The total impedance of the circuit is √R2 + χ 2C= 26331.4Ω.
The peak current IP = 311.1/26331.4 = 11.8mA.
The peak voltage across capacitor VC(P) = 11.8mA × 14468.6Ω

= 170.9V.
The triggering angle (θf ) is equal to
|
θf = 90° − tan−1
1
wRC
+ sin−1 || (
VBR(F)
VC(p) )| = 90° − tan−1 ( )
14468.6
22000
+
sin−1
( )25
170.9
= 90° − 33.3° + 8.4° = 65.1°.
The conduction angle is 180° − 65.1° = 114.9°.

1,000W
The rms current of the load is = 4.5A and the peak current
220V
IP is equal to 6.35A.
√( )
Ip θf sin 2θf
The rms current of the load is ILrms = = 1− +
√2 180° 2p
√( )
6.35 65.1° sin130.2°
= 1− + = 3.91A.
√2 180° 2p
The power received by the load is 3.91A × 220V = 860.2W.

UNIT 2 59
The percentage of power delivered to the load is

860.2
1,000 × 100% = 86.0%.
1,000
UNIT 2 61
References
Alexander, C K and Sadiku, M N O (2004) Electric Circuits, 2nd edn, New York:
McGraw-Hill.
Carlson, A B (2000) Circuits, New York: Brooks/Cole.
Nilsson, J W and Riedel, S A (2001) Electric Circuits, 6th edn, New York: Prentice
Hall.
UNIT 2 63
Glossary
Cgd Gate-to-drain capacitance
Cgs Gate-to-source capacitance
COMFET Conductivity modulated field effect transistor
DMOS Dual MOS transistor
ECrit Critical electric field
IA Anode current
IH Holding current
IK Cathode current
Irms Root mean square current
IGBT Insulated gate bipolar transistor
MCT MOS controlled thyristor
Na Modulated concentration of hole
ND Doping concentration of electron
RL Load resistance
SCR Silicon control rectifier
SCS Silicon control switch
SIT Static induction transistor
trr Reverse recovery time
VAK Voltage across anode and cathode
VBR/VB Breakdown voltage
VBR(F) Forward break over voltage
VDS Drain-to-source voltage
VG Gate voltage
VGS Gate-to-source voltage
Vox Voltage across oxide
VP Peak voltage
Wd Thickness of drift layer
µn Mobility of electron
µp Mobility of hole
t Diffusion time
eS Permittivity of silicon

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UNIT 2 i

Semiconductor power devices

EXTERNAL COURSE ASSESSOR

© 2014 Wawasan Open University

Wawasan Open University [DU013(P)]

2.1 Power devices 3

Insulated gate bipolar junction transistor 13

Silicon carbide power MOSFETS 29

Suggested answers to activities 32

DIAC and TRIAC 47

Suggested answers to activities 53

Suggested answers to self-tests 57

2. Describe different types of power devices.

3. Describe a thyristor being a four-layer device.

4. Distinguish different types of thyristor devices such as Shockley diode,

5. Use thyristor device in power control circuit design.

2.1 Power Devices

2. Describe different types of power devices.

3. Describe dc and switching characteristics of a power diode, an insulated

4. Solve turn-on resistance issue of power MOSFETs with other configurations.

Figure 2.1 Power diode made from pn junction

Figure 2.2 The current-voltage characteristics of a pn junction power diode

For non-punchthrough type of breakdown, the depletion thickness of breakdown

For punchthrough breakdown type, the depletion thickness of breakdown extends

(a) Profile of power diode

(b) Electric field profile of power diode at non-punchthrough and

where ND is the doping concentration of drift layer and eS is the permittivity of

Depletion layer boundary control

Guard ring Guard ring

nno = 1014 cm−3

density (Jn−ep) in equation (2.8).

Substituting equation (2.8) into equation (2.4) would yield

Vp_diode = VR + RonI (2.11)

where I is the current flows in the diode.

Taking WBreak as equal to Wd in equation (2.12) and substitute it with equation

non-conductivity modulated drift region and inductance of wire. As soon as the

Figure 2.7 Timing diagram of a power diode

Insulated gate bipolar junction transistor

(a) Vertical structure (b) Lateral structure of an n-channel IGBT

Figure 2.9 Output characteristic of an n-channel IGBT

where k is Boltzmann constant and Xn is the depletion thickness in the channel. Da

The characteristic of mode is shown in the linear region of Figure 2.9.

Figure 2.11 Equivalent circuit of pnp transistor mode of IGBT

Describe how an IGBT can be switched-on?

Figure 2.12 Cross sectional view of a p-channel MOS-controlled thyristor

The complete p-channel MCT or n-channel MCT is usually composed of many

OFF-MOSFET pnp ON-MOSFET

Figure 2.13 Equivalent circuit of p-channel MOS-controlled thyristor

Figure 2.14 Characteristic curve of p-channel MOS-controlled thyristor

Turn-on and turn off of MCT

During switch off means the n-channel OFF-MOSFET is conducting. To ensure

What is the purpose of ON-FET and OFF-FET of a p-MCT device?

Switching time of MCT

Figure 2.15 Switching waveform of an n-channel MCT

Figure 2.16 An n-channel power vertical diffusion MOSFET structure

Figure 2.17 The switching on accumulation at the SiO2-n−-epi interface

Figure 2.18 The switching off depletion boundary of power MOSFET

The current-voltage (I-V) characteristic of power MOSFET has the characteristic