0.

5 kHz – 32 MHz Digital Fractional-N Frequency

Synthesizer with Burst-Frequency Switch
Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, and Young-Chan Jang
Department of Electronic Engineering
Kumoh National Institute of Technology, Gumi, Korea
ycjang@kumoh.ac.kr

Abstract— A digital frequency synthesizer is proposed to

support the burst-frequency switch for a motion controller. The
proposed digital frequency synthesizer consists of a phase-locked
loop (PLL) generating a 63-phase clock with a frequency of 128
MHz and a programmable open-loop fractional divider. It
generates an output clock with a frequency resolution of 0.1%
over a frequency range from 0.5 kHz to 32 MHz. The
programmable open loop fractional divider generates an output (a)
clock such that its frequency is synthesized by periodically
selecting the phase interpolated clock from the 63-phase clock of
the PLL according to a digital control code. The frequency
switching operation is performed within one cycle of the output
clock owing to the operation of the phase selection of the open-
loop fractional divider. The proposed digital frequency
synthesizer is implemented using a 0.25 ȝm CMOS process with a
2.5 V supply. The measured rms time jitter of the output clock
with 16 MHz frequency is approximately 8.06 ps.

Keywords—frequency synthesizer; phase-locked loop; open-

loop fractional divider; phase interpolation; burst-frequency switch

I. INTRODUCTION
The demand for motion controllers has greatly increased
with the rapid development of automatic devices such as
automatic equipment, surgical robots, and 3D printers. In
general, a pulse width modulation (PWM) signal is used for
motion control, and it can be generated using a clock generator
including a fractional-N frequency synthesizer or a
programmable oscillator [1]-[4]. Since a diverse PWM signal is
required for a high-precision motion controller, the clock
generator should generate a clock signal having high-resolution
and wide-range frequency. Furthermore, the frequency
mismatch or variation among multiple clocks should be
minimized for usage in the applications of a multi-axis motion
controller.
A phase locked loop (PLL) using sigma-delta modulation
can be used for a fractional-N frequency synthesizer [1]-[3].
The frequency divide ratio for a reference clock and feedback
clock supplied from a voltage-controlled oscillator (VCO) may
be increased to implement frequency synthesis with high
resolution. In this case, the locking time of a frequency
synthesizer and time jitter of a frequency-synthesized clock can
be increased during the operation of the frequency synthesizer.
A programmable digitally controlled oscillator (DCO) has also
been used to generate a PWM signal for a motion controller [4].
Fig. 1(a) shows a conceptual block diagram of the
(b)
Fig. 1. Frequency synthesizer (a) conceptual block diagram (b) simulation
result of frequency according to output voltage of DAC.
programmable DCO. It consists of a digital-to-analog converter
(DAC), VCO, and programmable frequency divider. The DAC
outputs an analog voltage according to a digital input code and
the VCO generates an output clock with various frequencies
according to the output voltage of the DAC, as shown in Fig.
1(b). However, this architecture also requires locking time for a
frequency switch. Furthermore, the usage of the VCO without
a feedback loop for control voltage can cause frequency errors
due to process, voltage, and temperature (PVT) variations. The
above mentioned frequency synthesizers do not have constant
locking times as the target frequency of the frequency
synthesizer keeps changing. This increases the complexities in
the generation of PWM signals and requires additional soft
algorithms for high-precision motion control.
In this work, the digital frequency synthesizer, which uses a
multi-phase PLL and a programmable open-loop fractional
divider, is proposed to support the burst-frequency switch.
Although the proposed frequency synthesizer uses the open
loop fractional divider, it performs high-precision frequency
synthesis that is independent of the PVT variations according
to the digital control.

978-1-4673-6853-7/17/$31.00 ©2017 IEEE

 II. PROPOSED 63-PHASE PLL-BASED DIGITAL FREQUENCY
SYNTHESIZER
The proposed digital frequency synthesizer consists of a 63-
phase PLL and programmable open loop fractional divider, as
shown in Fig. 2, to support a burst frequency switch. The PLL,
which uses the architecture of a conventional charge-pump
PLL, generates a 63-phase clock with 128 MHz frequency
using a frequency divider by eight in the feedback path when
the frequency of the input reference clock for the PLL is 16
MHz. The 63 phase clocks of the PLL have an even phase
difference with each other. The programmable open loop
fractional divider, which follows the 63-phase PLL, performs
frequency synthesis by combining and interpolating 63 clocks
supplied from the PLL. It is digitally controlled using a 14-bit
binary digital code EX_DIGIT[13:0]. The programmable open
loop fractional divider proposed in this work can perform a
burst frequency switch because it is based on a digital counter
instead of an analog circuit with negative feedback. The
proposed frequency synthesizer with a reference clock of 16
MHz frequency generates a clock with a frequency range from
16 MHz to 32 MHz using a 10-bit digital code
EX_DIGIT[13:4]. Furthermore, it supports a frequency range
from 0.5 kHz to 32 MHz using an integer frequency divider,
which is controlled by a 4-bit digital code EX_DIGIT[3:0].
A. 63-Phase Phase-Locked Loop
If the phase differences among 63 phase clocks are not
constant with each other, the phase error and time jitter of the
output clock of the proposed frequency synthesizer increase
because the programmable open-loop fractional divider
synthesizes a frequency of the output clock by combining and
interpolating the rising edges of 63 clocks supplied from the
PLL. In this work, the 63-phase PLL uses three VCOs to
increase the maximum operating frequency and to reduce the
phase error due to the mismatch of delay cells while it
generates the 63-phase clock [5][6], as shown in Fig. 3. Each
Fig. 2. Block diagram of proposed digital frequency synthesizer.
Fig. 3. Circuit diagram of 63-phase voltage-controlled oscillator.
VCO consists of 21 delay cells, and a delay cell is based on a
current starved inverter. Three VCOs are coupled with each
other using a resistor averaging network. The value of the
resistor used in the resistor averaging network affects the phase
averaging performance and time jitter owing to the changes in
rising and falling time. In this work, the values of the output
resistor of the delay cell and the resistor of the resistor
averaging network are determined to be 4 kȍ and 2 kȍ, when
the 63-phase PLL is locked with a CLK_REF having a
frequency of 16 MHz.
B. Programmable Open Loop Fractional Divider
Fig. 4 shows the conceptual timing diagram of the proposed
programmable open loop fractional divider which is based on a
direct digital period synthesis (DDPS) by combining 504 phase
clocks. The clock signal with 504 phases is generated by
interpolating by eight a 63-phase clock with 128 MHz
frequency supplied from the PLL. The clock signal CLKSYN
with a frequency from 42.66 MHz to 64 MHz is generated
using the clock signal CLKDIV3 with a frequency divided by 3
from the 128 MHz clock signal. When a digital control code
EX_DIGIT[4] is low, CLKSYN with 42.66 MHz and 64 MHz
frequencies are generated combining the rising edges of the
most lagging-phase clock and the most leading-phase clock,
respectively, among the 504 phase clocks of CLKDIV3. However,
the duty cycle ratio of CLKSYN is not determined to be 50%
except in the case that the programmable open-loop fractional
divider generates CLKSYN_MIN. Thus, the proposed frequency
synthesizer outputs the clock signal with a frequency from
21.33 MHz to 32 MHz by dividing by two the frequency of
CLKSYN. When the digital control code EX_DIGIT[4] is high,
CLKSYN has a frequency from 32 MHz to 42.66 MHz using the
same method as in the case when EX_DIGIT[4] is low. In this
case, the proposed frequency synthesizer generates the clock
signal with a frequency from 16 MHz to 21.33 MHz via the
frequency division by two for the duty cycle ratio of 50%.
Fig. 5(a) shows the frequency range of the clock signal
generated by the proposed frequency synthesizer according to a
10-bit digital code EX_DIGIT[13:4]. A clock signal with a
frequency less than 16 MHz is generated by dividing the
frequency of the clock signal with a frequency between 16
MHz to 32 MHz. This frequency division is controlled using a
4-bit digital code EX_DIGIT[3:0] and the total frequency range
from 0.5 kHz to 32 MHz is implemented by using a 14-bit
digital code EX_DIGIT[13:0] in the proposed frequency
1 cycle of 128-MHz clock
CLKPLL
(128 MHz)
504- phase clock
CLKDIV3
(128 /3 MHz)
EX_DIGIT[4] CLKSYN_MIN
=1b˅0 (42.66 MHz)
CLKSYN_MAX
( 64 MHz)
504-phase clock
CLKDIV4
(128 /4 MHz)
EX_DIGIT[4] CLKSYN_MIN
=1b˅1 ( 32 MHz)
CLKSYN_MAX
(42.66 MHz)
Fig. 4. Concept of frequency synthesis by combining 63-phase clock.
 (a)
(b)
Fig. 5. Performances of frequency-synthesized clock according to
EX_DIGIT[13:4] (a) frequency range (b) frequency resolution.
synthesizer. The frequency change in the frequency-
synthesized clock is not linear because the period of the output
clock linearly decreases on combining the rising edges of a
multi-phase clock when EX_DIGIT[13:4] linearly increases.
However, the controllable frequency resolution, which is
determined by the maximum frequency difference
implemented by the proposed frequency synthesizer, is
approximately 0.1% of the frequency of the output clock over
the 16-32 MHz frequency range, as shown in Fig. 5(b).
Furthermore, it falls below 0.1 % as the frequency of the output
clock of the frequency synthesizer becomes lower than 16
MHz.
Fig. 6 shows the block diagram and timing diagram of the
proposed programmable open-loop fractional divider. The
programmable open-loop fractional divider basically consists
of a phase selector, frequency range controller, and 2K+1
frequency divider, as shown in Fig. 6(a). The proposed open
loop fractional divider needs the 504-phase clock for the
frequency synthesis that is performed by combining the rising
edge of a multi-phase clock, as shown in Fig. 4. The phase
selector including two 63-to-1 multiplexers selects two clocks
with adjacent phases among the 63 phase clocks supplied from
the PLL using a 6-bit digital control code EX_DIGIT[13:8].
The first accumulator ACC1 in the phase selector generates the
control signal PH_SEL[5:0] so that each 63-to-1 multiplexer
combines the rising edges of the 63-phase clock. This phase
combination is performed by switching from the lagging-phase
clock to the leading-phase clock at the rising edge of the
lagging-phase clock, as shown in Fig. 6(b). It results in stable
frequency switching without the generation of any glitch noise
in the phase selector. The clock signal C_CLK, which is
confined to one phase among 504 phases, is generated via
phase interpolation by eight in the phase interpolator with two
output signals from the two 63-to-1 multiplexers, MUX_OUT0
and MUX_OUT1, using a 3-bit digital control code
(a)
(b)
Fig. 6. Proposed programmable open loop fractional divider (a) Block
diagram (b) timing diagram (@ fFS_OUT=21.56MHz).
8
7
1
M
MUX_OUT1 6 U C_CLK
X
MUX_OUT0 2
1
7 3
INT_SEL[2:0]
8
Fig. 7. Circuit diagram of phase interpolator.
EX_DIGIT[7:5]. The frequency range control logic generates
the clock signal O_CLK which has a frequency divided by 3 or
4 using the control signal FR generated using a digital control
code EX_DIGIT[4]. Finally, the proposed open loop fractional
divider generates the output clock, FS_OUT, with a frequency
range of 0.5 kHz to 32 MHz using an integer frequency divider
by 2K, which is controlled by a 4-bit digital code
EX_DIGIT[3:0] and a frequency divider by two to maintain the
duty cycle ratio of 50% for FS_OUT. According to the above
mentioned operation, the frequency switch of the proposed
frequency synthesizer is performed at the rising edge and
within one cycle of the output clock.
Fig. 7 shows the circuit diagram of the phase interpolator
used in the proposed open-loop fractional divider. The phase
interpolator has the architecture of the inverter-based digital-to-
phase converter [7] and is controlled using a 3-bit digital
control code EX_DIGIT[7:5]. Eight phase-interpolated clock
signals are connected with each other via resistors to improve
the linearity of the phase interpolation.
 III. CHIP IMPLEMENTATION AND MEASUREMENT RESULTS
The proposed digital frequency synthesizer, which supports
a burst-frequency switch, was implemented using a 0.25 ȝm
CMOS process with a 2.5 V supply. The areas of the PLL
including the band-gap reference circuit and programmable
open-loop fractional divider are 0.424 mm2 and 0.148 mm2,
respectively, as shown in Fig. 8. The total current consumption
of the proposed digital frequency synthesizer is 13 mA.
Fig. 9 shows the experimental results. The frequency of the
output clock, FS_OUT, of the proposed frequency synthesizer
increases from 2.31 MHz to 9.32 MHz and decreases from 9.32
MHz to 2.31 MHz. The frequency switch process which was
Fig. 8. Layout of implemented proposed digital frequency synthesizer.
synchronized by the external control signal, LOAD, was
performed within one cycle of FS_OUT. Furthermore, the
switched frequency of FS_OUT was updated from its rising
edge. In these cases, the stable frequency switch was also
performed within one cycle of the output clock without the
generation of any glitch noise. The measured peak-to-peak and
rms time jitter of output clock with 16 MHz frequency was
measured to be approximately 56.0 ps and 8.06 ps, respectively,
as shown in Fig. 10. The performance of the proposed digital
frequency synthesizer is compared with other state-of-the art
fractional-N clock generators in Table I.
IV. CONCLUSION
The digital frequency synthesizer, which consists of a PLL
generating a 63-phase clock and programmable open-loop
fractional divider, was proposed in this work. It performed a
burst-frequency switch within one cycle of the output clock.
The proposed digital frequency synthesizer was implemented
using a 0.25 ȝm CMOS process with a 2.5 V supply and
generated an output clock with a frequency resolution of 0.1%
over a frequency range of 0.5 kHz to 32 MHz. The measured
rms time jitter of the output clock with 16 MHz frequency is
approximately 8.06 ps.

ACKNOWLEDGMENT
(5A176 (5A176 This research was supported by the MSIP, Korea, under the
/*\ /*\ /*\ /*\ ITRC support program (IITP-2016-H8601-16-1011) and the
KIAT grant funded by the Korean government (Motie, HRD
.1#& .1#& Program for Software-SoC convergence) (No. N0001883).

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