A Hybrid Solution to Meet IEC 61000-3-2

Regulations Reprocessing a Small Part of the Total

Power
A. Fernández, D.G. Lamar, M. M. Hernando, J. Sebastián

Universidad de Oviedo, Grupo de Electrónica Industrial

Edificio 3, Campus de Viesques s/n, 33204 Gijón, SPAIN
Phone: +34 985 182 569; e-mail: arturo@ate.uniovi.es

Abstract. When a power system needs power factor correction and output voltage regulation can be very good. Fig. 1a shows the
fast output voltage regulation, two main possibilities arise: to use typical scheme of this system. As can be seen, both converters
two converters connected in cascade or to use a single converter should be designed to process the total power. Moreover, total
performing both things. In the first case, each converter performs power is processed twice. Hence, the efficiency of the whole
a different function; the first one corrects the power factor and
conversion will be around 85%-90%. It should be noted that
the second one provides fast output voltage regulation. With this
option, the total power is processed twice. In the second case, both converters must have an efficiency higher than 95% to
a single converter achieves both specifications. In this case, the achieve a 90% total efficiency. This is not so obvious for real
power is processed less than twice by the converter looking for a commercial converters.
better efficiency. This paper presents a hybrid method to reduce
the harmonic content achieving fast output voltage regulation. Another option is to use single-stage topologies [5-8]. These
Two converters are used but the one in charge of reducing the converters (Fig. 1b) are a trade-off solution when power factor
input current harmonic content only process a small part of the correction and fast output voltage regulation are needed at the
total power. Apart from the high efficiency of the system, the same time: the input current is not sinusoidal but it meets
main advantage is that the voltage across the bulk capacitor
the regulations and the output voltage dynamic response is
can be equal to peak input voltage. In the proposed solution, the
second converter is connected to an auxiliary output of the main more or less the same as in a conventional DC/DC converter.
one and is a very simple buck converter. The main drawback Another advantage of this type of converters is that most of
is that this system is slightly more complex than a single stage the output power is only processed once and only a small part
converter. A prototype for a 600 W application has been built of the total power is processed twice. Thus, the efficiency of
and tested to study the real performance of this system. single-stage converters is typically quite high and the size is
generally smaller than the size of a two stage solution. These
I. INTRODUCTION advantages are especially remarkable for low and medium
Power Factor Preregulators are one of the most widely used power levels. Total efficiency can be around 92% using a
power converters nowadays. There are many reasons for
that. The input current waveform is sinusoidal and hence, the
injection of current harmonics to the line is very low. Thus,
compliance with international regulations such as IEC 61000-
3-2 and IEEE 519 is almost sure for the whole range of power
levels, even if those regulations change in the future. Another
advantage is that these circuits can be used with universal
input voltage range [1]. The main disadvantage is the poor
output voltage dynamics. As is known, this is due to the low
pass filter placed in the voltage feedback path. This filter
is needed to reduce the Total Harmonic Distortion (THD)
of the input current waveform and to improve the power
factor. If the output voltage of the error amplifier (Vea) has
a strong 100 Hz ripple, the input current will be distorted.
Then, the filter is used to reduce this ripple and improve the
input current waveform [2-4]. If the application needs a tight
and fast output voltage regulation, a second stage placed in
cascade is needed. This second converter can be any dc-to-
dc converter and the dynamic characteristics of the whole
Fig. 1: a) Two stage converter scheme; b) single-stage converter scheme
power stage will be determined by the second stage. Thus, the
converter with the same efficiency as the second stage of
the previous example. As a consequence, efficiency can be 2
points higher keeping a small size of the total system.
Nevertheless, single stage solutions have two main
drawbacks:
• The energy which is processed twice is generally
sent back to the input. Typically, the main consequence of this
is that the voltage across the bulk capacitor is higher than the
peak input voltage. Then, if this voltage is too high, the stress
on the semiconductors will also increase a lot and hence, the
behaviour of the circuit will be quite poor. In the best cases,
the bulk capacitor voltage can be 1.3 times higher than the
peak input voltage. However, this can rise up to 2.5 times in
the worst cases.
• Due to the uncontrolled values of the voltage across
the bulk capacitor, it is very difficult to optimize a single stage
converter for universal input voltage specifications. Hence,
they are mostly used with narrow input voltage ranges as the
European (190 - 250 V) or the American (85 - 130 V). The
reason is simple: in the best case, the maximum voltage across
the bulk capacitor can be near 500 V and the minimum input
voltage would be around 120 V. Hence, the DC/DC converter
will deal with a 1:4 input voltage ratio
In practice, two-stage and single-stage converters are the
main active options to achieve power factor correction and
fast output voltage regulation for power levels higher than
200 W. This paper presents a hybrid active solution in which
an independent converter is used to correct the power factor.
Hence, it cannot be strictly considered as a single stage
solution. However, this converter only process a small part
of the total power and hence, the efficiency is inherently
high. Furthermore, the size is also smaller than the front-end
of a two stage system and also simpler. In fact, the second
converter will be a conventional buck converter which is
connected to an auxiliary output of the main DC/DC stage.
The efficiency is the same as in a single stage converter
and the voltage across the bulk capacitor can be controlled.
Obviously, this is achieved increasing a little the complexity
of the converter.
II. PARTIAL POWER PROCESSING CONCEPT
When a two-stage converter is used, the whole output power
goes through two separate processes: first through the power
factor corrector and afterwards through the second dc-to-dc
converter. Hence, the efficiency of the whole system will be
the product of the efficiencies of both converters and, as a
consequence, very high efficiencies are needed on both steps
to achieve a good efficiency in the whole process.
The idea of the partial power processing concept comes from
the passive solutions used to correct the power factor. If an
inductor [9] or even a resistor [10] is placed between the input
rectifier and the bulk capacitor as shown in Fig.2a, the input
current will be quite smooth and its harmonic content will be
low. As is known, IEC 61000-3-2 regulations can be easily
meet with this system for low power levels [9-10]. However,
when the power is higher than 300 W, losses on those
components are very high and the system is less interesting.
Although the concept of placing an impedance between the
rectifier and the capacitor is still useful for high power levels,
the practical implementation with real impedances does not
work.
Nevertheless, an active impedance with lower losses could be
placed there to perform the same function. In fact, the output
of a converter could be that impedance as shown in Fig.2b.
As can be seen, the converter is not placed in series with
the input as in the two-stage system. Moreover, the power
processed by it will be the product of the input current of the
system (note that this current is also the output current of the
converter) and the output voltage of the converter. It can be
easily seen that, if this voltage is lower than the input voltage,
the power processed by this converter will be lower than the
input power. Hence, the total power will be processed less
than twice. As will be shown later, the power undergoing a
second process can be lower than 10%. Then, even though
the converter was not very efficient (say around 80%), the
efficiency penalty of the whole system will be very small.
Furthermore, the size of this converter will also be smaller
than the typical first stage used to correct the power factor
because its rated power will be only 10% of the total.
If the auxiliary converter is as shown in Fig. 2b, its input
voltage will be as high as in the case of the main converter.
Furthermore, as galvanic isolation is needed and the power
processed is very low, the best choice will be typically
a Flyback converter. This means that the semiconductor
voltage stress will be around 600 V and hence, 800 V devices
are needed. As a consequence, efficiency will be penalized
because 800 V devices have lower performance than 600 V
a) Impedance: R or L
ig
ig
DC/DC
Line
converter
LOAD
Impedance created by
the converter
b)
ig
DC/DC
ig
Line DC/DC
converter
LOAD
DC/DC
Main
Transformer
c)
ig Impedance
created by the
converter
DC/DC
i
g
Line
converter
LOAD
Fig. 2: a) Passive PFC solution to reduce the harmonic content at low
power levels; b) active solution based on using a converter to emulate an
impedance in series with the input; c) proposed solution based on connect-
ing the auxiliary converter to an output of the main converter.
devices.
To overcome this issue, the auxiliary converter can be
connected to an auxiliary output of the main one as shown
in Fig. 2c. As the turns ratio of this output can be chosen, the
input voltage of the auxiliary converter can be decided by the
designer.
This solution has some advantages and some drawbacks.
The auxiliary voltage obtained from the main converter
will be much lower than the voltage across the main bulk
capacitor. Typically, this voltage will be around 150 V. As a
consequence, the devices used in the auxiliary converter can
be rated to around 200 V, which is very interesting. However,
the system shown in Fig. 2b can be designed independently
of the main converter as a separate module. In fact, the same
module could be used for many different applications. It
could even be designed as an external module and connected
to the main converter if needed. In the case of the proposed
system, the main converter and the auxiliary one should be
designed altogether. This means that, if a company wanted
to implement the system in an existing product, even though
the main converter will have only a slight modification (the
addition of an auxiliary output), the whole printed board
should be re-designed and, in practice, the length of the
project would be longer.
III. AUXILIARY CONVERTER BASED ON THE BUCK CONVERTER
When this system is used, the auxiliary output of the main
converter lowers the input voltage of the auxiliary converter
and hence, the MOSFET and the diode can be rated to a
low voltage. From the point of view of the efficiency of the
module, this is very important. As no galvanic isolation is
needed, the buck converter is the best option because it is
a very simple topology and the potential efficiency is the
highest possible. Furthermore, as the topology is simple, the
The consequence of this is that the equivalent circuit placed
between the input rectifier and the bulk capacitor is as shown
in Fig, 3b. The effect of the RLF is dramatic because the input
current will be formed by pieces of a sinusoidal waveform as
shown in Fig. 3c:
Vg ( wt ) + VS − VC (3)
ig ( wt ) =
RLF
where VC is the voltage across the bulk capacitor. It should
be noted that inductor Ld needs a coupled winding and a
diode to demagnetize because, when the MOSFET is off, the
Ld current needs to keep flowing and, otherwise, it would be
impossible. This is interesting because the energy stored in
Ld is recovered as far as is sent to the input capacitor. As the
equivalent circuit of the output voltage consists of a voltage
source (VS) and a Loss-Free-Resistor, we have called this
converter the Buck VLFR module.
The period of time during which the input current is flowing is
called conduction angle (фC). It has already been demonstrated
in [1-3] that this type of waveform can meet IEC 61000-3-2
regulations by selecting a proper conduction angle in nominal
conditions. Class A is less restrictive for low power levels
because the limits are absolute and are high enough so that
a 3kW converter can meet the regulations. Hence, it is really
easy to meet the regulations for a 500 W converter. Class D
is much more restrictive because limits are relative to input
power. In this paper we will show designs for Class D, which
is more complicated, in order to show the competitiveness
of this system. In fact, the conduction angle needed with this
a)
Ld
L1
VBuck
VAux

size is also small.

Buck VLFR module
However, a conventional buck converter cannot be directly
used because the impedance placed between the input rectifier b) Buck Main
and the bulk capacitor of the main converter will be just a VLFR Transformer

voltage source. In that case, the harmonic content of the input VBuck
ig
current will not be reduced. However, if a small inductor (Ld)
operating in the Discontinuous Conduction Mode (DCM) is VS RLF
placed at the input of the auxiliary converter, as shown in Fig. DC/DC
Vg
3a, the output of the auxiliary converter behaves as a voltage VC Main LOAD
converter
source (VS) plus a Loss-Free-Resistor (RLF).
VBuck = VAux ⋅ d − LD ⋅ fS ⋅ ig (1)
This equation can be written in the following form: c)
Vg(ωt)
VBuck = VS − RLF ⋅ ig (2) VC-VS

where VS = VAux ⋅ d and RLF = LD ⋅ fS .

The effect of the inductor is similar to the effect of the
leakage inductance in any converter with galvanic isolation: ig(ωt)
the output voltage is reduced. Furthermore, this reduction is
proportional to the current passing through it and hence, it φC
behaves as a “resistor”. Obviously, as it is not a real resistor Fig. 3: a) scheme of the buck converter with a delaying inductor; b) equiva-
lent circuit of the auxiliary converter placed between the input rectifier and
(it just behaves as it was) it has no losses.
the bulk capacitor.
 a) fC
100
VC − VS = Vg cos (5)
2
CONDUCTION ANGLE (º)

80
The value of VS depends on the control strategy of the
60 system. This issue is interesting because it represents the
main advantage of this system in comparison with single
40
250 V stage topologies. As the control system is independent, we
230 V can decide the parameter to control. Hence, the auxiliary
20
190 V converter can be controlled in such a way that the voltage
200 400 600 across the bulk capacitor is equal to peak input voltage (VC =
b) OUTPUT POWER (W) Vg). In this case, the main converter will have the same input
8 voltage level that a conventional ac-to-dc converter with no
PFC. In this case, the value of VS needed would be as shown
PEAK CURRENT (A)

6 in Fig. 4c. As can be seen, the maximum value is 72 V. This

voltage is needed to calculate the auxiliary voltage that should
4 be obtained from the main converter (VAux). In the case of the
250 V buck converter:
230 V
2 VS = VAux ⋅ d (6)
190 V

100 200 300 400 500 600 The only constraint is that VAux should be higher than the
c) OUTPUT POWER (W) maximum VS value. As usual, there is a trade-off between
75 stress on the semiconductors and complexity of the driver. The
60 trade-off would be around a maximum duty cycle of 0.5 and a
VS VALUE (V)

45
VAux value around 140 V. This means that 200 V devices could
be used for this application, which is much more interesting
250 V
30 than using high voltage devices in other solutions.
230 V
15 190 V
The power processed by the buck VLFR module can be easily
200 400 600
OUTPUT POWER (W)
Fig. 4: a) input current conduction angle for a design for the European volt-
a) 40

age range; b) peak value of the input current for any operating condition
250 V
(power level + input voltage); c) value of the voltage VS that appears on 30
230 V
the equivalent circuit of the buck VLFR. 190 V
type of waveform is only 75º to meet Class D regulations. It 20
should be noted that the angle is the same for any power level
due to the fact that the limits are relative.
To obtain this angle at nominal conditions (nominal input 10
voltage and nominal power), the values of VS and RLF must
be chosen. The expression of the input power as a function
of the conduction angle and the peak input voltage Vg can be 100 200 300 400 500 600
OUTPUT POWER (W)
obtained:
b) 6
Vg 2 (4)
P = ⋅ ( f C − sin f C )
EFFICIENCY PENALTY (%)

2 ⋅ p ⋅ RLF

Hence, the value of RLF can be directly calculated from (4).

In the case of a 600 W prototype, this value is 9.6Ω. Once 4

RLF is known, (4) can be used to calculate the value of the

conduction angle for any operation condition (input voltage
+ power level). Fig. 4a shows the value of фC for the whole 2 250 V
power range and three input voltage levels (190 V, 230 V and 230 V
250 V). As can be seen, фC adapts to the power level and 190 V
increases when the power demand increases. Fig. 4b shows
the peak input current value. 100 200 300 400 500 600
OUTPUT POWER (W)
Fig. 5: a) absolute value of the power recycled by the buck VLFR for a Eu-
The value of VS can be calculated from the following
ropean range design; b) power recycled by the buck VLFR module related
expression: to the input power.
calculated multiplying the input current waveform by (VC
- Vg) and obtaining its average value and is shown in Fig. a) 150

POWER PROCESSED TWICE (W)

250 V
5a (absolute value) and Fig. 5b (relative to input power). As
can be seen, the module processes a very small part of the 85 V
100
total power: 35 W in the worst case, which represents 6%
of the total power (600 W). Obviously, the size of this 35 W
converter will be really small in comparison with the main
600 W converter. 50

Furthermore, as the module has an independent control

circuit, we have much more flexibility to make other designs. 100 200 300 400 500 600
It should be noted that this could not be done in single-stage OUTPUT POWER (W)
converters. This fact could be used to improve the behaviour b) 25

with universal input voltage, which is the main drawback 250 V

of single-stage converters. Typical designs shown in the

EFFICIENCY PENALTY (%)

literature exhibited voltages across the bulk capacitor around
500 V in the best cases. As the minimum peak voltage is 120
V, the ratio raised up to 1 : 4.9 (the ripple on the capacitor
has been taken into account). Apart from the operation
of the PFC circuit, the fact of increasing the input voltage
range has a negative effect on the efficiency. From our
experiments, a converter designed for universal input voltage
range will have an efficiency around 2 points lower than a
converter designed for the European voltage range. Hence,
the global improvement of the proposed system will be quite
important.
If the buck VLFR is used for universal input voltage, the
maximum input voltage of the main converter will be 265•√2
= 375 V. Moreover, the minimum input voltage will be around
85•√2•0.85 = 100 V. In this case, the ratio is 1:3.6, which means
that the main converter can have a much better behaviour
than in the case of a single-stage one and the efficiency will
be higher due to this reason. As can be seen, this not a serious
problem any more if the buck VLFR system is used. However,
there is still another issue to solve. Fig. 6a shows the recycled
energy for the minimum input voltage. As the conduction
angle increases to 160º, the energy processed by the module
is 120 W at maximum input power, which means around 20%
of the total power (Fig. 6b). Hence, the size of the module
will not be so small and the potential efficiency will not be so
high. A solution for this is to make the buck VLFR operate at
two different switching frequencies: f1 (e.g 100 kHz) for the
low input voltage range and twice that value for the higher
20
85 V
15
10
5
100 200 300 400 500 600
OUTPUT POWER (W)
Fig. 6: a) absolute value of the power recycled by the buck VLFR for a
universal input voltage range design; b) power recycled by the buck VLFR
module related to the input power.
It is important to analyze the current passing through these
inductors in order to make a good physical design. Although
they are operating at the switching frequency, their envelope
waveform is the 50 Hz sinusoidal waveform seen at the input.
Furthermore, the high frequency ripple needed to calculate
the core losses changes according to the instantaneous current
level. Table I shows the most significant values needed to
design both inductors. As can be seen, an E20 core can be
used in both cases. Fig. 7 shows the high frequency current
ripple on the inductors, which has been used to calculate
the core losses. As can be seen in Table I, copper losses are
much more significant in the design of these inductors. As a
consequence, the type of material used in the core will not
have too much influence in the performance.
HF AC component of the input current (A)

input voltage range. As a consequence, the RLF is changed 1.5

(1) and the conduction angles will be almost equal for both
1
ranges. Hence, the recycled energy will be approximately the
same in both cases. 0.5

0
As can be seen in (1) and (2), the value of the RLF depends on
the switching frequency of the Buck VLFR module and the 0.5

auxiliary inductor Ld. In our case, the switching frequency is 1

200 kHz and hence, the inductor needed is 48 μH. 1.5
Regarding the filter inductor, its value is not critical at all 0 5 ms 10 ms
because its purpose is just to keep some current flowing at Time (ms)
Fig.7: high frequency current ripple on the inductors of the buck VLFR
the output. However, it is interesting to keep its value at least
during a line period
equal to Ld.
 TABLE I: MOST SIGNNIFICANT CURRENT VALUES ON LD AND L1

Freq. = 200 kHz Ld = 50µH L1 = 50 µH

Ipeak 6,9 A 6,9 A

Irms 1,92 A 2,92 A

Iac 0,97 A 0,22 A

Core Type E20 E20

Copper Losses 0,175 W 0,4 W

Core Losses ≈0 ≈0

TOTAL Losses 0,179 W 0,4 W

V. EXPERIMENTAL RESULTS
A prototype of the Buck VLFR module has been designed
for a 600 W server application. In order to comply with IEC
61000-3-2 Class D regulations, the nominal conduction angle
will be 75º. As has been mentioned, the RLF value is 9.6 Ω and
hence, the delaying inductor is 50μH. The filter inductor L1
will also have 50 μH. Both of them can be built in a E20 core
shape. The value of VS at nominal conditions is 72 V (@230 Fig.
V). Both the MOSFET and the diode were 200 V devices. 9: a) power paths on both the main converter anf the auxiliary output; b)
effciency penalty on the main converter.
As can be seen, the size of the magnetic components is very recycled through the auxiliary output. The power processed
small, especially if the power level of the main converter is by the module is only around 35 W (6% of the total power).
taken into account. Fig. 9b shows the efficiency penalty due to the Buck VLFR
module. In the prototype, the penalty was always lower than
The need of an independent control circuit is the other 4%. At nominal conditions, the efficiency penalty is only
disadvantage of this Buck VLFR module in comparison with 3%. This will be very difficult to achieve with a conventional
a single stage solution. However, the main advantage of this two-stage converter. As the power processed is very low,
system is achieved by means of this independent control the size of the module is quite small. Regarding the input
circuit because this new freedom degree allows the system current, Fig. 10a shows its waveform for nominal conditions.
to clamp the voltage across the bulk capacitor at the peak The harmonic content has been measured and IEC 60000-3-
input voltage. It should be noted that, with this design, the
maximum voltage across the bulk capacitor is only 375 V.
In the case of the best single stage solutions, the maximum
a)
voltage could be between 450 and 500 V. To achieve this, the
reference voltage of the regulator has been obtained from a
peak detector circuit connected to the input rectifier as shown
in Fig.8.

Fig. 9a shows the power paths of the system. As can be seen, the
main converter processes the full output power and also the power

b)
2.5

IEC 61000-3-2 Class D limits

RMS value (A)

Harmonic content of the waveform

1.5

0.5

0 11
3 7 15 19 23 27 31 35 39
Harmonic Order
Fig. 8: circuit used to addapt the reference voltage to the peak input voltage
and make the bulk capacitor voltage follow it. Fig. 10: a) measured input current waveform at nominal conditions; b)
measured harmonic content at nominal conditions.
2 Class D regulations have been met as can be seen in Fig.
10b.
VI. CONCLUSIONS
This paper presented an active method to reduce the harmonic
content of the input current that only process a small part of
the total power (<7%). The system is based on connecting
the output of a dc-to-dc converter between the input rectifier
and the bulk capacitor of any ac-to-dc converter. The output
impedance of the auxiliary converter makes the input
current smoother and the harmonic content is reduced. As a
consequence, IEC 61000-3-2 regulations can be easily met.
As this converter processes a small part of the total power, the
efficiency penalty of the system is much better than in a two-
stage converter. Furthermore, the efficiency of the auxiliary
converter is not critical at all. The proposed solution, which is
based on a buck converter, is connected to an auxiliary output
of the main converter. As the voltage of this output is around
150 V, the semiconductors needed for the module are only 200
V devices instead of 800 V devices used in previous solutions.
The consequence of all of this is that the size of the module
is very small. This makes this solution very competitive for
Class D applications and medium power levels. It should
be noted that, as the auxiliary converter process very low
power, its size is much smaller than the typical first stage
PFC converter. The solution is slightly more complex than
a single-stage converter because it needs an independent
control system. However, the design procedure is easier
and the voltage across the bulk capacitor can be clamped to
peak input voltage, avoiding the main disadvantage of these
converters.
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