MB130 IDTV

SERVICE MANUAL
Table of Contents
1. INTRODUCTION .......................................................................................................................................................... 3
A. General Block DIagram .............................................................................................................................................. 4
B. Placement of Blocks ................................................................................................................................................... 5
2. T/T2/C/A TUNER (U118) .............................................................................................................................................. 6
3. S/S2 TUNER (U116) OPTIONAL ................................................................................................................................. 8
4. AUDIO AMPLIFIER STAGES...................................................................................................................................... 9
A. MAIN AMPLIFIER (U123) (8W/10W/12W options).................................................................................................. 10
B. HEADPHONE AMPLIFIER (U120) .............................................................................................................................. 12
C. SCART AUDIO AMPLIFIER (U119) ............................................................................................................................. 13
5. POWER STAGE ........................................................................................................................................................... 14
A. FDC642P ................................................................................................................................................................... 16
B. NTGS3446 ................................................................................................................................................................ 16
C. RT7278G ................................................................................................................................................................... 18
D. TPS563200 ............................................................................................................................................................... 20
E. TPS54821 ................................................................................................................................................................. 22
F. AP2111 ..................................................................................................................................................................... 24
6. MICROCONTROLLER ............................................................................................................................................... 25
A. MSTAR G10 MSD95PMVW4 (U114) ........................................................................................................................ 25
7. 2GB DDR3 SDRAM .................................................................................................................................................... 33
A. Hynix H5TQ2G63GFR-TEC (U113-U110) .................................................................................................................. 33
8. 2GBIT - 4GBIT(CONNECTED OPTION) (256M X 8 BIT) NAND FLASH MEMORY .......................................... 34
A. MT29F2G08ABAEAWP (U105) ................................................................................................................................. 34
9. 16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM ............................................................................................ 36
A. KH25L1606EM2-12G Macronix SPI Flash (U115) ..................................................................................................... 36
10. USB INTERFACE ........................................................................................................................................................ 37
A. USB POWER SWITCH TPS2553-1 (U109-U117-U122) ............................................................................................. 38
11. CI INTERFACE............................................................................................................................................................ 38
12. SOFTWARE UPDATE ................................................................................................................................................ 39
A. Main Software Update ............................................................................................................................................. 39
13. TROUBLESHOOTING ................................................................................................................................................ 39
A. No Backlight Problem .............................................................................................................................................. 39
B. CI Module Problem .................................................................................................................................................. 42
C. Staying In Stand-by Mode ........................................................................................................................................ 43
D. IR Problem................................................................................................................................................................ 43
E. Keypad Touchpad Problems .................................................................................................................................... 44

1
 F. USB Problems ........................................................................................................................................................... 44
G. No Sound Problem ................................................................................................................................................... 45
H. Standby On/Off Problem ......................................................................................................................................... 46
İ. No SIgnal Problem.................................................................................................................................................... 46
14. SERVICE MENU SETTINGS ..................................................................................................................................... 48

2
 1. INTRODUCTION
17MB130 main board is driven by MStar SOC. This IC is a single chip iDTV solution that supports channel
decoding, MPEG decoding, and media-center functionality enabled by a high performance AV CODEC and
CPU.
This board can be driven just 50Hz UHD panels.
Key features include:
 Combo Front-End Demodulator
 A multi standart A/V format decoder
 The MACEpro video processor
 Home theatre sound processor
 Rich internet connectivity and completed digital home network solution
 Dual-stream decoder for 3D contents
 Mılti-purpose CPU for OS and multimedia
 Peripheral and power management
 Embedded DRAM (for connected option)

Supported peripherals are:

 1 RF input VHF I, VHF III, UHF
 1 Satellite input
 1 Side AV (CVBS, R/L_Audio)
 1 SCART socket(Common)
 1 Slim SCART socket (Optional)
 1 YPbPr (from VGA with special cable) (Optional)
 1 PC input(Common)
 3 HDMI input (with ARC option from 1st input)
 1 Common interface(Common)
 1 Optic/ Quax S/PDIF output
 1 Headphone(Common)
 2 USB(1X Side Common, 1X Side Optional) and 2x internal USB for Wifi/Bluetooth
 1 Ethernet-RJ45
 1 3way/External Touchpad/Tact Switch (Common)

3
 A. GENERAL BLOCK DIAGRAM

PWM
BACKLIGHT_DIM
3D_SYNC_OUT
KEYBOARD
SPI
PANEL_VCC

51 pins LVDS/VbyONE SOCKET

TOUCHPAD
UART
AMP_RST
1V5_VCC 1V5_VCC HP_DETECT
HP_AMP_MUTE
PC_SCL/SDA
PCM_PWR_CTRL
3D_ENABLE
STBY_ON/OFF
RX/TX_HOTEL
AUX_RESET
12V/24V_VCC
TUN_RESET
2Gb DDR3 2Gb DDR3 FLASH_WPN1
HDMI DET SYS_SCL

Speak. Connector
MEMORY MEMORY PROTECT

SPEAKERs
USB-ENABLE
BACKLIGHT SYS_SDA ESMT
PANEL_VCC AD82587D
RESET_HUB 2X6W/8W/
TUNER_RESET I2S 10W AMP
1V5_VCC

5V_VCC
DATA ADDRESS DATA
8 Lane VbyONE PWR
RAM BUS GPIOs HPHONE
LVDS/VbyONE 3
TS_IN
HP_RIGHT AD22657B HP_OUT_R
CI_TS_IN
CI SOCKET

TS BLOCK
HP_LEFT HP AMP. HP_OUT_L

AUDIO I/Os
SAV_R_IN
SAV AUDIO IN
SAV_L_IN
CI_TS_IN
TS_OUT

SPDIF_OUT

SPDIF OUT
12V_VCC

DIGITAL SAT
DVBS/S2 SC_L/R AMP

DEMOD
SC_AUD_R/L_IN
SC_L/R
H/V
Selection LNBP SYS_SCL SAT TUNER SAT I/Q
OUT

DISEQC TI Montage
22kHz TPS65233 SYS_SDA M88TS2022 SC_CVBS
OUT SC Pin8

PWR
Mstar SC FB
ResetN

SC_RGB
RF

1V1_VCC
4

VIDEO I/Os
LNB_SUP 3V3_VCC
G10V SC_CVBS
IN
SCART
ETHERNET

BAV_CVBS
IN SAV CVBS IN
DVD_CVBS
IN

ET_T
23X23 VGA_RGB
ET_R

VGA
VGA HS/VS
3V3_VCC

XTAL
ANALOG
DIGITAL/
DEMOD

RF TUNER 24 MHz

Si2151 DIGITAL/ANALOG_IF

PWR
2
3V3_VCC
SYS_SCL

SYS_SDA

Keyboard
USB 4

GPIOs
STBY
2.0

IR – Led1/2
Keyboard Socket
USB_BT_DP

USB 3 USB 2 USB 1 PWR SPI

HDMI 1 HDMI 2 HDMI 3 NAND
USB_BT_DN

2.0 2.0 2.0 1 FLASH

KEYBOARD Led/IR Socket

VGA
HDMI
USB2_DN
USB2_DP

USB1_DN
USB1_DP

3V3_STBY
HDMI 5V

HDMI 5V
STBY_ON/OFF
HDMI 5V
USB_WIFI_DN
USB_WIFI_DP

TMDS

TMDS

TMDS
ARC

CEC

I2C
I2C

I2C

MX25l512
HDMI 1 HDMI 2 HDMI 3 NAND FLASH
512MB

USB2 USB1
5V_VCC 5V_VCC

4
 B. PLACEMENT OF BLOCKS

Power
Con. CI FLAS
H

L
V
D
S
C
O
n USB

SPI
RAM MAIN
IC

Sat. Tuner SAV

HDMI
RJ45 Connectors

VGA Tuner
S/PDIF HP

Keyb 3-WAY
oard SW
SCART
CON

Internal
LED Audio SPEAK. Wifi& BT
CON Amp CON Connector

5
 2. T/T2/C/A TUNER (U118)

Description:
The Si2151 is Silicon Labs' sixth-generation hybrid TV tuner supporting all worldwide terrestrial and cable
TV standards. Requiring no external balun, SAW filters, wirewound inductors or LNAs, the Si2151 offers the
lowest-cost BOM for a hybrid TV tuner. Also included are an integrated power-on reset circuit and an option
for single power supply operation. As with prior-generation Silicon Labs TV tuners, the Si2151 maintains very
high linearity and low noise to deliver superior picture quality and a higher number of received stations when
compared to other silicon tuners. The Si2151 offers increased immunity to WiFi and LTE interference,
eliminating the need for external filtering. For the best performance with next-generation digital TV standards,
such as DVB-T2/C2, the Si2151 delivers industry-leading phase noise performance.

Features:
 Worldwide hybrid TV tuner
o Analog TV: NTSC, PAL/SECAM
o Digital TV: ATSC/QAM, DVBT2/T/C2/C, ISDB-T/C, DTMB
 1.7 MHz, 6 MHz, 7 MHz, 8 MHz, and 10 MHz channel bandwidths
 42-1002 MHz frequency range
 Industry-leading margin to A/74, NorDig, DTG, ARIB, EN55020, OpenCable™,DTMB
 Lowest BOM for a hybrid TV tuner
o No balun, SAW filters, or external inductors required
o Increased ESD protection on 4pins
 Best-in-class real-world reception
o Lowest phase noise
o High Wi-Fi and LTE immunity
 Low power consumption
o 3.3 V and 1.8 V power supplies
o Integrated 1.8 V LDO for 3.3 V singlesupply operation
 Integrated power-on reset circuit
 Standard CMOS process
 3x3 mm, 24-pin QFN package
 RoHS compliant

Figure 1.1 Si2151 Pin description

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7
 3. S/S2 TUNER (U116) OPTIONAL

Description

Figure: Pin description

Features
 Single-Chip tuner
 Compliant with DVB-S2 and ABS-S standards
 Support PSK, (PSK and 16APSK
 Direct-conversion from L-band to baseband
 Symbol rate:1 to 45 Msybol/s
 Integrated VCOs and PLL, with on-chip inductors varactors and loop filter
 Integrated RF AGC for optimal performance
 Integrated baseband DC offset cancellation removes external loop filters
 Excellent immunity to strong adjacent undersired channels
 Integrated clock driver provides auxiliary divided clock output for other devices
 Selectable RF bypass
 Support sleep mode
 2-wire serial bus with 3.3V compatible logic levels
 Power supply+3.3V
 28-pin QFN package
 RoSH compliant

8
Block Diagram

4. AUDIO AMPLIFIER STAGES

Figure: The block diagram of the audio part

9
 A. MAIN AMPLIFIER (U123) (8W/10W/12W OPTIONS)

Description
AD82587D is a digital audio amplifier capable of driving a pair of 8 ohm, 20W or a single 4 ohm, 40W
speaker, both which operate with play music at a 24V supply without external heat-sink or fan requirement.
Using I2C digital control interface, the user can control AD82587D’s input format selection, DRC (dynamic
range control), mute and volume control functions. AD82587D has many built-in protection circuits to
safeguard AD82587D from connection errors.
Features
 16/18/20/24-bit input with I2S, Left-alignment and Right-alignment data format
 PSNR & DR(A-weighting) Loudspeaker: 97dB (PSNR), 105dB (DR) @ 24V
 Multiple sampling frequencies (Fs)
 32kHz / 44.1kHz / 48kHz and
 64kHz / 88.2kHz / 96kHz and
 128kHz/176.4kHz/192kHz
 System clock = 64x, 128x, 256x, 384x, 512x, 768x,1024x Fs
 256x~1024x Fs for 32kHz / 44.1kHz / 48kHz
 128x~512x Fs for 64kHz / 88.2kHz / 96kHz
 64x~256x Fs for 128kHz /176.4kHz/192kHz

 Supply voltage
 3.3V for digital circuit
 10V~26V for loudspeaker driver
 Loudspeaker output power for Stereo@ 24V
 10W x 2ch into 8_ @ 0.16% THD+N
 15W x 2ch into 8_ @ 0.18% THD+N
 20W x 2ch into 8_ @ 0.24% THD+N
 Loudspeaker output power for Mono@ 24V
 20W x 1ch into 4_ @ 0.17% THD+N
 30W x 1ch into 4_ @ 0.2% THD+N
 40W x 1ch into 4_ @ 0.24% THD+N
 Sounds processing including:
 Volume control (+24dB~-103dB, 0.125dB/step)
 Dynamic range control
 Power clipping
 Channel mixing
 User programmed noise gate with hysteresis window
 DC-blocking high-pass filter
 Anti-pop design
 Short circuit and over-temperature protection
 I2C control interface with selectable device address
 Internal PLL
 LV Under-voltage shutdown and HV Under-voltage
 detection
 Power saving mode
 Dynamic temperature control

10
 Figure 3.2: Pin description

Figure 3.3: Functional Block Diagram

Table3.1: Absolute Maximum Ratings

11
 Table3.2: Recommended Operating Conditions

B. HEADPHONE AMPLIFIER (U120)

Description
The AD22657B is a 2-Vrms cap-less stereo line driver. The device is ideal for single supply electronics.
Cap-less design can eliminate output dc-blocking capacitors for better low frequency response and save cost.
The AD22657B is capable of delivering 2-Vrms output into a 10k ohm load with 3.3V supply. The gain
settings can be set by users from 1V/V to 10V/V externally. The AD22657B has under voltage protection to
prevent POP noise. Build-in shutdown control and de-pop control sequence also help AD22657B to be a pop-
less device.
The AD22657B is available in a 10-pin MSOP package.

Features
 Operation Voltage: 3V to 3.6V
 Cap-less Output
o Eliminates Output Capacitors
o Improves Low Frequency Response
o Reduces POP/Clicks

 Low Noise and THD

o Typical SNR 107dB
o Typical Vn 7uVrms
o Typical THD+N < 0.02%

 Maximum Output Voltage Swing into 2.5k Load

o 2Vrms at 3.3V Supply Voltage

 Single-ended Input
 External Gain Setting from 1V/V to 10V/V
 Fast Start-up Time: 0.5ms
 Integrated De-Pop Control
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  External Under Voltage Protection
 Thermal Protection
 Less External Components Required
 +/-8kV IEC ESD Protection at line outputs

Figure: Pin description

Table: Pin functions

Table: Recommended operating conditions

C. SCART AUDIO AMPLIFIER (U119)

AD22657B is used for scart audio amplifier, as well.

13
 5. POWER STAGE

Figure: Power Block Diagram

Figure: Power Socket and Power Options

Power socket is used for taking voltages which are 24V_VCC, 12V_STBY and 5V_STBY. These voltages
are produced in power card. Also socket is used for giving dimming, backlight and standby signals with power
card. Power socket pinning is shown in above figure.
24V_VCC goes directly to the audio part. 12V_STBY is converted several different voltages on the
mainboard which are shown in below figure.

14
 Figure: Power Block Diagram

List of the components:

 SW-1(Q105) → FDC642P
 SW-2(Q100) → NTGS3446
 DC-DC-1(U101) → RT7278G
 DC-DC-2(U100) → TPS563200
 DC-DC-3(U107) → TPS563200
 DC-DC-4(U103) → TPS54821
 DC-DC-5(U104) → TPS563200
 LDO-1(U112) → AP2111H

15
 A. FDC642P

Figure: Pin description

B. NTGS3446
Features
 Ultra Low RDS(on)
 Higher Efficiency Extending Battery Life
 Logic Level Gate Drive
 Diode Exhibits High Speed, Soft Recovery
 Avalanche Energy Specified
 IDSS Specified at Elevated Temperature
 Pb−Free Package is Available

APPLICATIONS
 Power Management in portable and battery−powered products, i.e. computers, printers, PCMCIA cards,
cellular and cordless
 Lithium Ion Battery Applications
 Notebook PC

16
 Figure 4.7: Pin description

Table 4.8: Maximum ratings

17
 C. RT7278G

Figure: Pin Assignment

18
19
 D. TPS563200

Figure: Pin Assignment

20
Electrical Characteristics

21
 E. TPS54821

General Description
The TPS54821 in thermally enhanced 3.5 mm x 3.5 mm QFN package is a full featured 17 V, 8 A
synchronous step down converter which is optimized for small designs through high efficiency and integrating
the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which
reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint. The
output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power
supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the
open drain power good pins. Cycle by cycle current limiting on the high-side FET protects the device in
overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There
is also a low-side sinking current limit which turns off the low-side MOSFET to prevent excessive reverse
current. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset
time. Thermal hiccup protection disables the device when the die temperature exceeds the thermal shutdown
temperature and enables the part again after the built-in thermal shutdown hiccup time.

Features
 Integrated 26 mΩ / 19 mΩ MOSFETs
 Split Power Rail: 1.6 V to 17 V on PVIN
 200 kHz to 1.6 MHz Switching Frequency
 Synchronizes to External Clock
 0.6V ±1% Voltage Reference Over Temperature
 Low 2 μA Shutdown Quiescent Current
 Monotonic Start-Up into Pre-biased Outputs
 –40°C to 125°C Operating Junction Temperature Range
 Adjustable Input Undervoltage Lockout
 Adjustable Slow Start/Power Sequencing
 Power Good Output Monitor for Undervoltage and Overvoltage
 Adjustable Input Undervoltage Lockout

APPLICATIONS
 Digital TV Power Supplies
 Set Top Boxes
 Blu-ray DVDs
 Home Terminals

22
 Table 4.5: Recommended operating conditions

Figure 4.5 : Pin Description

23
 Table 4.6: Pin functions.

F. AP2111
General Description
The AP2111 is CMOS process low dropout linear regulator with enable function, the regulator delivers a
guaranteed 600mA (Min) continuous load current. The AP2111 provides 1.2V, 1.8V, 2.5V, 3.3V, 4.8V
regulated output and 0.8V to 5V adjustable output, and provides excellent output accuracy 1.5%, it is also
provides a excellent load regulation, line regulation and excellent load transient performance due to very fast
loop response. The AP2111 has built-in auto discharge function. The AP2111 features low power consumption.
The AP2111 is available in SOIC-8, PSOP-8 SOT-223 and SOT-23-5 packages.
Features
 Output Voltage Accuracy: ±1.5%
 Output Current: 600mA (Min)
 Foldback Short Current Protection: 50mA
 Enable Function to Turn On/Off VOUT
 Low Dropout Voltage (3.3V):
 250mV (Typ) @ IOUT=600mA
 Excellent Load Regulation: 0.2%/A (Typ)
 Excellent Line Regulation: 0.02%/V (Typ)
 Low Quiescent Current: 55μA (Typ)
 Low Standby Current: 0.01μA (Typ)
 Low Output Noise: 50μVRMS
 PSRR: 65dB @ f=1kHz, 65dB @ f=100Hz
 OTSD Protection
 Stable with 1.0μF Flexible Cap: Ceramic, Tantalum and Aluminum Electrolytic
 Operating Temperature Range: -40°C to 85°C
 ESD: MM 400V, HBM 4000V

24
 6. MICROCONTROLLER

A. MSTAR G10 MSD95PMVW4 (U114)

Description

Features

25
26
27
28
29
30
31
 Table: Recommended operating condition

32
 7. 2GB DDR3 SDRAM

A. HYNIX H5TQ2G63GFR-TEC (U113-U110)

Description
The H5TQ2G63GFR is a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of
the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the
CK), Data, Data strobes and Write data masks inputs are sam-pled on both rising and falling edges of it. The
data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Features
 VDD=VDDQ=1.5V +/- 0.075V
 Fully differential clock inputs (CK, CK) operation
 Differential Data Strobe (DQS, DQS)
 On chip DLL align DQ, DQS and DQS transition with CK transition
 DM masks write data-in at the both rising and falling edges of the data strobe
 All addresses and control inputs except data, data strobes and data masks latched on the rising edges of
the clock
 Programmable CAS latency 6, 7, 8, 9, 10, 11, 12 and 13 supported
 Programmable additive latency 0, CL-1, and CL-2 supported
 Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
 Programmable burst length 4/8 with both nibble sequential and interleave mode
 BL switch on the fly
 8banks
 Average Refresh Cycle (Tcase 0oC ~ 95oC)
o 7.8 μs at 0oC ~ 85oC
o 3.9 μs at 85oC ~ 95oC
 Auto Self Refresh supported Driver strength selected by EMRS
 JEDEC standard 96ball FBGA(x16) Asynchronous RESET pin supported
 Driver strength selected by EMRS TDQS (Termination Data Strobe) supported (x8 only)
 Dynamic On Die Termination supported 8 bit pre-fetch
 Asynchronous RESET pin supported
 ZQ calibration supported
 Write Levelization supported
 On Die Thermal Sensor supported
 8 bit pre-fetch
33
Memory Configuration of MB130

Memory Config
SoC NAND SPI
Name RAM Internal RAM external Flash Flash
Connected G10 2X2GBit 2X4Gbit 4Gbit 2MByte
Non-Connected G10V NA 2X2Gbit 2Gbit 2MByte

8. 2GBIT - 4GBIT(CONNECTED OPTION) (256M X 8 BIT) NAND FLASH

MEMORY

A. MT29F2G08ABAEAWP (U105)
Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations.
These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five
control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional
signals control hardware write protection and monitor device status (R/B#). This hardware interface creates a
low pin-count device with a standard pinout that remains the same from one density to another, enabling future
upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable
signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can
independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred
to as a logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see
Device and Array Organization. This device has an internal 4-bit ECC that can be enabled using the GET/SET
features or by factory (always enabled). See Internal ECC and Spare Area Mapping for ECC for more
information.

Features
 Open NAND Flash Interface (ONFI) 1.0-compliant
 Single-level cell (SLC) technology
 Organization
o Page size x8: 2112 bytes (2048 + 64 bytes)
34
 o Page size x16: 1056 words (1024 + 32 words)
o Block size: 64 pages (128K + 4K bytes)
o Plane size: 2 planes x 1024 blocks per plane
o Device size: 2Gb: 2048 blocks
 Asynchronous I/O performance
t
o RC/tWC: 20ns (3.3V), 25ns (1.8V)
 Array performance
o Read page: 25μs
o Program page: 200μs (TYP: 1.8V, 3.3V
o Erase block: 700μs (TYP)
 Command set: ONFI NAND Flash Protocol
 Advanced command set
o Program page cache mode
o Read page cache mode
o One-time programmable (OTP) mode
o Two-plane commands
o Interleaved die (LUN) operations
o Read unique ID
o Block lock (1.8V only)
o Internal data move
 Operation status byte provides software method for detecting
o Operation completion
o Pass/fail condition
o Write-protect status
 Ready/Busy# (R/B#) signal provides a hardware method of detecting operation completion
 WP# signal: Write protect entire device
 First block (block address 00h) is valid when shipped from factory with ECC. For minimum required
ECC, see Error Management.
 Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000
 RESET (FFh) required as first command after poweron
 Alternate method of device initialization (Nand_Init) after power up (contact factory)
 Internal data move operations supported within the plane from which data is read
 Quality and reliability
o Data retention: 10 years
 Operating voltage range
o VCC: 2.7–3.6V
35
 o VCC: 1.7–1.95V
 Operating temperature:
o Commercial: 0°C to +70°C
o Industrial (IT): –40ºC to +85ºC
 Package
o 48-pin TSOP type 1, CPL63-ball VFBGA

Table: Recommended operating conditions

9. 16M-BIT [16M X 1] CMOS SERIAL FLASH EEPROM

A. KH25L1606EM2-12G MACRONIX SPI FLASH (U115)

Description
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO).
Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins
become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page
basis, or word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The
status read command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions; please see security features section
for more details.
When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes
Macronix's proprietary memory cell, which reliably stores memory contents even after typical 100,000
programs and erase cycles.

Features
 Single Power Supply Operation
o 2.7 to 3.6 volt for read, erase, and program operations
 Serial Peripheral Interface compatible -- Mode 0 and Mode 3
 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure
 512 Equal Sectors with 4K byte each

36
 o Any Sector can be erased individually
 32 Equal Blocks with 64K byte each
o Any Block can be erased individually
 Program Capability
o Byte base
o Page base (256 bytes)
 Latch-up protected to 100mA from -1V to Vcc +1V

Figure: Pin configuration

Table: Pin description

10. USB INTERFACE

37
 A. USB POWER SWITCH TPS2553-1 (U109-U117-U122)

11. CI INTERFACE
17MB130 Digital CI ve Smart Card Interface Block diagram:

38
 Figure: CI interface

12. SOFTWARE UPDATE

A. MAIN SOFTWARE UPDATE

In MB98 project, please follow software update procedure:

1. mb130_en.bin, mb130_RomBoot.bin, mb130_PM51.bin and usb_auto_update_G10.txt documents should

be copied directly inside of a flash memory (not in a folder).
2. Insert flash memory to the TV when TV is powered off.
3. While pushing the OK button in remote control, power on and wait. TV will power-up itself.
4. If First Time Installation screen comes, it means software update procedure is successful.

13. TROUBLESHOOTING

A. NO BACKLIGHT PROBLEM
Problem: If TV is working, led is normal and there is no picture and backlight on the panel.
Possible causes: Backlight pin, dimming pin, backlight supply, stby on/off pin
BACKLIGHT_ON/OFF pin should be high when the backlight is ON. Collector pin of Q113 must be low
when the backlight is OFF. If it is a problem, please check Q106. Also it can be tested in TP108 in main board.
Please also check panel cables.

39
 Dimming pin should be high or square wave in open position. If it is low, please check S122 for Mstar side.
It also can be checked at TP106. Please also check panel or power cables and connectors.

Backlight power supply should be in panel specs. Please check Q124, shown below; also it can be checked
TP112.

40
 STBY_ON/OFF should be low for TV on condition, please check Q114’s collector.

41
 B. CI MODULE PROBLEM
Problem: CI is not working when CI module inserted.
Possible causes: Supply, suply control pin, detects pins, mechanical positions of pins.
 CI supply should be 5V when CI module inserted. If it is not 5V please check CI_PWR_CTRL, this pin
should be low.

 Please check mechanical position of CI module. Is it inserted properly or not?

 Detect ports should be low. If it is not low please check CI connector pins, CI module pins.

42
 C. STAYING IN STAND-BY MODE
Problem: Staying in stand-by mode, no other operation.
This problem indicates a short on Vcc voltages. Protect pin should be logic high while normal operation.
When there is a short circuit protect pin will be logic low. If you detect logic low on protect pin, unplug the TV
set and control voltage points with a multimeter to find the shorted voltage to ground.

D. IR PROBLEM
Problem: LED or IR not working
Check LED card supply on MB98 chasis.

43
 E. KEYPAD TOUCHPAD PROBLEMS
Problem: Keypad or Touchpad is not working
Check keypad supply on MB130.

F. USB PROBLEMS
Problem: USB is not working or no USB Detection.
Check USB Supply, It should be nearly 5V. Also USB Enable should be logic high.
USB Control is optional, so U109 and U117 may not be added. Check supply voltages only.

44
 G. NO SOUND PROBLEM
Problem: No audio at main TV speaker outputs.
Check supply voltages of 24V_VCC, VDD_AUDIO and 3V3_AMP with a voltage-meter. There may be a
problem in headphone connector or headphone detect circuit (when headphone is connected, speakers are
automatically muted). Measure voltage at HP_DETECT pin, it should be 3.3v.

45
 H. STANDBY ON/OFF PROBLEM
Problem: Device cannot boot, TV hangs in standby mode.
There may be a problem about power supply. Check main supplies with a voltage-meter. Also there may be
a problem about SW. Try to update TV with latest SW. Additionally it is good to check SW printouts via
Teraterm program. These printouts may give a clue about the problem. You can use Scart-1 for Teraterm
program connection.

İ. NO SIGNAL PROBLEM
Problem: No signal or Low signal in DVB-S/S2 mode.
Check signal cables and LNB voltage, if there is no problem, check M88TS2022 (U116) supply voltages;
3V3_VCC_SAT.
If the above measurements are OK, then measure the voltage from the PIN20 of U116.
If the PIN1 voltage is equal to 0V, please check i2c waveforms and software. If the PIN1 voltage is lower
than 1V(e.g: 0.8Vor 0.3V), change the U116 with a new part.

46
47
 14. SERVICE MENU SETTINGS
In order to reach service menu, first Press “MENU” buton, then write “4725” by using remote controller.
You can see the service menu main screen below. You can check SW releases by using this menu. In addition,
you can make changes on video, audio etc. by using video settings, audio settings titles.

Service Menu

Video Settings
48
 Audio Settings

Options 1

49
 Options 2

Options 3

50
 Tuning Settings

Source Settings
51
 Diagnostic

52
 1 2 3 4 5 6 7 8

X102

3V3_TUNER 1 4
2 3

TUNER

C439

C435

C519

C445
100n
1n2

1n2

1n2
24MHz C376
100n AC2
A IF_P

1
IP_T A

C442

100n
IF_N AC3 IM_T
100n

1
F145 C377
3V3_TUNER 10k AD1 SIFP

560nH
1k R405 AD2 SIFM

C447

L107
50V
1n2

12n

18

17

16

15

14

13
S204
TUNER_IF_AGC AC1 IFAGC_T 4
1 2
2

NC

VDDH_2

GND_3

VDDH_1

XTAL_O

XTAL_I
100n
8 6 4 2 19 RF_REF XOUT 12 C443
1

R419 R338
U114
C449 C450 R403 3V3_VCC_SAT 4k7 MSD91QV01
1
S193 20 11 AD3
JK103 RF_IP LIF_P 100R IF_P R413 3V3_TUNER 4k7
2 1
S2_RESET TGPIO0
3V3_TUNER 2 1
FEF_AGC_FREEZE AE2 TGPIO1
47p 39p 4k7 1
S192 2
21 GND_0 LIF_N 10 100R TUNER_SCL AF3 TGPIO2
50V IF_N
9 7 5 3 C451 U118 AE4
270nH
R404 TUNER_SDA 100n TGPIO3
L109

22 9 C357
22n

RF_IN SI2151 VDDH_0 3V3_TUNER 3V3_TUNER 4k7 S157 100n

C432
2 1

50V
C362 AH2

180nH

1n2
L110 39p 100n S2_IP R417 IP_S

560nH
1 2
23 8 S159 AH3
12n
ADDR GND_2 C518 S2_IN IM_S

L108
1 2
S158 C359 AF4

12n
S2_QP QP_S

GPIO2

GND_1
1 2
24 7 S160 100n 100n AG3

AGC2

AGC1
GPIO1 VDDL S2_QN QM_S

SDA

SCL
1 2

C363
B 16V B

C433

C434
6V3

50V
AG4

1n2
S2_AGC

3V3_TUNER
100n IFAGC_S

1u
C455

1 2
180p
50V

C517 S205

6
DISEQC_OUT AG5 GPIO15/DISEQC_OUT
C448 AF5 GPIO18/DISEQC_IN

27p

FEF_AGC_FREEZE
C446 R408
100R TUNER_IF_AGC
27p
16V

R416
100R

100R
R412
100n
C440

TUNER_SDA

TUNER_SCL
C C
F149
3V3_VCC 3V3_TUNER

100n 10V

100n 10V
60R

C477

C478

C475

C476
6V3

6V3
10u

10u
SAT TUNER
3V3_VCC_SAT

3V3_VCC_SAT C378 C379

27p 27p
X101
1 4
2 3
27MHz LNBp

DISEQC_OUT
14

13

12

11

10

SYS_SDA

SYS_SCL
VDDA4

TEST1

TEST2

TEST3

VDDA3

XTALN

XTALP

D D
R349
3k3 15 RES VDDA2 7 3V3_VCC_SAT
C130

100R
R149
100R
R148
1N5819
3V3_VCC_SAT 10k CAP CK_OUT 100n

C22V

D110

D111
16 6
R340 C406 100nF 50V 10V
Q127 10n CKDIV_OPT U116 IP S2_IP 220n
BC848B

17 5
S2_RESET 10k D109 C137
RFBYPASS M88TS2022

12

11

10
R339 IN S2_IN LNB_OUT

9
18 4
5 4 3 2 C134 1N5819

EXTM

VCTRL

SDA

SCL/VADJ
RESET VDDA1 3V3_VCC_SAT NC 10u
19 3 13 8

1N5819
C412 L106 25V VLNB FAULT

D107
CN107 1 LNA_IN QN S2_QN C129
20 2 C123 C114 C115 C124
50V 4n7 10u 10u 10u 10u 14 VCP EN/ADDR 7
3p3 270k
50V 0p5 21 TEST QP 1 S2_QP 25V 25V 25V 25V 100n 10V U102 R143
6 7 8 9 15 6
C409 BOOST TPS65233 ISEL 100k
VDD_DIG

VDD_REG

C128
VDAA5

VDDA6

16 5

1N5819

AGND
D122 PGND TCAP
SDA

SCL

AGC

D104

VIN

VCC
LX
E BAV99 100n 10V E
C112 22nF
22

23

24

25

26

27

28

10u

4
LNB_OUT 25V L102
1n 1n 1n 1n 1n 3V3_VCC_SAT 12V_VCC
C135

C415

C418

C416

C417

S2_AGC_D1 10u
C122
50V 50V 50V 50V 50V REG_OUT_AGC_D1 1u
3V3_VCC_SAT

C381 F105 16V

R341 10n 12V_VCC
100R TUNER_SCL S2_AGC C111 1k C121 C117
R345 S206 R317 10u 10u 100n
100R TUNER_SDA REG_OUT_AGC_D1 10k 1 2
100R S2_AGC_D1 16V 16V 16V
C399 C386 R316
C351

C361
16V

10V
100n
22n

27p 27p

Close SAT DEMOD Close SAT DEMOD

Close To TS2022

F F
F124
3V3_VCC 3V3_VCC_SAT
60R C385 C402 C365 C380 C398 C364 C515
C324

C516
6V3

6V3
10u

10u

100n 100n 100n 100n 100n 100n 100n

VESTEL PROJECT NAME : 17mb130p-r1 A3
SCH NAME :TUNER_SAT_LNB T. SHT:10
DRAWN BY :<YOUR NAME HERE> 20-06-2016_14:13
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8

SCART INDIA OPTION SAV INPUT

8
CDA4C16GTH

2
SC_CVBS_IN

D128

R306

C5V6

D118
4

75R
D129
YEL

C336
S152

2
50V
220p
A C474 A

R445
75R
YEL

1
33p IND_L_IN TP157 S153
50V 3 JK105 1

C15V
21 WHT SAV_CVBS_IN

2
1 TP212 SAV_L S183 2
20 SC_CVBS_IN IND_R_IN 2
TP194 R395 F139 TP161 WHT JK100
1 RED S182
1

SC_CVBS_OUT 3
SAV_L_IN 10k S177
19 1k
1 TP178
4
18 SAV_OPT2

1
F138TP160 RED

C473

R443
S181 5

75R
33p
SAV_R_IN 10k
17 1k
1 TP188 C422 R378

3n3

3n3
2
47R SC_FB 560p SAV_R SAV_OPT1

R394

R400

C427

C420
2 1
16

12k

12k
1 TP179 R444 C430
SC_R 560p
15
2

R432
75R

D142 D141
C463
14
33p
1

13 C5V6 C5V6
SCART LT1

B TP223 B
SC100

C472 2
75R 1 DEBUG_TX
12 1 2
R442 R441
TP180
11
1

1 TP189
75R 33p 50V
D126 C15V SC_G SLIM SAV INPUT
2 75R 1 DEBUG_RX
10 R431
D143
5k1
2 1 1
9 100n C454 SAV_OPT2
1 TP195 C5V6 R429 S180
10k 2
8 SC_PIN8 SAV_CVBS_IN
1 TP185 R440 F137
6
7 SC_B

33p 50V
TP190 1k

C462
1

1
10k 3
SC_AUD_L_IN SAV_L
R430
6
75R
C471 R428 F144
330p 4
C461
R427

5
12k

50V 1k
2

560p
5 JK101
4 IND_L_IN SAV_OPT1
F148 R424
SC_AUD_L_OUT 7
C 3 600R
1
100R
2
SAV_R C
1 TP181 R426
10k SC_AUD_R_IN
2
1 TP196 F147 R439
1
100R
2
SC_AUD_R_OUT
1 600R
TP183
C469

C459

1
4n7

4n7

C470 C460
R425
12k

330p 560p
50V
R336
C374 47n V1
IND_R_IN VGA_R 33R RIN0P
R333 68R C372 47n V3 GIN0M
C373 47n U1
VGA_G 33R GIN0P
R335 R332
C371 47n U2
VGA_B 33R BIN0P

VGA_HS P6 HSYNC0
VGA_VS R5 VSYNC0
5V_VCC
D D
5

U6 RIN1P
BAV70
D123

V6
CDA4C16GTH

GIN1M
VGA
D125

V4 GIN1P
2

C425
R398

R388

2
10k

10k

VGA_DDC_5V V5 BIN1P
1
100n
10V U114
4

15 VGA_SCL R346
MSD91QV01
C393 47n Y6
R397 SC_R 33R RIN2P
14
R389
560R VGA_VS SPDIF OUT SC_G
R330
33R
68R
C369 47n
C370 47n
Y5
W6
GIN2M
GIN2P
13 560R VGA_HS R331 R347
C394 47n W5
SC_B 33R BIN2P
12 VGA_SDA VIN 1 SPDIF_COAX
T6
FB100

F140 SC_PIN8 HSYNC1

1

11 VCC 2 5V_VCC SC_FB R6 VSYNC1

1k
TP172
TP176
TP175
TP166

C424
1

2
10V
100n
10 GND 3 47n
R390

R399

R401
2k2

2k2

4k7
E

1
R337 C383
V2 E
SPDIF_COAX

9 VGA_DDC_5V 68R VCOM

2

2
R344 C397
8 1 TP165 SAV_CVBS_IN 33R 47n T5 CVBS0
C428 R379 SC_CVBS_IN 33R U4 CVBS1
TP173

7 Q134 100R SPDIF_OUT R348 C396

BC848B 100n 10V 47n
C444

1
100n
10V

6 C423
R402
4k7

22p
1

5 2 220R 50V
3 SC_CVBS_OUT U5
2

JK102 R411 CVBSOUT1

4 1
C438
R415
220R

1
F143 1k TP170 22p

C395

R334
1

75R
33p
3 VGA_B 50V
F141 1k

2
2 VGA_G
F142 1k
1 VGA_R

F CN112 F
TP163
TP164
TP168

2 NUP4004M5

1
1
3

4
5

R391

R393

R392
75R

75R

75R
D124

VESTEL PROJECT NAME : 17mb130p-r1 A3

2

SCH NAME :PERIPHERALs T. SHT:10

DRAWN BY :<YOUR NAME HERE> 20-06-2016_14:11
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8
HDMI3 ***HOTEL TV OPTIONS*** ETHERNET
CN111 CN108
21 HDMI0_RX0N N3 RXA0N R383
N2 ETH_PIN1 S187 S172 ETH_PIN1 1
20 HDMI0_RX0P RXA0P 2
10k 1
3V3_STBY ETH_TP TD+
1 HDMI0_RX2P HDMI0_RX1N P3 RXA1N
P2 S186 S173 ETH_PIN2 2
2 HDMI0_RX1P RXA1P DEBUG_RX ETH_TN TD-
3 HDMI0_RX2N HDMI0_RX2N P1 RXA2N TP159 1

R3 S208 3
A 4 HDMI0_RX1P HDMI0_RX2P
M1
RXA2P TOUCHPAD_SDA 5V_STBY TCT A
5 HDMI0_CLKN RXACKN F132 S161
6 HDMI0_RX1N HDMI0_CLKP M2 RXACKP R381 1k C388 ETH_RP 4 RD+
R2 ETH_PIN2 S185
7 HDMI0_RX0P HDMI0_SCL DDCDA_CK 2
10k 1
3V3_STBY 1u
T3 S162 5
8 HDMI0_SDA DDCDA_DA S184 ETH_RN RD-
9 HDMI0_RX0N R352 HOTPLUG0 T2 HOTPLUGA DEBUG_TX TP158 1

10 HDMI0_CLKP CEC 100R P5 CEC 5V_STBY 6 RCT

R370 U3 S207
11 HDMI0_5V 33R HOTPLUGA_HDMI20_5V TOUCHPAD_SCL F134 S175
12 HDMI0_CLKN 1k C390 IR_FROM_ETH 7 NC1
13 CEC HDMI1_RX0N J2 RXB0N 1u
14 HDMI1_RX0P K3 RXB0P 8 NC2
15 HDMI1_RX1N K2 RXB1N 1 Q133
HDMI0_SCL
16 HDMI1_RX1P L3 RXB1P IR_FROM_ETH 9 SHLD1
HDMI0_SDA IR_RC
L2
17 HDMI1_RX2N
L1
RXB2N U114 10
18 HDMI0_5V HDMI1_RX2P RXB2P BC848B R385 SHLD2
J3
19 1
1k
2
HDMI0_5V HDMI1_CLKN
J1
RXBCKN MSD91QV01 B3
1
10k
2
5V_STBY
R373 HDMI1_CLKP RXBCKP TN ETH_TN
2

HDMI1_SCL N5 DDCDB_CK TP A3 ETH_TP

R360

R361

R372
47k

47k

10k
HDMI1_SDA N6 DDCDB_DA RN B4 ETH_RN
R4 C4
B 3
HOTPLUG1
R367 P4
HOTPLUGB RP ETH_RP C36710u R326
3V3_STBY
B
1

R377 HDMI1_5V 33R HOTPLUGB_HDMI20_5V 1k

1N4148
2
10k HOTPLUG0 C366 C368

R319

D121
10k
B1 RXC0N GPIO19/LED[0] R27 100n 100n
1
BC848B C1 RXC0P GPIO20/LED[1] R26 10V 10V
Q132 C2 RXC1N
D3 RXC1P HWRESET L27
D2 RXC2N
E3 AG1 S155
RXC2P XIN
A2 AF1
RXCCKN XOUT 24MHz
B2 S156

CN110
HDMI2 M5
L6
J4
RXCCKP
DDCDC_CK
DDCDC_DA
IRIN AE5 100R
R384
IR_RC
4
3
1
2
21 HOTPLUGC X100

C356

C355
H4

27p

27p
20 HOTPLUGC_HDMI20_5V
1 HDMI1_RX2P USB0_DM B7 USB_BT_DN
2 HDMI2_RX0N F1 RXD0N USB0_DP C7 USB_BT_DP
3 HDMI1_RX2N HDMI2_RX0P F2 RXD0P USB1_DM B6 USB_WIFI_DN
4 HDMI1_RX1P HDMI2_RX1N G3 RXD1N USB1_DP A6 USB_WIFI_DP
G2 AF7
C 5 HDMI2_RX1P
H3
RXD1P USB2_DM
AG7
USB2_DN C
6
7
8
HDMI1_RX1N
HDMI1_RX0P
HDMI2_RX2N
HDMI2_RX2P
HDMI2_CLKN
H2
E1
F3
RXD2N
RXD2P
RXDCKN
USB2_DP
USB3_DM
USB3_DP
AG8
AH8
USB2_DP
USB1_DN
USB1_DP
USB1 2.0
9 HDMI1_RX0N HDMI2_CLKP RXDCKP
10 HDMI1_CLKP HDMI2_SCL K5 DDCDD_CK TP221 1

11 HDMI2_SDA L5 DDCDD_DA 60R 4

12 HDMI1_CLKN HOTPLUG2 M6 HOTPLUGD NC1_USB AH9 C308 F122 TP136 1

13 CEC HDMI2_5V 33R L4 HOTPLUGD_HDMI20_5V NC2_USB AG9 USB1_DP 3

R364
14 100n TP138 1

15 5V_VCC 1 IN OUT 6 2
HDMI1_SCL USB1_5V_VCC USB1_DN
16 HDMI1_SDA U109 TP140 1

17 2 GND ILIM 5 560R USB1_5V_VCC 1

18 HDMI1_5V TPS2553-1 R292 C309

C306
100n
19 1 2
HDMI1_5V 33R 3 EN FAULT 4 560R 10u CN105
1k USB_ENABLE
R369 R296 R295 10V
2

2
R359

R358

R368
47k

47k

10k

D
1

Q131 2
R376 D
10k HOTPLUG1
BC848B
1

USB2 2.0
HDMI1 C414 16V
60R
F135 TP146 1

4
CN109 100n TP147 1

21 5V_VCC 1 IN OUT 6 USB2_DP 3

USB2_5V_VCC
20 U117 TP148 1

1 HDMI2_RX2P 2 GND ILIM 5 560R 2

USB2_DN
2 TPS2553-1 R351 TP155 1

3 EN FAULT 4
3
4
HDMI2_RX2N
HDMI2_RX1P WOWL OPTION USB_ENABLE 33R
R362
560R
R350
USB2_5V_VCC
C403
1

C410
100n
5 10u CN106
6 HDMI2_RX1N 10V
E 7 HDMI2_RX0P R477 R1 R482 E
8 37k4 100R
9
10
11
HDMI2_RX0N
HDMI2_CLKP
33k 4k7
WIFI&BT
12 HDMI2_CLKN

C504
C494

10u
16V
13 CEC

TP217
14 HDMI_ARC
15 HDMI2_SCL 100n
16 HDMI2_SDA C500 C499 CN116
17 6 BOOT GND 1 22u 100n C495 F155 TP203

1
1

18 HDMI2_5V WOWL_EN U121 L111 6V3 USB_BT_DP 1 2 3V3_WOWL

19 1 2
HDMI2_5V 1
10k 2 5 EN LX 2 3V3_WOWL 100n 60R TP202
1k 1
S198
R366 R476 RT6213BHGJ6F 3u3 1N5819 3V3_VCC 1 IN OUT 6 3V3_WOWL C5V6 D136 USB_BT_DN 3 4 3D_SYNC_I
2

4 FB VIN 3 12V_VCC U122 R486

R356

R357

R365

S199 S197
47k

47k

10k

C496 D132 2 GND ILIM 5 560R WOWL_DET 5 6

C498 S200 3D_SYNC
R2

100n 1N5819 TPS2553-1 R480 TP201 C5V6

R481

1
3
12k

WIFI/BT_ENABLE 3 EN FAULT 4 USB_WIFI_DN

1

R374 22u 5V_STBY 560R 7 8 2 1

Q130 2
10k HOTPLUG2 D134NC TP200 D139

1
1

BC848B
F USB_WIFI_DP 9 10 F

TP216
1
TP199 1

VESTEL PROJECT NAME : 17mb130p-r1 A3

SCH NAME :HDMI_USB_ETH T. SHT:10
DRAWN BY :<YOUR NAME HERE> 20-06-2016_14:56
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8
1V5_DRAM 60R
W/STR

DDR_VTT
F120
F161
1V5_DDR_STR
W/STR 60R R293 100R
1V5_DRAM F117 1 R1 8 100n
AB_MA14 C300
1V5_VCC 1V5_DRAM 2 R2 7
AB_MA8
E14 AB_MA0 60R 3 R3 6 100n

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
A-A0 C238 C230 C264 C263 AB_MA11

R508
C218

4k7
A-A1 B11 AB_MA1 4 R4 5
AB_MA6
E12 AB_MA2 AB_MA0 N3 22u 22u 10u 10u 100n

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
A A-A2 A0 A

C316

C315

R302
6V3 C216

100n
16V

50V
F14 AB_MA3 AB_MA1 P7 6V3 10V 10V

1k
A-A3 A1 R290 100R

1n
A-A4 A12 AB_MA4 AB_RSTn AB_MA2 P3 A2 1 R1 8 100n
AB_MA1 C220
A-A5 D13 AB_MA5 C862 AB_MA3 N2 A3 2 R2 7
AB_MA4
A-A6 A11 AB_MA6 100n AB_MA4 P8 A4 VREF_DQ H1 3 R3 6 100n
AB_MA12 C288
A-A7 F13 AB_MA7 16V AB_MA5 P2 A5 VREF_CA M8 1k 1V5_DRAM 1V5_DRAM 4 R4 5
AB_MBA1
A-A8 C9 AB_MA8 AB_MA6 R8 A6 R303 C256 C266 C265 C262 C253 C314 100n
F12 AB_MA9 AB_MA7 R2 E3 A_DQL0 C307
A-A9 A7 DQL0 100n 100n 100n 100n 100n 100n
A-A10 B13 AB_MA10 AB_MA8 T8 A8 DQL1 F7 A_DQL1 16V 16V 16V 16V 16V 16V R277 100R 100n
AB_MA9 C217
A-A11 B10 AB_MA11 AB_MCKE AB_MA9 R3 A9 DQL2 F2 A_DQL2 R276 100R
AB_MA13
A-A12 D17 AB_MA12 AB_MA10 L7 A10/AP DQL3 F8 A_DQL3
A-A13 C10 AB_MA13 AB_MA11 R7 A11 DQL4 H3 A_DQL4 R285 100R
WO/STR AB_RSTn

R507
A9 AB_MA14 AB_MA12 N7 H8 A_DQL5

1k
A-A14 A12/BC DQL5
A-A15 F16 AB_MA15 AB_MA13 T3 A13 DQL6 G2 A_DQL6 100n
D15 AB_MBA0 H7 A_DQL7
AB_MA15 4 R4 5 C213
A-BA0 DQL7 1V5_DRAM AB_MBA0 3 R3 6
A-BA1 B12 AB_MBA1 J1 NC1 C267 C313 C257 AB_MBA2 100n
E16 AB_MBA2 L1 D7 A_DQU0 2 R2 7 C289
A-BA2 NC2 DQU0 16V 100n 100n 100n AB_MA3 1 R1 8
A-RASZ F19 AB_MRASn AB_MA15 M7 NC3 DQU1 C3 A_DQU1 100n 16V 16V 16V R279 100R 100n
F18 AB_MCASn L9 C8 A_DQU2 C210
A-CASZ
F17 AB_MWEn AB_MA14 T7
NC4 U113 DQU2
C2 A_DQU3
C258 R278 100R
100n
B A-WEZ
F11 AB_MODTR310 J9
NC5 DQU3
A7 A_DQU4
AB_MA0 4 R4 5 C211 B
A-ODT
C14
NC6 H5TQ2G63BFR-PB DQU4 AB_MA5 3 R3 6
A-CKE 22R AB_MCKE DQU5 A2 A_DQU5
AB_MA2 2 R2 7
100n
C215
A-RST F15 AB_RSTn AB_MBA0 M2 BA0 DQU6 B8 A_DQU6
C15 AB_TMCLK AB_MBA1 N8 A3 A_DQU7
AB_MA7 1 R1 8 100n
A-MCLK BA1 DQU7 1V5_DRAM C279
A-MCLKZ A14 AB_TMCLKn AB_MBA2 M3 BA2 16V C338 C261 C260 C251 C252 R281 100R
AB_MCKE
A-CSB1 B8 AB_TMCSAn DQSL_0 F3 A_DQSL 100n 100n 100n 100n 100n 100n
WO/STR 100n
D11 AB_TMCSBn AB_MCLK J7 G3 A_DQSLn C299
A-CSB2 CK_0 DQSL_1 C250 16V 16V 16V 16V 16V AB_MRASn 4 R4 5
AB_MCLKn K7 CK_1 R3 6 100n
AB_MCASn 3 C219
DQSU_1 B7 A_DQSUn R2 7
AB_MODT 2
A-DQ[0] E22 A_DQL0 AB_MCKE K9 CKE DQSU_0 C7 A_DQSU R1 8
AB_MWEn
A-DQ[1] D19 A_DQL1 Close to DDR Power Pin 1
R280
A21 A_DQL2 AB_TMCSAn S146 L2 E7 A_DML
A-DQ[2] CS DML 100R
A-DQ[3] C17 A_DQL3 DMU D3 A_DMU R282 100R
A-DQ[4] D23 A_DQL4 AB_MRASn J3 RAS 1V5_DRAM 1 R1 8 100n
B_MCLKn C280
A-DQ[5] B15 A_DQL5 AB_MCASn K3 CAS ODT K1 AB_MODT C259 C337 2 R2 7
B_MCLK
A-DQ[6] B21 A_DQL6 AB_MWEn L3 WE 100n 100n 3 R3 6 100n
C16 A_DQL7 4 R4 5 C214

VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
A-DQ[7] 16V 16V

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
A-DQM[0] E18 A_DML AB_RSTn T2 RESET 100n
B19 A_DQSL L8 C212
C A-DQS[0] ZQ R288 C
AB_MA10 100R
Close to DDR Power Pin
R309
240R

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
A-DQSB[0] C19 A_DQSLn
A-DQ[8]/DQU0 F21 A_DQU0
A-DQ[9]/DQU1 B20 A_DQU1
A-DQ[10]/DQU2 B17 A_DQU2
A-DQ[11]/DQU3 F23 A_DQU3
A-DQ[12]/DQU4
A-DQ[13]/DQU5
F20
D21
E20
A_DQU4
A_DQU5
A_DQU6
AB_TMCLK

AB_TMCLKn
S149

S154
AB_MCLK

AB_MCLKn
1V5_DRAM
W/STR
A-DQ[14]/DQU6
A-DQ[15]/DQU7 A20 A_DQU7 R513 R511
R1
A-DQM[1] F22 A_DMU R301 51k 47k
A-DQS[1] A18 A_DQSU AB_MCLK 22R B_MCLK
8 A-DQSB[1] C18 A_DQSUn R300 C866
AB_MCLKn 22R B_MCLKn
U114
B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
2p NC
MSD91QV01 16V C850 50V
B28 B_DQL0 AB_MA0 N3
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
A-DQ[16]/DQL0 A0

C254

C255

R284
100n
16V

50V
F25 B_DQL1 AB_MA1 P7

1k
D A-DQ[17]/DQL1 A1 D

1n
C28 B_DQL2 AB_MA2 P3 100n
A-DQ[18]/DQL2 A2 C864 C865
A-DQ[19]/DQL3 A23 B_DQL3 AB_MA3 N2 A3 6 BOOT GND 1 22u 22u TP220
N.C.
A-DQ[20]/DQL4 F28 B_DQL4 AB_MA4 P8 A4 VREF_DQ H1 R510 U125 L116 6V3 6V3
A-DQ[21]/DQL5 B22 B_DQL5 AB_MA5 P2 A5 VREF_CA M8 1k 1V5_DRAM STR_EN 1
10k 2 5 EN LX 2 1V5_DDR_STR
A-DQ[22]/DQL6 E28 B_DQL6 AB_MA6 R8 A6 R286 RT6213BHGJ6F 3u3
A-DQ[23]/DQL7 C23 B_DQL7 AB_MA7 R2 A7 DQL0 E3 B_DQL0 4 FB VIN 3 12V_STBY
A-DQM[2] F24 B_DML AB_MA8 T8 A8 DQL1 F7 B_DQL1
C863 C868 C867
A-DQS[2] B26 B_DQSL AB_MA9 R3 A9 DQL2 F2 B_DQL2 R526 100n 10u 10u

100k
R512
A-DQSB[2] C26 B_DQSLn AB_MA10 L7 A10/AP DQL3 F8 B_DQL3 1
10k 2
16V 16V
R2
AB_MA11 R7 A11 DQL4 H3 B_DQL4

2
AB_MA12 N7 H8 B_DQL5

R527
A12/BC DQL5

10k
A-DQ[24]/DQU0 D25 B_DQU0 AB_MA13 T3 A13 DQL6 G2 B_DQL6
A-DQ[25]/DQU1 A27 B_DQU1 DQL7 H7 B_DQL7
E24 B_DQU2 J1

1
A-DQ[26]/DQU2 NC1
A-DQ[27]/DQU3 F27 B_DQU3 L1 NC2 DQU0 D7 B_DQU0
A-DQ[28]/DQU4 F26 B_DQU4 AB_MA15 M7 NC3 DQU1 C3 B_DQU1
C27 B_DQU5 L9 C8 B_DQU2
A-DQ[29]/DQU5
C24 B_DQU6 AB_MA14 T7
NC4 U110 DQU2
C2 B_DQU3
A-DQ[30]/DQU6 NC5 DQU3
D27 B_DQU7 J9 A7 B_DQU4
E A-DQ[31]/DQU7 NC6 H5TQ2G63BFR-PB DQU4 E
A-DQM[3]
A-DQS[3]
E26
C25
B24
B_DMU
B_DQSU
B_DQSUn
AB_MBA0
AB_MBA1
M2
N8
BA0
DQU5
DQU6
A2
B8
A3
B_DQU5
B_DQU6
B_DQU7
RAM VTT LDO
A-DQSB[3] BA1 DQU7
AB_MBA2 M3 BA2
W/STR DQSL_0 F3 B_DQSL
B-RST H26 2k AVDD_DDR_STR B_MCLK J7 CK_0 DQSL_1 G3 B_DQSLn
10V 10V 16V 16V
R515 B_MCLKn K7 CK_1 10u 10u 100n 100n
B-CKE G26 2k DQSU_1 B7 B_DQSUn C206 C202 C223 C237
R514 AB_MCKE K9 CKE DQSU_0 C7 B_DQSU 1V5_VCC 1 VDDQSNS VIN 10 3V3_VCC
DRAM_VREF L26 1k 1V5_DRAM
AB_TMCSBn S145 L2 E7 B_DML 2 VLDOIN
R287 CS DML S5 9
K27 D3 B_DMU
ZQ DMU U108
C290

C301

R289
100n

AB_MRASn J3 3 VTT GND 8

1k

RAS TP135
1n

M25 AB_MCASn K3 K1 AB_MODT

ZQ1 CAS ODT RT9026GFP
AB_MWEn L3 WE DDR_VTT 4 PGND S3 7 3V3_VCC
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

C228 C222 C221

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

AB_RSTn T2 RESET 100n 10u 10u 5 VTTSNS VTTREF 6

L8 ZQ 16V 10V 10V 16V
F 100n F
R291
240R
240R
R294

R299
240R

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C229

VESTEL PROJECT NAME : 17mb130p-r1 A3

SCH NAME :DDR T. SHT:10
DRAWN BY :<YOUR NAME HERE> 20-06-2016_11:04
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8

NAND FLASH
PCM_D0
PCM_D1
PCM_D2
PCM_D3
AC25
AG23
AB25
AD25
PCMDATA[0]/CI_DATA[0]
PCMDATA[1]/CI_DATA[1]
PCMDATA[2]/CI_DATA[2]
PCMDATA[3]/CI_DATA[3]
CI 1 NC1 NC29 48

PCM_D4 AC24 PCMDATA[4]/CI_DATA[4] TS2DATA[0] M24 CN103 2 NC2 NC28 47

PCM_D5 AC23 N24
A PCM_D6 AD24
PCMDATA[5]/CI_DATA[5] TS2CLK
N25 PCM_CD1
R244 35 1
CI_D3 3 46 A
PCMDATA[6]/CI_DATA[6] TS2VALID 3V3_VCC 10k 22R 36 2 NC3 NC27
PCM_D7 AD23 PCMDATA[7]/CI_DATA[7] TS2SYNC P25 R238 TS0_D3 37 3 CI_D4
TS0_D4 38 4 CI_D5 4 NC4 NC26 45
PCM_A0 AE24 PCMADR[0]/CI_A[0] TS0_D5 39 5 CI_D6
PCM_A1 AE23 PCMADR[1]/CI_A[1] 22R TS0_D6 40 6 CI_D7 5 NC5 I/O7 44 NAND_AD7
PCM_A2 AC22 PCMADR[2]/CI_A[2] R150 R225 TS0_D7 41 7 CI_CE R156
PCM_A3 AD22 PCMADR[3]/CI_A[3] 1 R1 8 TS0_D0 3V3_VCC 10k 42 8 CI_A10 3V3_NAND 4k7 6 NC6 I/O6 43 NAND_AD6
PCM_A4 AC21 PCMADR[4]/CI_A[4] TS0DATA_[0] AH20 2 R2 7 TS0_D1 10k 43 9 CI_OE
PCM_A5 AG22 PCMADR[5]/CI_A[5] TS0DATA_[1] AG20 3 R3 6 TS0_D2 R224 CI_IORD 44 10 CI_A11 NAND_RBZ 7 RB I/O5 42 NAND_AD5
PCM_A6 AD21 PCMADR[6]/CI_A[6] TS0DATA_[2] AF17 4 R4 5 R235 R207 CI_IOWR 45 11 CI_A9
PCM_A7 AC20 PCMADR[7]/CI_A[7] TS0DATA_[3] AH18 22R TS0_D3 TS1_SYNC 22R 46 12 CI_A8 NAND_REZ 8 R I/O4 41 NAND_AD4
PCM_A8 AC19 PCMADR[8]/CI_A[8]/SDIO_D0 TS0DATA_[4] AG17 1 R1 8 TS0_D4 TS1_D0 47 13 CI_A13
PCM_A9 AF21 PCMADR[9]/CI_A[9]/SDIO_D1 TS0DATA_[5] AF20 2 R2 7 TS0_D5 TS1_D1 48 14 CI_A14 NAND_CEZ 9 E NC25 40
PCM_A10 AD20 PCMADR[10]/CI_A[10]/SDIO_D2 TS0DATA_[6] AG18 3 R3 6 TS0_D6 TS1_D2 49 15 CI_WE R211
PCM_A11 AD19 AF18 4 R4 5 TS0_D7 TS1_D3 CI_IRQA 4k7 S104 10 39
PCMADR[11]/CI_A[11]/SDIO_D3 TS0DATA_[7] 50 16 CI_PWR NAND_CEZ1 NC7 NC24
PCM_A12 AD18 PCMADR[12]/CI_A[12] TS0CLK AF19 TS0_CLK R231 CI_PWR 51 17 CI_PWR
PCM_A13 AE18 PCMADR[13]/CI_A[13] TS0VALID AH17 TS0_VALID 22R 52 18 R196 11 NC8 NC23 38
PCM_A14 AE20 PCMADR[14]/CI_A[14] TS0SYNC AG19 TS0_SYNC 22R TS1_D4 53 19 22R TS1_VALID
U105

C139

C138
50V

50V
TS1_D5 TS1_CLK 12 37

10p

10p
B AB24 U23
R203
1 R1 8 TS1_D0 TS1_D6
54 20
CI_A12
22R 3V3_NAND VDD1 VDD2 3V3_NAND B
PCM2_CE_N/SDIO_CLK TS1DATA_[0] 55 21 R198 NAND128-A

C149

C150
50V

50V
AB23 T25 2 R2 7 TS1_D1 TS0_CLK TS1_D7 CI_A7 13 36

10p

10p
PCM2_IRQA_N/SDIO_CMD TS1DATA_[1] 22R 56 22 VSS1 VSS2
TS1DATA_[2] N23 3 R3 6 TS1_D2 R187 57 23 CI_A6
PCM_IRQA AE17 PCMIRQA/CI_INT TS1DATA_[3] P23 4 R4 5 TS1_D3 R153 CI_RST 58 24 CI_A5 14 NC9 NC22 35 NAND_DQS
PCM_OE AE21 PCMOEN TS1DATA_[4] U24 1 R1 8 TS1_D4 CI_PWR 10k CI_WAIT 59 25 CI_A4
PCM_IORD AG21 PCMIORD/CI_RD TS1DATA_[5] T23 2 R2 7 TS1_D5 60 26 CI_A3 15 NC10 NC21 34 1
10k 2

PCM_CE AC18 PCMCEN/CI_CS TS1DATA_[6] R25 3 R3 6 TS1_D6 R151 CI_REG 61 27 CI_A2 R228
PCM_WE AD17 PCMWEN TS1DATA_[7] R24 4 R4 5 TS1_D7 TS0_VALID 22R 62 28 CI_A1 NAND_CLE 16 CL NC20 33
PCM_CD AH21 PCMCD/CI_CD TS1CLK R23 TS1_CLK R195 TS0_SYNC 22R 63 29 CI_A0
PCM_RST AC16 PCMRST/CI_RST TS1VALID P24 TS1_VALID 22R R155 TS0_D0 64 30 CI_D0 NAND_ALE 17 AL I/O3 32 NAND_AD3
PCM_REG AF22 PCMREG/CI_CLK TS1SYNC T24 TS1_SYNC TS0_D1 65 31 CI_D1
PCM_IOWR AC17 PCMIOWR/CI_WR TS0_D2 66 32 CI_D2 NAND_WEZ 18 W I/O2 31 NAND_AD2
PCM_WAIT AD16 PCMWAIT/CIWACK 5 3V3_VCC 10k PCM_CD2 22R 67 33 10k CI_PWR
R134 R141 68 34 R154 NAND_WPZ 19 WP I/O1 30 NAND_AD1
U114 20 29
NC11 I/O0 NAND_AD0
MSD91QV01 21 28
NC12 NC19
C NAND_ALE AC13 22 27 C
NAND_ALE/EMMC_IO15 NC13 NC18
AD12
S105 NAND_WPZ NAND_WPZ/EMMC_IO17

TP109
NAND_CEZ AG11 23 26

BSH103
NAND_CEZ/EMMC_IO9/EMMC_CMD NC14 NC17
AC12
S106 NAND_CLE

Q118
NAND_CLE/EMMC_IO14
NAND_REZ AF11 NAND_REZ/EMMC_IO10/EMMC_CLK 24 NC15 NC16 25
AD13
S107 NAND_WEZ NAND_WEZ/EMMCIO16 R236

1
NAND_RBZ AG10 NAND_RBZ/EMMC_IO11/EMMC_RSTN 1 2
5V_VCC F113
3V3_VCC 10k CI_PWR

C170
100n
2

3
AE12

10V
R227 NAND_CEZ1 NAND_CEZ1/EMMC_IO12 C161 C162 C160 3V3_VCC 3V3_NAND
NAND_DQS 75R AD14 NAND_DQS/EMMC_IO8 1N4148 10u
2 2
60R C179
100n 100n C172 C171

1
R226 PCM_CD 1 1
10V

1
PCM_CD1 10V 10V 10u 100n 100n
22R
D113 R219 R220 10V 16V 16V
NAND_AD0 75R R4 AG15 NAND_AD0/EMMC_IO6/EMMC_D[6] 1N4148 12V_VCC 1
47k
2 1
47k
2

4 5 AH15
NAND_AD1 R3 NAND_AD1/EMMC_IO7/EMMC_D[7] PCM_CD2
3 6 AH14
NAND_AD2 R2 NAND_AD2/EMMC_IO2/EMMC_D[2] D105 R232
2 7 AG14 Q119
NAND_AD3 R1 NAND_AD3/EMMC_IO1/EMMC_D[1] CI_PWR_CTL 1
10k 2

1 8 AG13 BC847B
NAND_AD4 R4 NAND_AD4/EMMC_IO0/EMMC_D[0]
4 5 AF13
NAND_AD5 R3 NAND_AD5/EMMC_IO3/EMMC_D[3]
3 6 AH12
NAND_AD6 R2 NAND_AD6/EMMC_IO4/EMMC_D[4]
2 7 AF12
D NAND_AD7 R1 NAND_AD7/EMMC_IO5/EMMC_D[5] D
1 8
75R R229
22R

R237
PCM_D3 22R CI_D3

R162 R142
22R 22R
PCM_A0 8 R1 1 CI_A0 PCM_D0 8 R1 1 CI_D0
PCM_A1 7 R2 2 CI_A1 PCM_D1 7 R2 2 CI_D1
PCM_A2 6 R3 3 CI_A2 PCM_D2 6 R3 3 CI_D2
PCM_A3 5 R4 4 CI_A3 5 R4 4

R186 R234
22R 22R
PCM_A4 8 R1 1 CI_A4 PCM_D4 8 R1 1 CI_D4
PCM_A5 7 2 CI_A5 PCM_D5 7 2 CI_D5
E PCM_A6 6
R2
3 CI_A6 PCM_D6 6
R2
3 CI_D6 E
R3 R3
PCM_A7 5 R4 4 CI_A7 PCM_D7 5 R4 4 CI_D7

R212 R221
22R 22R
PCM_A8 8 R1 1 CI_A8 PCM_OE 8 R1 1 CI_OE
PCM_A9 7 R2 2 CI_A9 PCM_IORD 7 R2 2 CI_IORD
PCM_A10 6 R3 3 CI_A10 PCM_CE 6 R3 3 CI_CE
PCM_A11 5 R4 4 CI_A11 PCM_WE 5 R4 4 CI_WE

R201 R173
22R 22R
PCM_A12 8 R1 1 CI_A12 PCM_WAIT 8 R1 1 CI_WAIT
PCM_A13 7 R2 2 CI_A13 PCM_RST 7 R2 2 CI_RST
PCM_A14 6 R3 3 CI_A14 PCM_REG 6 R3 3 CI_REG
PCM_IRQA 5 R4 4 CI_IRQA 5 R4 4

F PCM_IOWR
R208
CI_IOWR F
22R

VESTEL PROJECT NAME : 17mb130p-r1 A3

SCH NAME :CI_NAND T. SHT:10
DRAWN BY :<YOUR NAME HERE> 27-06-2016_11:26
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8
R120

3V3_STBY
4k7 3V3_VCC

3V3_VCC
R483
4k7 3V3_VCC R206
R121 39k 24V_VCC
4k7 3V3_VCC R218
15k 12V_VCC
PROTECTION

STBY_ON/OFF
R122 R210
HSYNC_BS P27
A 33R PWM0 220R 5V_VCC A

R518

R222
4k7

4k7
3D_SYNC R28 PWM1 3V3_VCC
12V_VCC
BACKLIGHT_DIM N28 PWM2 3

2
25V100n
T22 U106 VCC

1N4148
R123 NC_TEST

BAW56
R215

C166

R104
120k

D102

D100
MAX809LTR RST GND

10k
VSYNC_BS 33R 3

C872 ILOGO AF6 PWM_PM 2 1

100n AB2

3V3_STBY
R525 VID0 CORE_VID0

1
3V3_VCC
3

3V3_STBY 4k7 KEYBOARD D4 SAR0 VID1 AB3 CORE_VID1 5V_VCC

HP_AMP_MUTE D5 SAR1 VID2 AA4 CPU_VID0 R230
2
Q101 R145
PANEL_VCC_ON/OFF C5 SAR2 VID3 Y4 CPU_VID1 R223 4k7 BC848B 2 1
24V_VCC
33k
AMP_MUTE B5 SAR3 4k7 AUX_RESET
1
R144
C106

R100

2
47k

PROTECT
POWER_SENSE E4 SAR5/PW_DET 7 LED0 AD4 LED1 100u 5k1

BAW56
D108
LED1 AC4 LED2 CORE_RESET 6V3 3 R146
2 1
AE11
R329 U114 WOL WOWL_DET S210 10k 12V_VCC

S101

S100
SPI_SCK 8 R1 1 G6 SPI_CK R147

1
7 R2 2 H6
SPI_SDI
6
SPI_DI MSD91QV01 4k7 3V3_STBY 3k9
SPI_SDO R3 3 H5 SPI_DO R492 R105 R114
SPI_CS1N 5 R4 4 J6 SPI_CZ1/GPIO_PM6 4k7 4k7 3V3_STBY 2 1 2 1
3V3_VCC
3V3_STBY 10k 10k
22R R108 R466

2
AE6
B GPIO_PM0 4k7 3V3_STBY B

BAW56
AUX_RESET R115

D103
W2 BC858B
3V3_STBY 4k7 GPIO_PM3 PROTECT R465 Q103
1
10k
2
3

S190 R380 GPIO_PM4/PW_CTRL W3 STBY_ON/OFF TP102 1

VGA_SCL GPIO_PM7 AA5 TOUCHPAD_SDA Q108 BC848B

1
C107 3 R124
DEBUG_RX AD10 DDCA_CK/UART0_RX GPIO_PM8 AA6 TOUCHPAD_SCL
2
1 2
3V3_VCC
100n R110 10k
DEBUG_TX AC10 DDCA_DA/UART0_TX GPIO_PM10 A5 WOWL_EN 10V Q102
1
2 1 2
10k
VGA_SDA S189
3V3_STBY 4k7
R382
SPI_SDO_BS
SPI_XCS_BS
N27
M26
GPIO2/EJ_TCK
GPIO3/EJ_TMS
GPIO_PM9 C6 STR_EN
SPI FLASH 1
BC848B
R138
100R
R137
47k
1V1_VCC_CPU

2
SPI_SDI_BS M27 GPIO4/EJ_TDI

C382

C874

R109

2
100n
10V

100n
10V

10k
SPI_SCL_BS M28 GPIO5/EJ_TDO

BAW56
D114
R233 R328 D120 3

AH6

TP153

1
3V3_VCC 4k7 GPIO_PM1/PM_TX1 FLASH_WPN1 3V3_STBY 4k7 3V3_STBY
GPIO_PM5/PM_RX1 AH5 WIFI/BT_ENABLE TP154
U115 Q107

1
1N5819
CI_PWR_CTL AC15 GPIO9/TX2
MX25L512 BC858B 1V5_VCC
SPI_CS1N
USB_ENABLE AD15 GPIO10/RX2 1 CS# VCC 8 R327 TP152 R130
3D_ENABLE AF16 GPIO11/TX3 2 SO HOLD# 7 4k7 6k8 1V5_DDR_STR
SPI_SDO 3V3_VCC
3D_BOOST AG16 GPIO12/RX3 GND_TEST P21 TP149 3 WP# SCLK 6
SPI_SCK

2
4 GND SI 5 10k

BAW56
D115
2 1

C 3V3_VCC 4k7 TP150 4k7 3V3_STBY R129 3

C
R249 R322 TP156 R320
3V3_STBY 4k7

1
SPI_SDI
R323 NC 1V_VCC_CORE
HP_DETECT AC11 GPIO30/SCK4 FLASH_WPN1 33R R136
AD11 S165

TP151
AMP_RST GPIO31/SDA4 6k8 3V3_VCC

SYS_SCL P26 DDCR_CK 1

10k 2

SYS_SDA N26 DDCR_DA R135

R387
3V3_VCC 4k7 TP167
R386
3V3_VCC 4k7 TP162
CN117 LED

10
4k7 1 R311

9
3V3_VCC
R490 12V_VCC 10k 1k POWER_SENSE
R307 needs GND shielding

R312

D119

C3V6
C873

330pF
1k

1n2
1

1
D CHIP CONFIGURATION 1k F160 D
TP209

TP208

TP215

TP207

TP214

TP219

TP218

TP213
5V_STBY
3V3_STBY 3V3_STBY 3V3_STBY 3V3_STBY D137 PESD9N5VH
R503

R500

R421

R318
4k7

4k7

4k7

4k7

nc nc nc D138 PESD9N5VH
2

2
S202

S201
S203
LED1 ILOGO LED2 SPI_SDI
1

1
CN114
R504

R498

R418

R321
4k7

4k7

4k7

4k7

TOUCHPAD_SCL

TOUCHPAD_SDA

nc KEYBOARD_ONBOARD
R463 2
C490
10k 3V3_STBY 100n
1

1k 10V KEYBOARD_ONBOARD
R464 F152 C5V6
1 2
F158 47R KEYBOARD 2 1

F151 1k TP182 D135

1k 3V3_STBY
E E

TP193

R475
SCANNING BACKLIGHT 5V_STBY D133 F153

R487

SOURCE R474
470R
3

10k

2k
R497 TOUCHPAD_SCL

TP191
R519 F156 C5V6 Q144 2 1
10k
2
ILOGO 1k
TP224 1
10k 2
IR_RC
BC848B
TOUCHPAD_SDA + -
R488
150R

C502
CN100

50V
R113 C501 1k 1
F154 1k
1n
1 TP225 33R VSYNC_BS TP187

D131
1 2

1
27p 50V

TP184

TP192

TP197

TP198
2 TP226 33R HSYNC_BS R118

1
TP186
1 2
R112 10k

CDA4C16GTH
3

3 TP227 1
10k 2
3V3_VCC R493 3 SW100
2

R119 LED2 1
10k
2 2
Q141 R478
R485

220R
R495

220R
R484

R479

E2 E1
10k

10k

4 TP228 1 8 BC848B Q140 2 1 2

R1 SPI_SCL_BS 10k

8
1 BC848B
2 R2 7

G4

G3

G2

G1
1
1

5 TP229

CN113
SPI_SDI_BS
LED1

6
6 TP230 3 R3 6
SPI_SDO_BS
Q142
4 R4 5 Q143
7 SPI_XCS_BS BC858B
F 33R R116 BC858B
KEYBOARD 3-WAY F
PESD9N5VH D144

PESD9N5VH D145

PESD9N5VH D146

PESD9N5VH D147

PESD9N5VH D148

PESD9N5VH D149

1 2
8 R111 10k 3V3_VCC
2

1 2
10k
220R
R489

220R
R494

R117

VESTEL PROJECT NAME : 17mb130p-r1 A3

1

5V_STBY
SCH NAME :GPIOs_SPI T. SHT:10
DRAWN BY :<YOUR NAME HERE> 27-06-2016_15:27
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8

VBYONE SOCKET
OPTIONS TABLE PANEL SUPPLY SWITCH

CN104
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

TP112
A A
PANEL_VCC
MEGA_DCR_IN
S140
OP_PIN38 common

1
S139 12V_VCC PANEL_VCC

OP_PIN36
OP_PIN35
OP_PIN34
OP_PIN33
OP_PIN32
OP_PIN31
OP_PIN30
OP_PIN29
OP_PIN28
OP_PIN38
OP_PIN37

6
VBY_HTPDN
VBY_LOCKN

VBY_0P

VBY_1N
VBY_1P

VBY_2N
VBY_2P

VBY_3N
VBY_3P

VBY_4N
VBY_4P

VBY_5N
VBY_5P

VBY_6N
VBY_6P

VBY_7N
VBY_7P
VBY_0N

2
S137

FDC642P
C155

R204
2

220n
25V
33k

Q116
PAN_SCL

1
S133

1
MEGA_DCR_OUT
S136

1
3D_SYNC_I R209
1 2
R262 47R
PANEL_VCC 33k OP_PIN37
R270 12V_VCC
10k

6
FDC642P
S138

Q115
3D_SYNC
B C188 TP129 PANEL I2C BUFFER PANEL_VCC
R273
OP_PIN36
B
G6F_VBY0N VBY_0N 33k
100n
C189 TP130 R275

1
3V3_STBY
VBY_0P 10k

3V3_VCC
G6F_VBY0P 100n R213
1 2
C186 TP128 47R

3V3_VCC
G6F_VBY1N VBY_1N S135
100n 3D_EN
C187 TP127

1
G6F_VBY1P VBY_1P
opt.

R214
100n S134

33k
C184 TP126 PAN_SDA
G6F_VBY2N VBY_2N R505 R264

R516

R509
100n

4k7

4k7
PANEL_VCC OP_PIN35

2
C185 TP125 10k 33k
G6F_VBY2P VBY_2P R263 3
100n
C180 TP124 10k R205
VBY_3N SYS_SCL BSN20 2 1 2
Q117
G6F_VBY3N 100n PAN_SCL PANEL_VCC_ON/OFF 10k
C181 TP123 S131 BC848B
C163

Q120
1

G6F_VBY3P VBY_3P PAN_SDA OP_PIN34 1n

100n 50V
C182 TP122 S125
G6F_VBY4N VBY_4N PAN_SCL OP_PIN33

3V3_VCC
100n
C183 TP121
C G6F_VBY4P 100n
VBY_4P
PANEL_VCC
R265
OP_PIN32
C
C177 TP120 33k
G6F_VBY5N VBY_5N R254
100n
C178 TP119 R506 10k
G6F_VBY5P VBY_5P 10k
100n
TP118 S126
C175 3D_EN
G6F_VBY6N VBY_6N
100n
TP117 R274
C176 SYS_SDA PANEL_VCC OP_PIN31
G6F_VBY6P VBY_6P PAN_SDA 33k
100n
C173 TP116 R253
Q123
BSN20

G6F_VBY7N VBY_7N 10k

100n
C174 TP115
VBY_7P
G6F_VBY7P

F112 1k
100n
TP113
3D_SYNC_I
S119

R246
DIMMING
G6F_LOCKN VBY_LOCKN PANEL_VCC 33k OP_PIN30
R245 S130
G6F_HTPDN VBY_HTPDN 10k 3V3_VCC
F111 1k TP114 S129
D S118 5V_VCC D
3D_SYNC OP_PIN29

MEGA_DCR_OUT
S117

R520 R261 BC858B

PANEL_VCC 33k 4k7 Q125

R260
1k
OP_PIN28 C196
S116 R243
220p 100R
8 1
R1

S127
50V
S124 7 R2 2
T27 LVSYNC R269
S122 S128 DIMMING
U27 LCK 6 BACKLIGHT_DIM 4k7 Q124 6 R3 3
U26 LDE BC848B
T28 LHSYNC
U114 C197 5 R4 4
S123
MSD91QV01 MEGA_DCR_IN 1 2 R259 C190
V27 Q121
E B0M[R_ODD7] 220p 4k7 10u E

2
V28 B0P[R_ODD6] BC848B 16V

R252
50V

10k
W28
W27
B1M[R_ODD5]
B1P[R_ODD4]
3D ENABLE C194

Y27

1
G6F_VBY0N B2M[R_ODD3]/VB1_0N 220p 50V
3V3_VCC

3V3_VCC

G6F_VBY0P AA26 B2P[R_ODD2]/VB1_0P

G6F_VBY1N AA28 BCKM[R_ODD1]/VB1_1N
G6F_VBY1P AB26 BCKP[R_ODD0]/VB1_1P
G6F_VBY2N AB27 B3M[G_ODD7]/VB1_2N
G6F_VBY2P AC26 B3P[G_ODD6]/VB1_2P
G6F_VBY3N AD26 B4M[G_ODD5]/VB1_3N
G6F_VBY3P AD27 B4P[G_ODD4]/VB1_3P
100R
R240

R248
4k7

G6F_VBY4N AE26 A0M[G_ODD3]/VB1_4N

G6F_VBY4P AE28 A0P[G_ODD2]/VB1_4P
AF26 S120
G6F_VBY5N A1M[G_ODD1]/VB1_5N 3D_EN
G6F_VBY5P AF27 A1P[G_ODD0]/VB1_5P
G6F_VBY6N AG27 A2M[B_ODD7]/VB1_6N
R239
4k7

G6F_VBY6P AG28 A2P[B_ODD6]/VB1_6P ncQ122 4k7 3D_ENABLE

AH27 BC848B
F 3V3_VCC 2
R216
1
G6F_VBY7N
AH26
ACKM[B_ODD5]/VB1_7N R247 F
10k G6F_VBY7P ACKP[B_ODD4]/VB1_7P
G6F_LOCKN AF25 A3M[B_ODD3]/LOCKN
G6F_HTPDN AG25 A3P[B_ODD2]/HTPDN
3V3_VCC 2
10k 1 AG24 A4M[B_ODD1]
R217 AH24 A4P[B_ODD0] VESTEL PROJECT NAME : 17mb130p-r1 A3
SCH NAME :VBYONE T. SHT:10
DRAWN BY :<YOUR NAME HERE> 20-06-2016_10:18
1 2 3 4 5 6 7 8 AX M
 1 2 3 4 5 6 7 8

L112
A_OUT1B

Y3
4u7 C426
6W/8W/10W 10u
C507
LINE_IN_0L SAV_L_IN 220n
LINE_IN_0R Y2 1 PD VDDLA 24 50V
SAV_R_IN AMP_EN VDD_AUDIO

TP204

TP210
A C421 4u7 R491
2 23 A
C392 4u7 100R ERROR N.C.2
LINE_IN_2L Y1
SC_AUD_L_INCLOSE TO MSTAR IC
LINE_IN_2R AA3 3 SDATA LA 22 A_OUT1A
SC_AUD_R_IN AOSDATA0 C503
C391 4u7 220n 4

C352

C353

C334

C335
AOLRCK 4 LRCIN GNDL 21 L113 50V
R496 A_OUT1A 3
3n3 3n3 3n3 3n3 100R 5 SDA LB 20 A_OUT1B 10u
L115
S150 SYS_SDA
LINE_OUT_0L AB5 SC_DAC_L R499 U123 A_OUT2B 2
AB6 S151 6 19 10u
LINE_OUT_0R SC_DAC_R SYS_SCL 100R SCL VDDLB VDD_AUDIO
LINE_OUT_2L AC5 AD82587D 1
C512
LINE_OUT_2R AC6 AMP_RST 7 RESET VDDRB 18 220n
VDD_AUDIO
C505 50V CN115
AD5 S147 8 17

TP211

TP205
EARPHONE_OUT_L S148 HP_LEFT DGND RB A_OUT2B
EARPHONE_OUT_R AD6 HP_RIGHT 100n
C419 3V3_AMP 9 DVDD GNDR 16
M4 S179
ARC0 HDMI_ARC R501 C514
1u 6V3 10 15
3V3_AMP 4k7 SA0 RA A_OUT2A 220n
C3844u7 R502 L114 50V
AA2 11 14 A_OUT2A
B AUVAG
AA1 CLOSE TO MSTAR IC AOMCLK 100R MCLK N.C.1
10u B
3 AUVRM C375
F131 C509 12 BCLK VDDRA 13
100n AOBCK VDD_AUDIO
U114 12p
220R 50V
MSD91QV01 1
S195
2 5V_VCC
1 2 VDD_AUDIO
NC1_TP T21 TP144 S196
R314
NC2_TP R20 TP143 22R

2
NC3_TP R21 TP222 8 R1 1 AOLRCK

R469
10k
7 R2 2 AOSDATA0
I2S_OUT_BCK E6 6 R3 3 16V
AOBCK
E5 5 R4 4 100u

1
I2S_OUT_MCK AOMCLK
I2S_OUT_WS
I2S_OUT_SD
I2S_OUT_SD1
F4
F6
F5
12p C349

12p
12V_VCC
S114

C513
VDD_AUDIO POP NOISE 2
1

C491
10k
2

C497

C506

C510

C511
S113

2
100n

100n

100n

100n
I2S_OUT_SD2 G5 24V_VCC 220u R462

R472

R468
10k

10k
C354 10V

3V3_VCC
5V_VCC
C

1
C
K6 BC858B
SPDIF_IN BACKLIGHT_ON/OFF_OUT Q139
SPDIF_OUT J5
SPDIF_OUT

2
F157

R470

R471

C869

100k
R473
4k7

4k7

100n
3V3_VCC 3V3_AMP
60R C508

1
100n
16V AMP_EN
3 3

R446 C480 R461

F159
BC848B

1k
AMP_MUTE 1
10k
2 2
100n Q138
2
33k
Q137
16V

2
1 1
BC848B
NC

100k
R467
1
R454
D HP_AMP_EN 4k7 3V3_VCC D
R528
AMP_MUTE 1
10k
2

3 3

R460 C487 R459

HP_AMP_MUTE 1 2 2
BC848B 2
10k Q136 100n Q135 33k
16V
1 1
BC848B

SCART AUDIO AMP HEADPHONE OUTPUT

10V
HEADPHONE AMP

C436
2

220p
50V
C467 C481 C483 1
R435 R448 R451
E

1
SC_AUD_R_OUT
2
33k
1

1
R457
2
10V
HP_RIGHT
2
10k
1 1
10k
2
HP_LEFT R409 S191 TP169 TP174
2 E
10u 33k 1u 1u HP_OUT_L 47R
1

1
C465 C458
R449

R450
33k

33k
12p SC_AUD_L_OUT 2
10k 1
6
50V 10u 1 -INR 10 R433 TP177 R414
-INL S194
C468 3
2

2
R437 C486 HP_OUT_R 47R
SC_DAC_R 68k 1 -INR 10 12p HP_OUT_R 2 OUTR OUTL 9 HP_OUT_L
-INL

2
50V 1u U120 4
C466 C437 C452

R407

R422

C456
1u

2
10k

10k

220p
50V
150p 2 OUTR OUTL 9 R452 6V3 3 EN GND 8
6V3 HP_AMP_EN 10n 10n
R455

R456

R434

R410
JK104
4k7

4k7

47R

47R
50V 5

1
U119 68k SC_DAC_L AD22657B 16V 16V
3 EN GND 8 4 PVSS PVDD 7

1
AMP_EN C453
AD22657B C479 NC NC 7
C488
4 PVSS PVDD 7 150p 1u 5 CN CP 6
C457 50V 6V3 F150 1k TP171
1u 5 CN CP 6 3V3_VCC R447
6V3 C492 HP_DETECT 100R
C482

100n

F146 1k 10u
C489

6V3

1
1u

3V3_VCC 10V

R517

R453

D130

C5V6
4k7

4k7
C484
C464

6V3

C485

100n
1u

F 10u
10V
F
3V3_STBY 3V3_VCC

VESTEL PROJECT NAME : 17mb130p-r1 A3

SCH NAME :AUDIO AMPs T. SHT:10
DRAWN BY :<YOUR NAME HERE> 20-06-2016_14:02
1 2 3 4 5 6 7 8 AX M
 F
E
D
C
B
A
25V
10u
C333
3V3_STBY

AC7
AC8
AC9
AD7
AD8
AD9
AE3
AE8
AE9
AF2
AF8
AF9
AG2
AG6
AH1

AB21
AB22
AB28
AC14
AC27
AD28
AE14
AE27
AF10
AF14
AF15
AF23
AF24
AG12
AG26
AH11
AH28
3V3_VCC

60R
60R

F123
F136
60R

220R
F125
220R
F126
220R
F129
220R
F130
F128
220R
F127
C5V6
D140

16V
100n
C345

GND241
GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250
GND251
GND252
GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272

1
1

AB20 GND240 GND104 K17

25V
10u
25V
10u

C322
C413
AB19 GND239 GND103 K11

16V
100n
C344
AB18 GND238 GND102 K10

16V
100n
16V
100n
16V
100n
16V
16V
100n

C328
C325
C348
C329

AB17 GND237 GND101 J26

16V
100n
100n

C340
C346
AB16 GND236 GND100 J25

16V
100n
16V
100n

C320
C411
AB9 GND235 GND99 J23

16V
100n
C342
AB8 GND234 GND98 J22

16V
100n
16V
100n
16V
100n
16V
100n

C326
C327
C347
C330

AB7 GND233 GND97 J21

16V
100n
16V
100n

C339
C341

AA27 GND232 GND96 J19

16V
100n
16V
100n

C321
C408
AA25 GND231 GND95 J17
16V
100n
C343

AA24 GND230 GND94 J16

AVDD_USB
AA23 GND229 GND93 J15

AVDD_AU33

1u
AVDD_EAR33
AVDD33_ADC
AVDD33_LAN
AVDD_DMPLL

AA18 GND228 GND92 J11

16V
100n

C319
C407
AA17 GND227 GND91 J10
AA16 GND226 GND90 H25
AA11 GND225 GND89 H24
AA8 GND224 GND88 H23

16V
100n
C405
AA7 GND223 GND87 H22

AVDD_LPLL
Y26 GND222 GND86 H21
Y24 H20

2
2

GND221 GND85
Y23 GND220 GND84 H19

16V
100n
C404
Y18 GND219 GND83 H18

1V5_DDR_STR
1V_VCC_CORE

AVDD_DDR

Y17 GND218 GND82 H17

1V5_DDR_STR
1V5_VCC
1V_VCC_CORE

Y16 GND217 GND81 H16

Y11 GND216 GND80 H15

NC 16V
100n
C400
Y10 GND215 GND79 H14
Y9 H13

W/STR
GND214 GND78
220R
F116

Y8 GND213 GND77 H12

220R
F166
W26 GND212 GND76 H11

16V
100n
60R
60R

C401
F162
F165
220R
F121
F115

W25 GND211 GND75 H10

220R0R

W24 GND210 GND74 H9

W23 GND209 GND73 H1
W22 GND208 GND72 G27
25V
10u

16V
100n
16V
100n

C886
C883
C198

W17 GND207 GND71 G25

16V
100n
C292

W16 GND206 GND70 G24

6V3
2u2

16V
100n
C860
C207

W14 GND205 GND69 G23

W13 GND204 GND68 G22

16V
100n
16V
100n
16V
100n

C885
C884
C227

W12 GND203 GND67 G21

NC 16V
100n
C293

W11 GND202 GND66 G20

16V
100n
16V
100n

C861
C203

W9 GND201 GND65 G19

3
3

VDDP33
V26 GND200 GND64 G18
16V
100n
C226

V25 GND199 GND63 G17

V24 GND198 GND62 G16
16V
100n
C870

V23 GND197 GND61 G15

V22 GND196 GND60 G14
V21 G13
AVDD_DDR_STR
AVDD15_MOD
DVDD_DDR

GND195 GND59
V17 GND194 GND58 G12
AVDDL_MOD

16V
100n
C871

V16 GND193 GND57 G11

1V_VCC_CORE

V15 GND192 GND56 G10

V14 GND191 GND55 G9
V13 GND190 GND54 F10
V12 GND189 GND53 F9

U114
V11 F8
AVDD_DDR_B

GND188 GND52
22u
C205

6V3

V10 GND187 GND51 F7

V9 E27

MSD91QV01
GND186 GND50
U22 GND185 GND49 E25
NC 16V
100n
C303
1u

U21 GND184 GND48 E23

C350

U20 GND183 GND47 E21 G7 VDDC1 DVDD_NODIE Y12

25V
10u
C287

U19 GND182 GND46 E19 G8 VDDC2

22u
6V3

U18 E17 H7
C225

GND181 GND45 VDDC3

4
4

U17 GND180 GND44 E15 H8 VDDC4 AVDD_NODIE Y7

AVDD33_LAN
U13 GND179 GND43 E13 J7 VDDC5
NC 16V
100n
C304

U12 GND178 GND42 E11 J8 VDDC6

22u
6V3

U11 E10 J9
C209

GND177 GND41 VDDC7

U10 GND176 GND40 E9 K7 VDDC8 DVDD_DDR1 M10
T26 GND175 GND39 E8 K8 VDDC9 DVDD_DDR2 N9
NC 16V
100n
C297

T20 GND174 GND38 E7 K9 VDDC10 DVDD_DDR3 N10

DVDD_DDR
22u
6V3

T19 E2 L7
C236

GND173 GND37 VDDC11

T18 GND172 GND36 D28 L8 VDDC12
T17 GND171 GND35 D26 L9 VDDC13 AVDD_DDR_A1 M14
NC 16V
100n
C294

T12 GND170 GND34 D24 M9 VDDC14 AVDD_DDR_A2 N14

22u
1V_VCC_CORE

6V3

T11 D22 M8 P14

C247

GND169 GND33 VDDC15 AVDD_DDR_A3 AVDD_DDR

T10 GND168 GND32 D20 M7 VDDC16 AVDD_DDR_A4 N15
T9 GND167 GND31 D18 AVDD_DDR_A5 M15
NC 16V
100n
C296

R19 GND166 GND30 D16 V18 VDDC_CPU1

16V
100n
100n

C302

R18 GND165 GND29 D14 V19 VDDC_CPU2

C283

R17 GND164 GND28 D12 V20 VDDC_CPU3 AVDD_DDR_B1 K12

R15 GND163 GND27 D10 W18 VDDC_CPU4 AVDD_DDR_B2 K13
R14 GND162 GND26 D9 W19 VDDC_CPU5 AVDD_DDR_B3 K14
25V
10u

NC 16V
100n
C295
C276

R13 GND161 GND25 D8 W20 VDDC_CPU6 AVDD_DDR_B4 J12 AVDD_DDR_B

R12 D7 W21 J13

5
5

GND160 GND24 VDDC_CPU7 AVDD_DDR_B5

R11 GND159 GND23 D6 Y19 VDDC_CPU8 AVDD_DDR_B6 J14
R9 GND158 GND22 C22 Y20 VDDC_CPU9
16V
100n
100n

C305
C281

R8 GND157 GND21 C21 Y21 VDDC_CPU10 AVDD_DDR_DRAM1 K21

R7 GND156 GND20 C20 Y22 VDDC_CPU11 AVDD_DDR_DRAM2 K26 AVDD_DDR_STR
R1 GND155 GND19 C13 AA19 VDDC_CPU12
L24 GND122 GND18 C12 AA20 VDDC_CPU13
100n
C851

L23 GND121 GND17 C11 AA21 VDDC_CPU14 AVDD_DDR_VBP_A J27 AVDD_DDR

L20 GND120 GND16 C8 AA22 VDDC_CPU15 AVDD_DDR_VBP_A_DM M13
1V1_VCC_CPU

L19 GND119 GND15 C3

100n
C854

L18 GND118 GND14 B27 AVDD_DDR_VBN_A K28

1V5_VCC
1V5_DDR_STR
1V1_VCC_CPU

L17 GND117 GND13 B25 AVDD_DDR_VBN_A_DM N13

L16 GND116 GND12 B23 H27 NC1
L15 GND115 GND11 B18 L13 NC2
L14 GND114 GND10 B16 G28 NC3 AVDDL_MOD1 R10
Close to IC

AVDDL_MOD
L11 GND113 GND9 B14 L12 NC4 AVDDL_MOD2 T13
22u

60R
60R

100n C855
F118
F164
6V3
C208

L10 GND112 GND8 B9 AA15 NC6 AVDDL_MOD3 AH23 100n C856

K25 GND111 GND7 A28 Y15 NC7 NC_1 W15
K24 GND110 GND6 A26 NC5 J18
16V
100n
C233

K23 GND109 GND5 A24

K22 GND108 GND4 A17

6
6

25V
10u
25V
10u

C231
C224

K20 GND107 GND3 A15 P22 GND_EFUSE AVDD15_MOD1 K15

K19 GND106 GND2 A8 AVDD15_MOD2 K16
AVDD15_MOD
NC 16V
100n
C243

K18 GND105 GND1 A1 9

16V
100n
16V
100n

C268
C286

AVDD_MOD AA14
U114 VDDP33
NC 16V
100n
C275

GND154
GND153
GND152
GND151
GND150
GND149
GND148
GND147
GND146
GND145
GND144
GND143
GND142
GND141
GND140
GND139
GND138
GND137
GND136
GND135
GND134
GND133
GND132
GND131
GND130
GND129
GND128
GND127
GND126
GND125
GND124
GND123

MSD91QV01
16V
NC100n
16V
100n

C239
C284

AVDDL_MHL3_1 N7
P9
P8
P7
M3

N8
P20
P19
P18
P16
P15
P13
P12
P11
P10
N22
N21
N20
N19
N18
N17
N16
N12
N11
M23
M22
M21
M20
M19
M18
M17
M16
M12
M11

AVDDL_MHL3_2 1V_VCC_CORE
16V
100n
C234

NC_2 W10
AVDD3P3_MHL3_1 AA12
16V
100n
16V
100n

C241
C246

AVDD3P3_MHL3_2 AB12
VDDP33
16V
100n
C232

16V
NC100n
16V
100n

C242
C245

VDDP_3318_A AA10 VDDP33

VDDP_3318_C AB11
7
7

16V
NC100n
16V
100n

C270
C273

PADA_EMMC_CTRL AE15
16V
100n
16V
100n

C269
C272

AVDD3P3_DADC W7
AVDD33_LAN
AVDD3P3_DMPLL AA9
AVDD_DMPLL
SCH NAME :MAIN_POWER
16V
100n
16V
100n

C240
C244

AVDD3P3_ETH W8

AVDD3P3_USB2_1 U7
DRAWN BY :<YOUR NAME HERE>

AVDD3P3_USB2_2 T7
AVDD_USB
16V
NC100n
16V
100n

C271
C285

NC_3 T8

AVDD3P3_ADC1 V7
AVDD3P3_ADC2 V8
AVDD33_ADC
16V
100n
16V
100n

C282
C235

AVDD_AU33 U8
AVDD_AU33
AVDD_EAR33 U9
AVDD_EAR33
GS101
GS100
16V
100n
16V
100n

C291
C274

AB14
8
8

VDDP1
VDDP2 AB15
VDDP33

AVDD_LPLL1 AA13
25V
10u
C204

AB13
VESTEL PROJECT NAME : 17mb130p-r1

AVDD_LPLL2

AVDD_PLL_A Y13
AVDD_LPLL
AVDD_PLL_B Y14
AVDD_DDR

A3
T. SHT:10
20-06-2016_10:18
F
E
D
C
B
A

AX M
 1 2 3 4 5 6 7 8
CN102
12 11 12V_STBY
DC/DC 1 SW2 LDO 1
10 9 power_pin9
5V_STBY/VCC STEP-DOWN (3A) 5V_VCC SWITCH
8 7 DIMMING
12V_VCC
F107
60R
33p
5V_STBY 5V_VCC 3V3_STBY LDO
C108

4
U124
A 6 5 BACKLIGHT_ON/OFF F106 VFB 10u
LM1117 A

NTGS3446
C131 10V
3 IN OUT 2

Q100
4 3 STBY_ON/OFF_NOT 60R R169 R160 R158
60R 120k R2 4k7 22k GND VOUT
power_pin2 2 1 power_pin1

TP141
R1 1 4
12V_STBY F109 100nC127 C126 C125 F102 TP101 R132

3
2
10u 10u 60R 12V_STBY 33k
12V_STBY 60R 16V 16V 16V 5V_VCC U112
CN101 LM1117
F108 F101 R128
TP104 2 1 12V_VCC 2 1
47R 2 3 IN OUT 2 3V3_STBY
1
33k 5V_STBY
R152 60R R131 C323 C331 C332

D117

C5V6
4 3 power_pin9S108 5V_STBY 2 1 1 2
F103
100n
C100 10u
ADJ VOUT
10u 10u
10k 10k

R133
16V 1 4

1k
TP105 1 1 TP106 R159 60R 10V 10V 10V
6 5 DIMMING 1 EN VIN 8 TP206
1 TP108 U101 C116 L101
8 7 BACKLIGHT_ON/OFF 2 VFB VBST 7 5V_STBY
VFB R140

C5V6D106
10u Q106
1 TP107 TPS54528 100n C118 C119 100n 60R STBY_ON/OFF_NOT
2
10k
1

10 9 STBY_ON/OFF_NOT 3 VREG5 SSW 6 10u 10u F104 BC848B

10V 10V 16V C120
power_pin212 S111 4 VSS
B 11 C132 GND 5 B
S112 1u

50V
8n2
TP110 1 24V_VCC 16V
S109
power_pin1 C133
S110
3D_BOOST

DC/DC 2 DC/DC 3
SW1 3V3_VCC DC/DC (3A) 1V5_VCC DC/DC (2A)
12V_VCC SWITCH
R101 R1 R102 R255 R1 R266
S102 1 2
37k4 4k7 47k 51k
S103 33k
C102 C195
4k7
C TP103 C
12V_STBY 12V_VCC 2p NC 2p NC
50V 50V
4

C110

TP100

C200

TP131
100n

100n
16V C199
FDC642P

C5V6

D101

D116
C5V6
1

Q105

C105 16V 16V 16V

C113

R139
2

220n
25V

33k

6 BOOT GND 1 C104 6 BOOT GND 1 3u3 C201

L100 L105
1

U100 10u 10u U107 10u 10u

5 EN LX 2 5 EN LX 2
2

3V3_VCC 1V5_VCC
3

RT6213BHGJ6F 3u3 F100 RT6213BHGJ6F F114

R127
1 2 4 FB VIN 3 12V_VCC 4 FB VIN 3 12V_VCC
47R
C109 16V 16V 60R C191 C192 16V 60R
1

R107 100n C103 C101 R271 100n 16V C193

R126
33k

R103 R2

R2
1
10k
2
16V 10u 10u 1
10k
2
16V 10u 10u

100k
R256
12k
2

R106

R272
4k7

4k7
R125
Q104
Vout=0.765x(1+(R1/R2)) Vout=0.765x(1+(R1/R2))
STBY_ON/OFF 22k
BC848B
D D

Backlight On/Off Circuit

DC/DC 4
DC/DC 4 1V_VCC_CORE DC/DC (8A)

C140

100n
10V
R163
1V_VCC_CPU DC/DC (2A)

TP111
R197 1
4k7 2 5V_VCC
8k2 R189
R200 BACKLIGHT_ON/OFF 1
4k7 nc 2 R175
12V_VCC 33k L104 1
4k7 2 3V3_STBY
R183 R1 R182 1V_VCC_CORE R188
1k8 10k 2u4 Q113 4k7 BACKLIGHT_ON/OFF_OUT
1 2

BC848B
3V3_STBY

C158 C159 C169 C168

S115

C145

100n
10V
C141

C151
22u 22u 22u 22u
R172

R171
8k2

15k

E 3K9 51K 6V3 6V3 6V3 6V3 E

560p
50V
2p NC C146 C152
50V 100n 22n
16V 6V3
C147

TP132

R199
100n

10k
C153
180k
R161

40k2
R170

C5V6

D112

13

12

11

10

C154 C148
9
2

6 BOOT GND 1 3u3 R1 STBY On/Off Circuit

R524

R523

39p
4k7

4k7

C157
BOOT

PH_1

PH_0

EN

SS/TR

U104 L103 10u 10u 50V

5 EN LX 2 1V1_VCC_CPU 4k7

R168
20k
Q112

3V3_STBY
1

RT6213BHGJ6F F110 R202 120K NC

R180

R179
150R
4n7

4k7
2N7002 2N7002 4 FB VIN 3 14 8
12V_VCC PWRGD U103 COMP 4K7 R174
Q111 16V 60R STBY_ON/OFF_NOT
R192 C142 16V TPS54821 3V3_STBY 1
10k
2

CPU_VID0 1k R194 100n C144 C143 1 RT/CLK VSENSE 7

R167

2
20k
PVIN_0

PVIN_1

1
10k
2
16V 10u 10u 0R
R184

GND_0

GND_1

R164
59k

4k7
R191 0R
R181
100k

VIN

R178 NC
CPU_VID1 1k C887 CORE_RESET 9k1 1K8
R193

R177
120k
2 1 3
4k7

1
100n S209 R176

R166

2
2k7
16V STBY_ON/OFF 22k
2
Q114
2

0R

R521

R522
4k7

4k7
BC848B
R185
4k02

C136
47K

100n
16V
1

F F
10k

1
10K NC
R190

Q109 Q110 NC
R165
2N7002 2N7002 CORE_VID0
12V_VCC 1k
10u 10u 10u 10u
C167
C164 C156
C165 R157
1k CORE_VID1
VESTEL PROJECT NAME : 17mb130p-r1 A3
SCH NAME :POWER T. SHT:10
DRAWN BY :<YOUR NAME HERE> 27-06-2016_14:55
1 2 3 4 5 6 7 8 AX M