module BCD_to_seven_seg(BCD, sign, seven_seg, no_seven_seg);

input [2:0] BCD;

input sign;
output [7:0] seven_seg, no_seven_seg;

assign seven_seg[0] = !sign;

assign seven_seg[7:1] = (BCD==3'b000)? 7'b1111110:
(BCD==3'b001)? 7'b0000110:
(BCD==3'b010)? 7'b1101101:
(BCD==3'b011)? 7'b1111001:
(BCD==3'b100)? 7'b0110011:
(BCD==3'b101)? 7'b1011011:
(BCD==3'b110)? 7'b1011111:
7'b1110000;
assign no_seven_seg[0] = !(seven_seg[0]);
assign no_seven_seg[1] = !(seven_seg[1]);
assign no_seven_seg[2] = !(seven_seg[2]);
assign no_seven_seg[3] = !(seven_seg[3]);
assign no_seven_seg[4] = !(seven_seg[4]);
assign no_seven_seg[5] = !(seven_seg[5]);
assign no_seven_seg[6] = !(seven_seg[6]);
assign no_seven_seg[7] = !(seven_seg[7]);

endmodule

module full_adder(a, b, cin, s, cout);

input a, b, cin;
output s, cout;

assign s = a^b^cin;
assign cout = (a&b) | ((a^b)&cin);

endmodule

module three_bit_adder(a, b, s, cout);

input [2:0] a, b;
wire cin;
output [2:0] s;
output cout;

assign cin = 1'b0;

full_adder s0(.a(a[0]), .b(b[0]), .cin(cin), .s(s[0]), .cout(carry1));

full_adder s1(.a(a[1]), .b(b[1]), .cin(carry1), .s(s[1]), .cout(carry2));
full_adder s2(.a(a[2]), .b(b[2]), .cin(carry2), .s(s[2]), .cout(cout));

endmodule

module three_bit_substracter(a, b, s, sign);

input [2:0] a, b;
output [2:0] s;
output sign;
wire cin,cinn,coutt;
wire [2:0] ss;

assign cin = 1'b1;

assign cinn = 1'b0;

full_adder s0(.a(a[0]), .b(!b[0]), .cin(cin), .s(ss[0]), .cout(carry1));

full_adder s1(.a(a[1]), .b(!b[1]), .cin(carry1), .s(ss[1]), .cout(carry2));
full_adder s2(.a(a[2]), .b(!b[2]), .cin(carry2), .s(ss[2]), .cout(sign));

full_adder s3(.a(!ss[0]), .b(1'b1), .cin(cinn), .s(s[0]), .cout(carry3));

full_adder s4(.a(!ss[1]), .b(1'b0), .cin(carry3), .s(s[1]), .cout(carry4));
full_adder s5(.a(!ss[2]), .b(1'b0), .cin(carry4), .s(s[2]), .cout(coutt));

endmodule

module mag_comparator(a, b, iguales, salida_igual, salida_num);

input [2:0] a, b;
output [7:0] salida_igual;
output [2:0] salida_num;
output iguales;
wire [3:0] A, B;

assign B[3] = 1'b0;

assign A[3] = 1'b0;

assign A[2:0] = a[2:0];

assign B[2:0] = b[2:0];

wire igual, mayor, menor;

assign igual = (!(A[3]^B[3]))&&(!(A[2]^B[2]))&&(!(A[1]^B[1]))&&(!(A[0]^B[0]));

assign mayor = ((A[3])&&(!(B[3])))||((!(A[3]^B[3]))&&((A[2])&&(!(B[2]))))||((!
(A[3]^B[3]))&&(!(A[2]^B[2]))&&((A[1])&&(!(B[1]))))||((!(A[3]^B[3]))&&((!
(A[2]^B[2])))&&((!(A[1]^B[1])))&&((A[0])&&(!(B[0]))));
assign menor = (!A[3]&&B[3])||((!(A[3]^B[3]))&&(!A[2])&&B[2])||(!(A[3]^B[3])&&(!
(A[2]^B[2]))&&(!A[1])&&B[1])||((!(A[3]^B[3]))&&(!(A[2]^B[2]))&&(!(A[1]^B[1]))&&(!
A[0])&&B[0]);

assign salida_igual = (igual == 1'b1)? 8'b00010010: 8'b00000000;

assign salida_num = (mayor == 1'b1)? a :
(menor == 1'b1)? b :
3'b000;
assign iguales = igual;

endmodule

module bit_concatenator(A, B, out);

input [2:0] A, B;
output [6:0] out;

assign out[5:0] = {A,B};

assign out[6] = ({A,B}==6'b000000)?1'b0:
({A,B}==6'b000011)?1'b0:
({A,B}==6'b000101)?1'b0:
({A,B}==6'b000110)?1'b0:
({A,B}==6'b001001)?1'b0:
({A,B}==6'b001100)?1'b0:
({A,B}==6'b001111)?1'b0:
({A,B}==6'b010001)?1'b0:
({A,B}==6'b010010)?1'b0:
({A,B}==6'b010100)?1'b0:
({A,B}==6'b010111)?1'b0:
({A,B}==6'b011000)?1'b0:
({A,B}==6'b011011)?1'b0:
({A,B}==6'b011101)?1'b0:
({A,B}==6'b100001)?1'b0:
({A,B}==6'b100001)?1'b0:
({A,B}==6'b100010)?1'b0:
({A,B}==6'b100100)?1'b0:
({A,B}==6'b100111)?1'b0:
({A,B}==6'b101000)?1'b0:
({A,B}==6'b101011)?1'b0:
({A,B}==6'b101110)?1'b0:
({A,B}==6'b110000)?1'b0:
({A,B}==6'b110011)?1'b0:
({A,B}==6'b110101)?1'b0:
({A,B}==6'b110110)?1'b0:
({A,B}==6'b111001)?1'b0:
({A,B}==6'b111010)?1'b0:
({A,B}==6'b111100)?1'b0:
({A,B}==6'b111111)?1'b0:
1'b1;
endmodule

module ALU(input_one, input_two, selector, seven_seg, lol);

input [2:0] input_one, input_two;

input [1:0] selector;
output [7:0] seven_seg;
output lol;
assign lol = 1'b0;

wire [6:0] out;

wire [2:0] s, s_s, num;
wire carry, flag;
wire [7:0] segment_one, segment_two, segment_three, segment_four, no_segment_one,
no_segment_two, no_segment_three, no_segment_four;
wire [7:0] igual;
wire [7:0] seven_seven, no_seven_seven;

three_bit_adder ad(.a(input_one), .b(input_two), .s(s), .cout(carry));

BCD_to_seven_seg
seg_one(.BCD(s), .sign(1'b1), .seven_seg(segment_one), .no_seven_seg(no_segment_one
));

three_bit_substracter sub(.a(input_one), .b(input_two), .s(s_s), .sign(signo));

BCD_to_seven_seg
seg_two(.BCD(s_s), .sign(signo), .seven_seg(segment_two), .no_seven_seg(no_segment_
two));

bit_concatenator conc(.A(input_one), .B(input_two), .out(out));

BCD_to_seven_seg
seg_three(.BCD({2'b00,out[6]}), .sign(1'b1), .seven_seg(segment_three), .no_seven_s
eg(no_segment_three));

mag_comparator
comp(.a(input_one), .b(input_two), .iguales(flag), .salida_igual(igual), .salida_nu
m(num));
BCD_to_seven_seg
seg_four(.BCD(num), .sign(1'b1), .seven_seg(seven_seven), .no_seven_seg(no_seven_se
ven));

assign segment_four = (flag == 1'b1) ? igual: seven_seven;

assign no_segment_four[0] = !segment_four[0];
assign no_segment_four[1] = !segment_four[1];
assign no_segment_four[2] = !segment_four[2];
assign no_segment_four[3] = !segment_four[3];
assign no_segment_four[4] = !segment_four[4];
assign no_segment_four[5] = !segment_four[5];
assign no_segment_four[6] = !segment_four[6];
assign no_segment_four[7] = !segment_four[7];

assign seven_seg = (selector==2'b00)? no_segment_one:

(selector==2'b01)? no_segment_two:
(selector==2'b10)? no_segment_three:
no_segment_four;

endmodule