Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

Design, Simulation, and Analysis of a Digital

Electro-optic SR NOR Latch
Law Foo Kui*, M. Rakib Uddin**, Nur Musyiirah and Nurazmina Lingas
Electrical and Electronic Engineering Programme Area
Faculty of Engineering
Universiti Teknologi Brunei (UTB)
Gadong, Brunei Darussalam
Email: *P20171002@student.utb.edu.bn, **rakib.uddin@utb.edu.bn

Abstract—This paper presents the novel design, simulation,
and analysis of a digital electro-optic SR NOR latch utilizing
the silicon micro-ring resonator. This work details the design
principle of the proposed SR NOR latch, demonstrates and
analyze the operation with the operating speed of 15 Gbps.
Clear output timing diagrams, as well as eye diagrams, show
the operation performance of the proposed circuit design.
Keywords— micro-ring resonator; electronic circuit design;
optical signals
I. INTRODUCTION
The advancement of the recent electronic circuit
nowadays is thanks to the sequential logic circuits
implemented to it. Both sequential logic, as well as
combinational logic together, form almost all of the practical
digital devices [1]. Digital flip-flops are among some of the
elements that are considered sequential logic, where it mostly
used as storage elements essentially used in digital memory
storage circuits [2, 3].
Flip-flops and latches are the common electronic circuits
that are implemented in every circuit boards and devices.
Due to its wide variety of usage and implementation,
improvements in terms of its operational performance as well
as its efficiency have become the research target till this day,
as we have seen methods to minimize the clock power for
high performance latches [4], a comparative analysis of the
impact of process and runtime variations on the digital flip-
flop performances [5], and also the evaluation of symmetric
and asymmetric gate-workfunction FinFET’s head to head in
order to design digital logic gates and flip-flops in high-
performance process [6].
SR type flip-flops and latches are one of the building
blocks amongst all the flip-flops available, as it is the
foundation towards designing all other sequential logic
circuits such as D flip-flops, T flip-flops, and JK flip-flops.
We have seen the realization of all-optical SR latches and
flip-flops based on active interferometric devices [7], and
also the manipulation of the dynamics in a nonlinear Fabry-
Perot interferometer with Kerr materials [8]. We have also
seen the derivation of optical SR latches, differential logic
gates, and modulators based on the electro-optic devices [9].
In terms of electro-optic devices and photonic circuits,
we have observed the research development of photonic
logic gates based on silicon micro-ring resonator such as the
demonstration of exclusive OR and NOR gates using two
cascaded micro-ring resonators [10], demonstration of
electro-optic logic gates based on a single micro-ring
resonator [11], and a theoretical model of two high-
throughput optical logic using voltage induced free-carrier
dispersion for CMOS logic operation [12]. We hope that by
utilizing the current photonic devices such as silicon micro-
ring resonator, we can implement our proposed design into
the construction of a digital electro-optic SR NOR latch with
micro-ring resonator as its base component.
This paper details the principal design of a digital electro-
optic SR NOR latch with a carrier injection electro-optic
modulation-based silicon micro-ring resonator as the
switching device, as well as provide the proposed design
time-varying simulation test for the performance analysis
with an operating data rate of 15 Gbps.
II. PRINCIPAL DESIGN OF SR NOR LATCH
SR NOR latch operates by utilizing two digital NOR
gates for its logical operation, which is demonstrated by Fig.
1, and its truth table logical operation is as shown in Table 1
[13]. Our proposed circuit design concept is to replace the
two digital logic gates shown in Fig. 1 into two photonic
devices, capable of operating at NOR mode as demonstrated
previously in our works [11], thus theoretically creating our
proposed design of electro-optic logic SR NOR latch.
The first part of our work is to design a suitable ring
waveguide in order for the electro-optic modulation effect to
take place properly. With this, we choose the PIN diode ring
waveguide build due to its effectiveness in causing the
nonlinear resonance wavelength shift when exposed to a
linear electrical voltage source. The ring waveguide cross
section is as shown in Fig. 2.
Fig. 1. Generic SR NOR latch circuit design.
TABLE I. SR NOR LATCH TRUTH TABLE.
Set Input Reset Input Q Inv(Q) State
0 0 - - No Change
0 1 0 1 Set Latch
1 0 1 0 Reset Latch
1 1 - - Invalid

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

Fig. 2. Cross-section of the silicon PIN waveguide.

The buried oxide SiO2, has the thickness of 1 µm, with

the silicon-based PIN waveguide sit on top of it. The core Fig. 4. Resonance spectra of the drop port at different logical inputs.
waveguide has the dimension of 400 nm in width and 220
nm in height. It is placed in the middle of the thinner
waveguide, forming the rib waveguide with a slab thickness
of 50 nm. The intrinsic region is approximated at 200 nm for
carrier injection operation during the resonance modulation
phase. The doping concentrations are indicated by the
colored regions in Fig. 2. The dosage for both p and n doping
regions are set to be 1  1018 cm-2, and p+ and n+ regions are
approximated at 5  1017 cm-2 and 2.5  1017 cm-2
respectively. The rib is attached an aluminum electrical
contacts for electro-optic modulation to occur at the ring
waveguide, and the entire ring resonator is finally layered by
Fig. 5. Schematic setup for the digital electro-optic SR NOR latch.
the surface oxide SiO2 of 1 µm in thickness as the separate
layer.
In order to determine the modulation voltage required for
Once we have designed the PIN waveguide structure and each of the inputs being fed into the ring, we run resonance
electro-optic modulation, we set up the micro-ring using the spectra simulations consisting of modulation inputs of three
ring waveguide designed as shown in Fig. 3. The micro-ring conditions, when both of them is at logic state ‘0’ (A=0,
resonator general properties are as shown in Table 2. Two B=0), when one of them is at logic state ‘1’ (A=0, B=1 or
electrical inputs act as operand are being fed into the ring A=1, B=0) and when both of the inputs are at logic state ‘1’
waveguide, and depending on the electrical signal voltage (A=1, B=1). The result is as shown in Fig. 4.
level, the nonlinear resonance is shifted accordingly to output
The results shown in Fig. 4 shows clear change in optical
an optical power level.
power level (from logic state ‘1’ to logic state ‘0’) at the drop
We have carried out the resonance response simulation of port when any of the input ports are experiencing the change
the silicon-based micro-ring resonator [14], and that based on in logic states, thus confirming that the micro-ring resonator
our findings, the designed micro-ring resonator is effectively is currently operating as a NOR gate at the operating
operating as a digital logic NOR gate when it is operating at wavelength of 1548 nm.
a single wavelength of 1548 nm when we apply the specific
Once we have obtained all the required properties for the
voltage.
micro-ring resonator to operate as NOR mode, we replace
the two NOR gates in Fig. 1 into two micro-ring resonators
(MRR1 and MRR2) to complete our proposed design as
shown in Fig. 5.
SR NOR latch design differs to that of SR NAND latch
in a way that the inputs are now at different locations, thus
Reset input is on MRR1 in Fig. 5 which corresponds to NOR
1 in Fig. 1. Set input, on the other hand, is fed into NOR 2 in
Fig. 1, while it is being fed into MRR2 in Fig. 5.

Fig. 3. Schematic setup of a single micro-ring resonator operating as a

Set input is active when it is exposed to the electrical
digital logic NOR gate. voltage 1.2V (logic state ‘1’) while Reset input is exposed to
0V (logic state ‘0’). Reset input is active when it receives an
electrical voltage of 1.2V (logic state ‘1’), while Set input is
TABLE II. MICRO-RING RESONATOR PROPERTIES being fed to electrical voltage 0V (logic state ‘0’).
Parameters Values When the Reset input is active, MRR1 outputs a digital
Ring Length 60 µm logic state ‘0’ to the Q output port, abandoning the logic state
Coupling Gap 200 nm Inv(Q) is in. After going through the photodetector, this logic
Effective Index Coefficient 2.56
state ‘0’ reaches MRR2, forcing it to generate a digital logic
Group Index Coefficient 4.41
state of ‘1’. When the Set electrical input is triggered with Q

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

output is currently at logic state ‘1’, MRR2 generates the B. Simulation Result and Discussion
digital logic ‘0’, which is then looped into MRR1, forcing it
to change its output logic state to ‘1’, finishing the Set
condition operation. This concludes that the complete cycle
described resembles to that of SR NOR latch operation, thus
indicating the successful circuit design, with its operation is
in accordance described in Table 1.

III. SIMULATION AND ANALYSIS

A. Simulation Setup
We simulate the circuit in one of the most reputable
simulation software for the design and analysis of photonic
integrated circuits, namely Lumerical INTERCONNECT
Simulation software. Continuous light (CW) light source
generating a single wavelength of 1548 nm, with the optical
power of 5 dBm, is being fed into the two micro-ring
resonators as its input light source as shown in Fig. 5. The
photodetectors used inside the proposed design shown in the
mentioned figure is Avalanche Photodiode photodetector
(APD). The reason in choosing this photodetector than the
generic PIN photodetector is to utilize its multiplication
factor that existed in APD, thus strengthening the small dBm
optical signal from the output ports of micro-ring resonators
into readable and applicable electrical signals for logic
operation processing.
The entire setup for the time-varying simulation,
however, is as shown in Fig. 6. The designed circuit from
Fig. 5 is now being tested as the setup shown in Fig. 6, with
predetermined input bit stream of amplitudes 1.2V and rise Fig. 7. Timing waveform generated for the proposed SR NOR latch.
and fall time of 0.05 ns each, generic PIN photodetectors and
a multi-channel electrical oscilloscope. The two PIN Fig. 7 shows the timing waveforms obtained from the
photodetectors used in the setup is operating in such a way oscilloscope in Fig. 6 at the time window of 0.5 ns. Based on
that it converts every 1 dBm of the optical signal into a 1V the timing waveform, as we set the Reset input into logic
electrical signal, which is finally being fed into the state ‘1’ (voltage of 1.2V), the Q port outputs a digital logic
oscilloscope for waveform analysis. state ‘0’ as well (voltage of 0V) and Inv(Q) outputs the
reverse, digital logic state ‘1’ (voltage of 5V). When both
The simulation is being carried out in the time frame of
inputs are at logic state ‘0’ (voltage of 0V), we observe a no
0.5 ns at the data rate of 15 Gbps. The sample rate used by
change in the outputs for both ports. When the Set input is at
the oscilloscope to obtain the time waveform result is 30
logic state ‘1’, Q changes its logic state from ‘0’ to ‘1’, while
THz, with the entire circuit is operated at the constant
Inv(Q) changes its logic state as well, from logic ‘1’ to ‘0’.
temperature of 300 K.
This clearly shows that the proposed design is capable of
operating as SR NOR latch at the data rate speed of 15 Gbps,
following the truth table detailed in Table 1.

Fig. 6. Time-varying simulation setup.

Fig. 8. Eye diagram for the proposed design.

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 Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference (Jeju, Korea, 28-31 October 2018)

Fig. 8 shows the clear eye diagram obtained from the
analysis of the Q output port. The time window for this is 20
ns at the sampling rate of 3 THz. We have also obtained
several results based on the analysis, such as the extinction
ratio is calculated as 20.28 dB, the rise time is found to be
40.369 ps and fall time is 13.293 ps. Both Q and Inv(Q)
signals are measured at the amplitude of 5V at the maximum
point, and the input is measured as 1.2V at both Set and
Reset inputs. There is a slight delay response time between
the inputs and the outputs, which is measured from the
graphs in Fig. 7 to be 53.3 ps.
stimulated Raman scattering," in Proc. of SPIE Vol, 2017, pp.
101080Q-1.
[13] T. Ndjountche, Digital Electronics 2: Sequential and Arithmetic
Logic Circuits, Volume 2, 1st ed. Hoboken, New Jersey: John Wiley
& Sons, Inc., 2016, pp. 12-15.
[14] L. F. Kui and M. R. Uddin, "Photonic microring resonator modulated
resonance response analysis," Optical and Quantum Electronics, vol.
49, p. 275, 2017.

IV. CONCLUSION
We have presented the design, simulation, and analysis of
the digital electro-optic SR NOR latch, where silicon micro-
ring resonator is used as the base component. We have
shown that nonlinear carrier-injection electro-optic
modulation effect embedded in the micro-ring resonator is
capable of digital logic circuit operation, such as the
proposed circuit design. We have replaced the two NAND
gates in the circuit diagram of the SR NOR latch into two
micro-ring resonators, each operating as NOR mode.
Simulation result shows clear timing diagrams for both Q
and Inv(Q) outputs, with its maximum amplitude reaching
the 5V threshold at the data rate of 15 Gbps and sampling
rate of 30 THz, with eye diagrams shows good eye-opening
when the proposed design is subjected operation time
window of 20 ns and sampling rate of 3 THz.

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