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Lm224 - Onsemiconductor ĐK Quat Dan L NH TL
Lm224 - Onsemiconductor ĐK Quat Dan L NH TL
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ESD RATINGS
Rating HBM MM Unit
ESD Protection at any Pin (Human Body Model − HBM, Machine Model − MM)
NCV2902 (Note 3) 2000 200 V
LM324E, LM2902E 2000 200 V
LM324DG/DR2G, LM2902DG/DR2G 200 100 V
All Other Devices 2000 200 V
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)
LM224 LM324A LM324, LM324E LM2902, LM2902E LM2902V/NCV2902
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Input Bias Current IIB − −90 −150 − −45 −100 − −90 −250 − −90 −250 − −90 −250 nA
TA = Thigh to Tlow − − −300 − − −200 − − −500 − − −500 − − −500
(Note 4)
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)
LM224 LM324A LM324, LM324E LM2902, LM2902E LM2902V/NCV2902
Characteristics Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
Bias Circuitry
Common to Four
Output Amplifiers
VCC
Q15
Q16 Q14 Q22
Q13
40 k
Q19
Q18 Q20
Inputs
Q11
Q9
- Q17 Q21
Q6 Q7 Q25
Q2 Q5 Q1 2.4 k
Q8 Q10
Q3 Q4 Q26
2.0 k
VEE/GND
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
CIRCUIT DESCRIPTION
1.0 V/DIV
stage performs not only the first stage gain function but also
performs the level shifting and transconductance reduction
functions. By reducing the transconductance, a smaller
compensation capacitor (only 5.0 pF) can be employed, thus
saving chip area. The transconductance reduction is
accomplished by splitting the collectors of Q20 and Q18. 5.0 s/DIV
Another feature of this input stage is that the input common
Figure 2. Large Signal Voltage Follower Response
mode range can include the negative supply or ground, in
single supply operation, without saturating either the input Each amplifier is biased from an internal−voltage
devices or the differential to single−ended converter. The regulator which has a low temperature coefficient thus
second stage consists of a standard current source load giving each amplifier good temperature characteristics as
amplifier stage. well as excellent power supply rejection.
70 70
60 60
Phase Margin
PHASE MARGIN (°)
GAIN MARGIN (dB)
50 50
40 40
30 30
20 Gain Margin 20
10 10
0 0
1.0 10 100 1000 10000
LOAD CAPACITANCE (pF)
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
20 120
18
16 VEE = GND
A VOL, LARGE-SIGNAL
14 TA = 25°C
80
12
60
10
Negative
8.0 40
Positive
I
6.0 20
4.0
0
2.0
0 -20
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 1.0 10 100 1.0 k 10 k 100 k 1.0 M
± VCC/VEE, POWER SUPPLY VOLTAGES (V) f, FREQUENCY (Hz)
Figure 5. Input Voltage Range Figure 6. Open Loop Frequency
14 550
VOR , OUTPUT VOLTAGE RANGE (V pp )
RL = 2.0 k 500
12
VCC = 15 V VO , OUTPUT VOLTAGE (mV) Input
VEE = GND 450
10 Gain = -100
Output
RI = 1.0 k 400
8.0 RF = 100 k
350
6.0
300
4.0 250 VCC = 30 V
VEE = GND
2.0 200 TA = 25°C
CL = 50 pF
0 0
1.0 10 100 1000 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
f, FREQUENCY (kHz) t, TIME (s)
2.4
2.1 TA = 25°C
I CC , POWER SUPPLY CURRENT (mA)
RL = R 90
I IB , INPUT BIAS CURRENT (nA)
1.8
1.5
1.2
0.9 80
0.6
0.3
0 70
0 5.0 10 15 20 25 30 35 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, POWER SUPPLY VOLTAGE (V) VCC, POWER SUPPLY VOLTAGE (V)
Figure 9. Power Supply Current versus Figure 10. Input Bias Current versus
Power Supply Voltage Power Supply Voltage
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
50 k
R1
5.0 k
VCC 10 k VCC
VCC R2 -
- Vref
1/4
1/4 LM324 VO
LM324 VO
+ 1
MC1403 + fo = 2 RC
2.5 V 1
Vref = V
2 CC
For: fo = 1.0 kHz
R R = 16 k
C
R1 R C C = 0.01 F
VO = 2.5 V 1 +
R2
1 R2
+
e1
1/4 CR R Hysteresis
LM324
VOH
-
R1 VO
Vref +
- 1/4
a R1 1/4 LM324
R1 LM324 eo VO
Vin -
+ VOL
VinL VinH
b R1
- 1 R1 Vref
CR VinL = (VOL - Vref) + Vref
1/4 R1 + R2
LM324
+ R1
e2 R VinH = (VOH - Vref) + Vref
R1 + R2
R1
H= (VOH - VOL)
eo = C (1 + a + b) (e2 - e1) R1 + R2
Figure 13. High Impedance Differential Amplifier Figure 14. Comparator with Hysteresis
R
1
fo =2 RC
R 100 k
R1 = QR
1
Vin C1 R2 R1 Vref = V
C C R2 = 2 CC
- R TBP
1/4
LM324 - 100 k
1/4 - R3 = TN R2
+ LM324 1/4
+ LM324 C1 = 10C
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
1 Triangle Wave
Vref = V R2
2 CC Output
300 k
Vref +
1/4 R3 VCC
+
LM324 1/4 R3
- 75 k C
R1 LM324 R1 C
- Square - CO
100 k Vin
Wave 1/4
Vref Output LM324 VO
C
+ CO = 10 C
Rf R2
R1 + RC R2 R1 Vref 1
f = if R3 = Vref = 2 VCC
4 CRf R1 R2 + R1
Figure 16. Function Generator Figure 17. Multiple Feedback Bandpass Filter
Given:fo=center frequency
A(fo)=gain at center frequency
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
ORDERING INFORMATION
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LM324, LM324A, LM324E, LM224, LM2902, LM2902E, LM2902V, NCV2902
MARKING DIAGRAMS
PDIP−14
N SUFFIX
CASE 646
14 14 14 14
1 1 1 1
SOIC−14
D SUFFIX
CASE 751A
14 14 14 14
LM324ADG LMx24DG LM2902DG LM2902VDG *
AWLYWW AWLYWW AWLYWW AWLYWW
1 1 1 1
14 14
LMx24EG LM2902EG
AWLYWW AWLYWW
1 1
TSSOP−14
DTB SUFFIX
CASE 948G
14 14 14 14
1 1 1 1
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*This marking diagram also applies to NCV2902.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
1
SCALE 1:1 NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D A 2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
14 8 E AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
H 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
1 7 LEADS UNCONSTRAINED.
c
NOTE 8 b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
NOTE 5 CORNERS).
A2
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
NOTE 3
A −−−− 0.210 −−− 5.33
L A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.35 0.56
SEATING
PLANE b2 0.060 TYP 1.52 TYP
A1 C 0.008 0.014 0.20 0.36
C M D 0.735 0.775 18.67 19.69
D1 D1 0.005 −−−− 0.13 −−−
e eB E 0.300 0.325 7.62 8.26
END VIEW E1 0.240 0.280 6.10 7.11
14X b
e 0.100 BSC 2.54 BSC
NOTE 6
0.010 M C A M B M eB −−−− 0.430 −−− 10.92
SIDE VIEW L 0.115 0.150 2.92 3.81
M −−−− 10 ° −−− 10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2 1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE
GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
TSSOP−14 WB
CASE 948G
14 ISSUE C
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF NOTES:
1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1
ÉÉÉ
ÇÇÇ
−V− DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT XXXX
XXXX
7.06
ALYWG
G
1 1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
0.65 G = Pb−Free Package
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X device data sheet for actual part marking.
14X
0.36 Pb−Free indicator, “G” or microdot “ G”,
1.26 may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASH70246A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.