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Nios An184 Avalon Multimaster
Nios An184 Avalon Multimaster
Nios An184 Avalon Multimaster
Once the master has control of the bus, the master sends information to
the appropriate slave. Figure 1 on page 2 illustrates the priority bus
architecture in a traditional processor system.
Altera Corporation 1
AN-184-1.1
AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Master 1 Master 2
Masters DMA
System CPU
Controller
Arbitrator
Bottleneck
System Bus
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Because master and slave peripherals are connected with dedicated paths,
multiple masters can be active at the same time and can simultaneously
transfer data to their slaves. This simultaneous multi-master architecture
offers great throughput performance advantages compared to a
traditional, shared bus architecture. Master peripherals do not have to
wait to access a target slave peripheral, as long as another master does not
access the same slave at the same time. Unlike a shared bus, a
simultaneous multi-master architecture with two masters offers up to
twice the throughput; with three masters, it offers up to three times the
throughput. The throughput improvement depends on how often all
three masters are active simultaneously.
Term Definition
Avalon Bus Module The collection of Avalon bus interconnects, multiplexers, and arbitrator logic used to
implement a system using the simultaneous multi-master Avalon bus. The SOPC Builder
creates the Avalon bus module and its contents automatically based on the designer’s
system.
Master Peripheral Sometimes abbreviated as “master.” A master peripheral can initiate bus transfers on the
Avalon bus and must have at least one master port that connects to the Avalon bus module.
A master peripheral may also have a slave port. For example, the DMA peripheral has two
master ports to perform simultaneous reads and writes between peripherals and a slave
port. The slave port accepts commands from a Nios processor to set up the DMA transfer.
Slave Peripheral Sometimes abbreviated as “slave.” A slave peripheral only accepts bus transfers from the
Avalon bus and cannot initiate bus transfers. Slave peripherals usually have only one slave
port that connects to the Avalon bus module.
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Term Definition
Master Port The collection of master peripheral signals used to initiate transfers on the Avalon bus.
Master ports present address and control signals to initiate read and write transfers from a
slave.
Slave Port The collection of peripheral signals used to accept Avalon bus transfers from another
peripheral’s master port. Slave ports accept the address and control signals presented by
a master port, allowing them to be read from or written to.
Master-Slave Pair The combination of a master port and a slave port that are connected via the Avalon bus.
Structurally, these master and slave ports connect to their respective ports on the Avalon
bus module. The master port’s control and data signals pass through the Avalon bus
module and interact with the slave port. You can specify connections between master and
slave ports (i.e., master-slave pairs) in the SOPC Builder.
Arbitrator A logic block inside the Avalon bus module that associates each slave port that is controlled
by multiple masters. When multiple masters request transfers to the same slave, the
arbitrator selects which master gains access to the slave. A single arbitrator controls access
to only one slave port. When several multi-master slaves exist, each slave has an
independent arbitrator.
Control Signals Signals that control the direction, sequence, and timing of a data transfer between a master
and slave port. These signals may vary depending on the implementation of the peripheral.
Control signals from a master port typically include read enable and write enable signals.
Control signals from a slave port typically include wait request and interrupt request (IRQ)
signals.
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Master 1 Master 2
Masters DMA
System CPU
Controller
Arbitrator
Note:
(1) All arrows represent address, data, and control signals.
Figure 3 provides additional detail of the data, address, and control paths
of the system in Figure 2. From the master to the slave, the arbitrator logic
multiplexes all address, data, and control signals from a master port to a
shared slave port. From the slave to the master, the slave’s data and
control signals can be multiplexed into the master so that the master port
receives the target slave’s signals at the appropriate time.
M1 Address Arbitrator
Master 2
DMA
Controller
Slave Read Data
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Slave Arbitrator
The Avalon bus module contains one slave arbitrator for each shared
slave port. You can parameterize each slave arbitrator individually in the
SOPC Builder. A slave arbitrator performs the following functions for its
associated slave port:
■ Defines control, address, and data paths from multiple master ports
to the slave port and specifies the arbitration mechanism to use when
multiple masters contend for the slave at the same time.
■ At any given time, selects which master port has access to the slave
port and forces all other contending masters (if any) to wait, based on
arbitration assignments.
■ Controls the slave port, based on the address, data, and control
signals presented by the currently selected master port.
The slave arbitrator matches the appropriate data bus, address bus, and
control signals from a master to a slave. The arbitrator selects between
multiple master ports based on the arbitration assignments you make in
the SOPC Builder. The master request slave signal (MRS), presented by
the request logic, indicates a request for access to a slave. If multiple
masters generate requests for bus transactions to a slave, the winning
master accesses the slave and the slave arbitrator generates a wait signal
for the losing master(s). See “Bus Timing” on page 9 for an example multi-
master bus transfer.
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
MRS Request
Logic MSG Arbitrator
Logic
Multiplexer
Multiplexer
MRS Request
Logic MSG Arbitrator
Logic
Multiplexer
S2 Read Data & Control Multiplexer
The arbitrator and request blocks generate control signals that are fed to
multiplexers on the master and slave ports. See Table 2.
Signal Function
Master Request Slave Multiplexer control that connects the wait and data signals
(MRS) from multiple slave ports to a single master port.
Master Select Multiplexer control that connects the data and control
Granted (MSG) signals from multiple master ports to a single slave port.
Wait Input to each master port that indicates that the bus
transfer should be held when the desired slave port cannot
be accessed immediately.
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
In more complex cases, Avalon peripherals can have more than one port
and may have both a master and slave port, e.g., the Nios processor or
DMA peripheral. The Nios processor has two master ports—separate
interfaces for instruction and data memory—and no slave ports. The
DMA peripheral has two master ports and a slave port. The slave port
accepts commands from a Nios processor to set up the DMA transfer and
the master ports initiate bus transfers with the source and destination
peripherals.
Because the Avalon bus module handles the arbitration details, special
considerations are not necessary when designing a peripheral to function
in a simultaneous multi-master Avalon bus system. However, the
peripheral master and slave ports must follow the rules of the Avalon bus
specification. For example, master peripherals must accept the
waitrequest signal because the arbitration logic may force the master
port to wait. A slave peripheral accepts bus transfers from the Avalon bus
module and is not aware of the multiple master ports that access it. The
slave only sees a sequence of bus transfers presented by the arbitration
logic.
Designers who want to build custom Nios peripherals can view the
system’s Peripheral Template File (.ptf) to see each peripheral’s master
and slave ports.
Arbitration Schemes
The Avalon arbitrator logic uses a fairness-based arbitration scheme,
sometimes referred to as a round-robin or weighted round-robin scheme.
For any given connection between a master and slave, you can select how
much access each master has to a given slave. You use the SOPC Builder
to make arbitration assignments to a specific master-slave pair.
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
Bus Timing
Simultaneous multi-master transfer timing is the same as that of other
Avalon transfers. While the Avalon interface specification rules hold true
for individual bus transfers, you can observe the arbitration settings of
each master and the control signals each master transmits to understand
the workings of multiple transfers to a shared slave.
Just after the next rising edge of the clock, the transfer between M1 and S1
completes and the MRS signal from the M1 request logic to the S1
arbitrator is negated, as is the wait signal to M2. The next transfer, which
is between M2 and S1, can complete.
clk
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AN 184: Simultaneous Multi-Mastering with the Avalon Bus
You do not need to make special settings for these transfers to take place
correctly. All transfers, including those shown above and those that are
more complex, execute according to the Avalon bus specification.
Additionally, other transfers (such as between another master and slave)
execute transparently through separate control and data lines.
Documentation Altera values your feedback. If you would like to provide feedback on this
document—e.g., clarification requests, inaccuracies, or inconsistencies—
Feedback send e-mail to nios_docs@altera.com.
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