Received April 2, 2018, accepted May 1, 2018, date of publication May 15, 2018, date of current version June

29, 2018.
Digital Object Identifier 10.1109/ACCESS.2018.2836858

INVITED PAPER

Dynamic Partial Reconfiguration of Concurrent

Control Systems Specified by Petri Nets and
Implemented in Xilinx FPGA Devices
REMIGIUSZ WIŚNIEWSKI , (Member, IEEE)
Institute of Electrical Engineering, University of Zielona Góra, 65-417 Zielona Gora, Poland
Corresponding author: r.wisniewski@iee.uz.zgora.pl

ABSTRACT This paper proposes a novel design concept of concurrent control systems specified by
interpreted Petri nets and implemented in Xilinx FPGA devices. The technique is oriented on further dynamic
partial reconfiguration of the system. An adequate splitting algorithm of the system into the dynamic
(reconfigurable) and static (non-reconfigurable) partitions is proposed. The main advantage of the presented
idea is the possibility of the dynamic reconfiguration of the already implemented system. It means that the
functionality of the selected component (module) of the controller can be changed, while the rest of the
system is still running. The presented technique is illustrated by a real-life case-study example, and it has
been verified experimentally with the application of Xilinx FPGA device.

INDEX TERMS Dynamic partial reconfiguration, FPGA, concurrent controllers, Petri nets, decomposition.

I. INTRODUCTION
The idea of dynamic partial reconfiguration of the Field Pro-
grammable Gate Arrays (FPGAs) is becoming very popular
nowadays [1]–[7]. This technique allows replacement of a
part of the already implemented system without the stopping
of the device [1], [2]. In other words, the functionality of the
selected components of the system can be modified while
the rest of the controller is still working. It is especially
applicable in the case of concurrent controllers executing
crucial operations that cannot be interrupted. Thus, despite
the primary under-exploitation in the industrial control
systems [8], the dynamic partial reconfiguration can be
found in the field of wireless telecommunication systems [1],
virtualized hardware cloud accelerators [3], automotive
industry [4], medicine [5], aero-space [6], or even
cryptology [9], [10]. Particularly, let us recall the Australian
FedSat satellite [6], where dynamic partial reconfiguration
was used in order to redefine the particular subsystems
without stopping of the device. Another interesting example
is described in [9], where the reconfigurable hardware crypto-
processor oriented for solving security tasks is presented.
A. PARTIAL RECONFIGURATION OF
CONCURRENT CONTROLLERS
Although the guidelines for the dynamic partial reconfigura-
tion of Xilinx FPGAs (which we shall follow in the paper)
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are clear and well written [7], they cannot be directly applied
to the universal prototyping method for the concurrent logic
controllers. Such systems are able to execute multiple oper-
ations at the same time [2], [11]. Therefore, an adequate
design flow ought to be applied, strictly dedicated to such
controllers [2].
Another important problem that has to be solved by the
designer concerns the proper selection of a reconfigurable
partition of the system. Such a partition should be selected
carefully, since it can be reconfigured only if it is not per-
forming any action. Moreover, the designer must pay atten-
tion to those operations of the controller that are executed
concurrently with the reconfigurable part, in order to avoid
malfunctions in the system.
The above restrictions make prototyping of concurrent
controllers oriented for further dynamic partial reconfigura-
tion especially hard to handle. Let us now briefly summarize
the most popular design techniques of such systems.
The prototyping method for dynamically reconfigurable
embedded microprocessors is presented in [12]. The idea
is based on Unified Modelling Language (UML), which is
used to create a specification of the system. Furthermore,
the technique employs the dedicated Xilinx tool (particularly
Xilinx Embedded Development Kit, EDK) for automatic
transformation of the controller into hardware description
languages (HDLs) code. Unfortunately, the method is limited
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
to the embedded microprocessors only, and other components
of the system cannot be dynamically reconfigured. A sim-
ilar technique is shown in [13], where Xilinx EDK is used
to automate the generation of the HDL codes. However,
the method additionally uses transformations between UML
models (with the use of Gaspard 2 framework) which causes
the serious limitations and restrictions.
The UML language is also used in [14], where the authors
clearly indicate that the lack of the design flows discourage
designers from adopting the reconfigurable computing tech-
nology. The proposed design flow is split into three phases,
namely: design and implementation of the system software
model, hardware synthesis and software synthesis. The inputs
are the C++ code and UML 2.0 diagrams (class, sequence
and state machine diagrams) built with the Rhapsody 5.0 tool.
The general idea of partial reconfiguration of controllers
specified by Petri nets is presented in [15]. The method is
based on the decomposition of the net into state machine
components that are further modeled in hardware descrip-
tion languages. Unfortunately, the description of the recon-
figuration process is very general, giving no details, or
algorithms. Furthermore, the applied reconfiguration method-
ology (difference-based technique) is obsolete and cannot be
applied to today’s FPGAs.
The implementation of a fuzzy logic controller on the
reconfigurable FPGA system is demonstrated in [16]. It pro-
poses the integrated development environment FADIS (Fuzzy
logic controller Automatic Design and Implementation Sys-
tem), which supports the design and implementation phase.
The VHDL (Very High Speed Integrated Circuits Hardware
Description Language) code is automatically generated from
the design specification of the hardware structure. Addition-
ally, FADIS system performs operations such as synthesis,
optimization, placement and routing, generation of the hard-
ware objects, downloading, data transfer and monitoring of
the control action. Thus, the whole prototyping flow strongly
depends on third-party synthesis and implementation tools.
Another interesting approach is proposed in [17], where
Temporal Petri nets are applied as a specification of the logic
controller. The system is split into two parts: fixed logic area
(FLA) and reconfigurable logic area (RLA). The first one
describes the static (non-reconfigurable) components of the
controller and additionally holds the reconfiguration control
(called schedule) sub-system. Although the idea seems to be
promising and interesting, it affects major modification to the
prototyped controller. Furthermore, the designer is required
to have deep knowledge of the system details (such as the
structure of the device or the cycle time of the system) to
handle the configuration process.
Petri nets are also applied in the technique shown in [18].
The presented idea additionally uses hierarchy in the design
process. The control system is split into top-level module
(which is non-reconfigurable) and macroplaces which are
formed from the subnets that describe various versions of
the reconfigurable area. However, additional modifications
to the initial system ought to be made, since the proper
VOLUME 6, 2018
synchronization between the top-level and macroplaces needs
to be assured.
A methodology used to design Petri-net based systems
for implementation in the reconfigurable hardware is also
proposed in [19]. A specification of the system is expressed
by means of dynamic modifiable high-level (DMHL) Petri
nets. The proposed design flow consists of three stages: mod-
eling, analysis/partitioning, and synthesis. The great benefit
of this approach relies on a formal model, which is used in all
design phases. Unfortunately, the proposed method requires
the specific design methodology which is enforced by the
application of DMHL Petri nets.
B. OUR CONTRIBUTION
In the paper we propose a novel design method for concurrent
controllers specified by an interpreted Petri net. The tech-
nique is oriented on the further dynamic partial reconfigura-
tion of the system. The main idea relies on the splitting of the
controller into the dynamic (reconfigurable) and static (non-
reconfigurable) partitions. Such a division can be seen as a
two-stage technique. Firstly, the system is decomposed into
the sequential modules. Next, one of the achieved modules is
once more decomposed, in order to obtain the dynamic part
of the system which can be reconfigured on-the-fly. In other
words, the functionality of this partition can be exchanged
without the stopping of the physical device. The complete
prototyping methodology is presented in the paper. All the
steps required to apply the proposed technique are explained
in detail. Finally, the results of the experimental verification
are shown and discussed.
Let us point out that the presented idea is a signif-
icant enhancement of the previous works published by
authors [2], [20], [22]. In [20] the general prototyping
technique of the concurrent control system specified by an
interpreted Petri net was proposed. However, the partial
reconfiguration aspects were not considered in the paper.
Such concepts were initially presented in [2] and [21], but
both methods have serious restrictions. The idea shown
in [21] is limited to static partial reconfiguration, while the
technique proposed in [2] describes general ideas, without
presenting a formal splitting algorithm, or a complete syn-
chronization of the remaining parts of the system. Finally,
the technique proposed in [22] is restricted to controllers
specified by the UML and it cannot be applied to systems
based on Petri nets, since prototyping flows are totally differ-
ent. Nevertheless, we shall follow the notations introduced
in the above publications (such as reconfigurable region,
dynamic part, static part, etc.) in order to apply them to Petri
net-based reconfigurable systems.
In short, our main contributions can be summarized as
follows:
• A splitting algorithm which divides the concurrent con-
troller into dynamic (reconfigurable) and static (non-
reconfigurable) parts is proposed. The complexity of
the algorithm is estimated, supported by an adequate
proposition and proof.
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 R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems

• An innovative, universal prototyping flow of logic con- Definition 4: A Petri net S = (P0 , T 0 , F 0 , M00 ) is a State
trollers implemented in FPGA devices is shown. The Machine Component (S-component, SMC) of a Petri net N =
presented technique permits further dynamic partial (P, T , F, M0 ), if and only if:
reconfiguration of the already implemented system, and 1) S is an SM-net;
it does not require major changes to the design, nor the 2) S is strongly connected;
0
application of specialized tools. 3) P ⊆ P; n o
• A case study of a real-life concurrent controller is pre- 0 0
4) T = x | x ∈ T , ∃p ∈ P : ((p, x) ∈ F ∨ (x, p) ∈ F) ;
sented. The system was prepared using the proposed  0 0

design flow, and oriented towards further dynamic par- 5) ∀x, y ∈ P ∪ T : ((x, y) ∈ F ⇔ (x, y) ∈ F 0 );
 
tial reconfiguration of the controller.
• The proposed idea has been verified experimentally with
the use of real FPGAs (particularly, with application of
devices from Artix-7, Virtex-5, and Virtex-7 families).
The structure of the paper is organized as follows.
Section II introduces definitions and preliminaries necessary
to understand the presented idea. The main concept of the pro-
posed methodology is shown in Section III, while Section IV
illustrates it by a case-study a real-life example. The results
of experimental research are shown in Section V. Finally,
Section VI summarizes the paper.
II. PRELIMINARIES
Let us introduce notations and definitions necessary to
explain the idea of the proposed technique [2], [20]–[41].
Definition 1: A Petri net is a 4-tuple:
N = (P, T , F, M0 ), (1)
where P is a finite set of places, T is a finite set of transitions,
F ⊆ (P × T ) ∪ (T × P) is a finite set of arcs, M0 is an initial
marking (state) of the net.
Sets of input and output places of a transition are defined
as: • t = {p ∈ P : (p, t) ∈ F}, t • = {p ∈ P : (t, p) ∈ F}; sets of
input and output transitions of a place are denoted as: • p =
{t ∈ T : (t, p) ∈ F}, p • = {t ∈ T : (p, t) ∈ F}.
The state of a net is called marking, which can be seen
as a distribution of tokens in the net places. A marking is
changed by the firing of a transition. A transition can be
fired if each of its input places contains a token. Firing of
a transition removes a token from all its input places and adds
a token to each of its output places. Places and transitions are
called nodes of the Petri net. A net is connected if for any
pair (ni , nj ) of its nodes there is a path leading from ni to
nj or from nj to ni . A net is strongly connected if for any pair
(ni , nj ) of its nodes there is a path leading from ni to nj .
For computation purposes, Petri nets are often described
by an incidence matrix. Let us define it formally.
Definition 2: Incidence matrix of a Petri net N =
(P, T , F, M0 ) with n = |P| places and t = |T | tran-sitions
is an Am×n of integers, given by:

−1, (pi , tj ) ∈ F

aij = 1, (tj , pi ) ∈ F (2)
 tains reusable logic that can be further replaced on-the-fly by
0, otherwise.

Definition 3: A State Machine net (SM-net) is a Petri net
such that each of its transitions has exactly one input place
and exactly one output place, i.e. ∀t ∈ T : |• t| = |t •| = 1.
32378
6) M 0  = 1; M 0 ⊆ M0 .
0 0
Definition 5: State Machine Decomposition (SM-
Decomposition) Of a Petri net N = (P, T , F, M0 ) is a set of S-
components S = {S1 , . . . , Sn }, such that each place pi ∈ P is
a place of exactly one component Sj ∈ S. If place pi ∈ P exists
in more than one S ∈ S, it is replaced by a non-operational
place (NOP) in all S ∈ S, except one [2].
Definition 6: A place invariant (p-invariant): of a Petri
net N is a vector Ey of non-negative integers that solves the
equation:
Ey · AT = 0, (3)
where Ey 6 = 0 and A is an incidence matrix of a Petri net.
Each value (entry) of Ey corresponds to a place of the net. The
set of places that refers to non-zero values of the p-invariant
is called its support and is denoted by I . The p-invariant is
minimal if its support does not contain a support of any other
p-invariant.
Definition 6: A Petri net is live if for every reachable
marking M any transition t can be fired at this marking or in
a reachable marking from M .
Definition 7: A Petri net is safe if there is no marking such
that any place contains more than one token.
Definition 8: An interpreted Petri net is a live and safe Petri
net, defined as a 6-tuple:
PN = (P, T , F, M0 , X , Y ), (4)
where X is a finite set of logic inputs, Y is a finite set of logic
outputs.
Interpreted Petri nets are often used to describe real-life
systems, such as concurrent controllers [21]. The system
communicates with the environment via input and output sig-
nals. The inputs are associated with transitions, while outputs
are bounded to the places of the net. A transition can be fired
if each of its input places contains a token, and the conditions
of all of its input signals are fulfilled.
III. THE IDEA OF THE PROPOSED TECHNIQUE
The proposed design methodology involves several steps.
The principle one relies on the adequate splitting of the
controller into two parts. The first of these (dynamic) con-
different versions. The second part is the static one, that is,
non-reconfigurable. For better understanding of the presented
method, let us start with the description of the complete
prototyping flow of concurrent control systems oriented for
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
further dynamic reconfiguration. The design methodology is
divided into three main stages that include seven steps:
Stage I: Prototyping of the initial version of the system:
1) Specification of the concurrent control system by the
interpreted Petri net.
2) Splitting of the system into dynamic and static parts:
a) SM-decomposition of the controller into state
machine components (sequential automata).
b) Selection of the reconfigurable region (one of the
decomposed automaton) of the controller.
c) Splitting of the reconfigurable region into the
dynamic and static modules.
d) Supplementation of all remaining components by
the reconfiguration request signal.
e) Formation of the dynamic andstatic parts.
3) Description of the controller in the hardware descrip-
tion languages (HDLs), synthesis and logic implemen-
tation of the first version of the system.
4) Physical implementation of the first version of the con-
current control system.
Stage II: Prototyping of additional versions of the dynamic
part of the system:
5. Specification of a new version of the dynamic part by
an interpreted Petri net.
6. Description and logic synthesis of the new version of
the dynamic part, logic implementation of the new
version of the dynamic part together with the static part
of the controller.
Note that the designer may prepare as many versions of
the dynamic part as needed.
Stage III: Dynamic partial reconfiguration of the system.
7. Dynamic reconfiguration of the controller.
Let us describe the proposed design method in more details.
The particular steps are explained with paying special atten-
tion to the splitting of the system into the dynamic and static
parts.
A. STAGE I: PROTOTYPING OF THE INITIAL
VERSION OF THE SYSTEM
1) SPECIFICATION OF THE SYSTEM BY AN
INTERPRETED PETRI NET
Initially, based on the informal specification, the concurrent
controller is described by an interpreted Petri net. Such a
specification naturally reflects the concurrency relations of
the designed system. Furthermore, control systems described
with Petri nets can be easily decomposed into sequential
modules. We shall use this property, since the modularity is
an important aspect of the proposed technique and it strongly
influences the selection of the reconfiguration part of the
system (please refer to Subsections 2A-2C).
Petri nets are supported by verification and analysis meth-
ods [27]–[30], [33]–[35]. The designer may also anal-
yse the reliability and robustness of the system [42]–[44].
Interpreted Petri nets are suitable for control process mod-
elling, as they additionally take into account the input and
VOLUME 6, 2018
output signals of logic controllers [2], [20], [25]–[30],
[37]–[41]. They are applied in various fields, such as system
engineering [28], flexible manufacturing systems [37], [38],
distributed systems [20] or concurrent control systems
implemented in digital devices [2], [19]. Furthermore, it is
possible to use them as an input format for formal verifica-
tion (such as model checking) which allows finding some
divergences between the formal model and the requirements
of the customer/user [31]–[34]. The verification is usually
performed automatically by dedicated tools, such as symbolic
model checker NuSMV or its extension – nuXmv [35].
2) SPLITTING OF THE SYSTEM INTO
DYNAMIC AND STATIC PARTS
This is an essential stage of the proposed prototyping flow,
thus we shall describe it in detail. Initially, the control system
is divided into sequential automata, called State Machine
Components (SMCs). Next, one of the SMCs is selected in
order to indicate the reconfigurable region of the system.
Finally, such a region is divided into two parts: dynamic and
static. The dynamic part forms the reconfigurable resources
in the destination FPGA, which can be reprogrammed on-the-
fly without the stopping of the system. Let us present those
steps in more detail.
a: SM-DECOMPOSITION OF THE CONTROLLER INTO SMCs
The SM-decomposition splits the specified control system
into the state machine components. Indeed, each of the
obtained SMCs forms a sequential automaton [2], [20], [38].
This is an important step in the proposed design technique,
and we shall use the obtained results in further steps. In case
of relatively small nets, such a process can be done even
manually. However, if a controller contains a lot of concur-
rent tasks, the SM-decomposition is a real challenge to the
designer. There are several algorithms that can be applied
to perform an SM-decomposition. One of the most popular
methods is based on a linear algebra technique where place
invariants are computed [23], [36], [41]. Loosely speaking,
such an algorithm solves linear equations based on the inci-
dence matrix of an initial Petri net. Invariant-based meth-
ods are relatively fast and easy to implement, thus they are
widely applied in various design methods for concurrent
systems [23], [41].
In the proposed algorithm we shall apply the modified
method initially shown in [39]. However, contrary to the
original idea (where the set of place invariants is computed),
the aim of the presented technique is to compute proper
SMCs. The decomposition method includes 6 sub-steps:
1) Formation of the unit matrix Q = [Dn×n |Am×n ], where
D is initially equal to an identity matrix In , and A is an
incidence matrix of the Petri net.
2) For each column (transition) tj :
a) find row pairs that annul the j-th column of A
(i.e. their sum is equal to 0) and append it to
matrix Q,
b) delete all rows of Q in which the intersection with
the j-th column is not equal to 0,
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 R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems

c) reduce all rows of Q whose binary covers other Algorithm 1 Splitting of Region SR into parts SD and SS
ones. Input: Reconfigurable region SR = (PR , TR , FR , M0R , XR ,
3) Formation of the set of supports of all minimal p- YR ) set of dynamically reconfigurable places PDR
invariants J . Such a set is directly achieved from the Output: Dynamic part SD = (PD , TD , FD , M0D , XD , YD )
matrix Q, since its rows refer to the obtained place static part SS = (PS , TS , FS , M0S , XS , YS )
invariants.
// The dynamic part:
4) Formation of the set of S-components S: for each sup-
port I ∈ J examine whether I contains exactly one 1: PD ←− PDR //Split the set of places according to
token in the initial marking. If so, S = S ∪ I . PDR
5) Selection of the achieved S-components. Sometimes, 2: PD = PD ∪ {NOPS } //Add NOPS to replace static
especially in the case of large controllers, an additional part
selection of SMCs ought to be performed. Such a step 3: for all [p ∈ PD ] do
can be done automatically with the use of dedicated 4: if[• • p = ∅] then • • p = NOPS
algorithms [2], [38], but usually designers select com- 5: else if [p • • = ∅] then
ponents manually to satisfy exactly their needs. 6: p • • = NOPS
6) Replacement of the repeated places by NOPs: for 7: Yp = [outputs generated by place p; Yp ∈ YD ]
S-components Si , Sj ∈ S, examine whether there is 8: Yp = Yp ∪ {zD }
a place p such that p ∈ Si and p ∈ Sj . If so, replace it 9: YD = YD ∪ {zD }
in one of the components by a non-operational place. 10: end if
Please note that such a replacement can be easily auto- 11: end for
mated, however the designer may decide in which SMC 12: if (M0R ∈ PD ) then M0D = M0R //Assign initial marking
the place is replaced by a NOP [2]. M0D
The above algorithm enables the determination of the state 13: else M0D = NOPS
machine components for a Petri net. Each of the compo- //The static part:
nents forms a Finite State Machine (FSM). This means that
14: PS ←− PR /PDR
operations inside the single SMC are executed sequentially.
15: PS = PS ∪ {NOPD } //Add NOPD to replace dynamic
We shall apply this property in order to select the reconfig-
part
urable region of the system.
16: for all [p ∈ PS ] do
Note that instead of the linear algebra, any known decom-
17: if [p • • = ∅] then p • • = NOPD
position method can be applied. The presented design flow
18: else if [• • p = ∅] then
simply requires division of the initial net into the sequential
19: • • p = NOPD
automata, therefore other decomposition algorithms may be
20: Yp = [output signals generated by p; Yp ∈ YS ]
used (cf. [2], [25]).
21: Yp = Yp ∪ {zS }
b: SELECTION OF THE RECONFIGURABLE REGION (ONE OF 22: YS = YS ∪ {zS }
THE DECOMPOSED AUTOMATON) OF THE CONTROLLER 23: end if
At this point, the reconfigurable region (further denoted as 24: if [p 6 = NOPD ]
SR ) of the system is selected. In the proposed design tech- 25: Yp = [output signals generated by p; Yp ∈ YS ]
nique, such a region strictly refers to modules obtained during 26: Yp = Yp ∪ {Ral}
the decomposition. Indeed, the designer selects one of SMCs. 27: end if
The reconfigurable (dynamic) part of the system is located 28: end for
inside the selected region. Particularly, the set of dynamically 29: YS = YS ∪ {Ral}
reconfigurable Petri net places (denoted by PDR ) is selected 30: if (M0R ∈ PS ) then M0S = M0R //Assign initial marking
directly by the designer. This operation is executed manually, M0S
and it strictly depends on the requirements. For example, 31: else M0S = NOPD
in the case of the milling machine example (presented in the //Synchronization (zD and zS ) and request (Req) sinnals:
subsequent section), the set of reconfigurable places is related 32: xD = [logical conditions assigned to NOPD •; xD ∈
to the operations of cutting out the proper shape from the XD ]
wood. 33: xD = xD ∧ zD
Furthermore, there are no strict rules regarding such 34: XD = XD ∪ {zD }
a selection, however the set of chosen places ought to form 35: xS = [logical conditions assigned to NOPS •; xS ∈ XS ]
a connected subnet. In particular, rules 1,3,4,5 from Defini- 36: xS = xS ∧ zD
tion 4 ought to be fulfilled, since further supplementation by 37: xR = [logical conditions assigned to • M0S ; xR ∈ XS ]
the non-operational place makes the net strongly connected 38: xR = xR ∪ {Req}
(rule 2) and marked at the initial state (rule 6), which we shall 39: XS = XD ∪ {zS Req}
show later (cf. Algorithm 1). 40: return [SD , SS ]

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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
c: SPLITTING OF THE RECONFIGURABLE REGION INTO THE
DYNAMIC AND STATIC MODULES
At this step, the reconfigurable region SR is split into two
components (sub-modules). The division of the places is
executed according to the set PDR of reconfigurable places,
specified manually by the designer.
FIGURE 1. The splitting schema of the reconfigurable module.
Figure 1 shows the splitting schema of the reconfigurable
region into two partitions: dynamic and static. The first
one (dynamic module) is exchanged during the reconfig-
uration process, without interrupting the rest of the sys-
tem. The second component (static module) includes the
non-reconfigurable partition.
The main role of such a splitting is to prevent the con-
troller executing operations of the dynamic module while
the reconfiguration is being performed. Furthermore, special
synchronization and reconfiguration signals are introduced.
Formally, the splitting procedure divides the automaton SR
into two automata: SD and SS (where SD denotes dynamic
sub-module, and SS refers to a static one), as shown in
Fig. 1. There are two additional reconfiguration signals that
are added to the design: Reconfiguration Request (Req) and
Reconfiguration Allowed (Ral). The first one (Req), is added
as an input signal to the control system. It is assumed that
this signal is activated by the operator in order to proceed
the partial reconfiguration procedure. If this signal is active,
the reconfigurable region is not allowed to enter the recon-
figurable states and dynamic partial reconfiguration can be
safely proceeded. Moreover, Req prevents execution of oper-
ations in all other SMCs that are concurrent to the dynamic
module. The second reconfiguration signal (Ral) is an output
signal and it is assigned to all places of the static sub-module.
This signal is used to inform that the reconfiguration process
can be safely executed. In addition, Ral is gated with the Reset
signal in the dynamic module. Therefore, dynamic part is
permanently zeroed when the reconfiguration is allowed (that
is, when Ral is active) in order to avoid unstable states and to
satisfy Xilinx requirements [7]. Furthermore, internal signals
zD and zS are used to synchronize both sub-modules.
Algorithm 1 presents the proposed splitting technique
in a formal way. Based on the reconfigurable region
VOLUME 6, 2018
SR (specified as an interpreted Petri net), and the set of
dynamically reconfigurable places chosen by the designer
(PDR ), the dynamic (SD ) and static (SS ) modules are gener-
ated (they are also specified as interpreted Petri nets). Gen-
erally, the algorithm is divided into three sections: lines 1-
13 refer to the dynamic module, lines 14-30 describe the static
module, while the remaining code deals with the synchroniza-
tion signals.
The algorithm can be described as follows:
1) Splitting of the set of places (according to PDR ) into
two disjoint subsets: PDR = PD ∪ PS in such a way that
PD ∩ PS = ∅ (lines 1 and 14).
2) Supplementation of the dynamic module by non-
operational place NOPS in order to substitute all the
places that belong to the static module (lines 2-11, note
that for all loop is executed to connect NOPS with the
remaining places of the dynamic module).
3) Determination of the initially marked place of
the dynamic module (lines 12-13). Simply, if PD
contains M0R , then such a marking becomes the initial
state of the dynamic module. Otherwise, NOPS is
assigned as an initial marking.
4) Supplementation of the static module by non-
operational place NOPD to substitute all the places
that belong to the dynamic module (lines 15-28), note
that for all loop is executed to connect NOPD with the
remaining places of the static module).
5) Determination of the initially marked place of the
static module (lines 30-31). Simply, if PS contains M0R ,
then this marking becomes the initial state. Otherwise,
NOPD is assigned as an initial marking.
6) Supplementation of the outputs Yp ∈ YS (generated by
places p ∈ PS NOPD }) by Ral signal (lines 24-27, 29).
7) Supplementation of both parts by the synchronization
signals zD and zS (lines 7-9, 20-22, 32-37, 39). Those
signals assure disjoint functionality of the dynamic and
static modules. Simply, the dynamic module can be
reconfigured while the controller executes operations
assigned to the places of the static module. Particularly,
zD is added as an input signal to the static module and
forms a logical condition for the transition NOPD •.
This signal is produced by the dynamic module. Thus,
zD is added as an output signal generated by • • NOPS
(i.e. former place of NOPS ). Similarly, zs is added as an
input signal to the dynamic module and forms a logical
condition for the transition NOPS •. Furthermore, it is
generated by the place • • NOPD in the static module.
It should be noted that there is a possibility that
a synchronization signal is already assigned to
NOPS or NOPD (as a result of SM-decomposition).
In such a case, this signal can be used instead of zD
or zS . We shall show a proper example in Section 4.
8) Supplementation of the static part by the Req signal
(lines 37-39). Particularly, Req (negation of Req signal)
is assigned to the transition NOPD (i.e. input transition
of NOPD ). This signal is also assigned to the other
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SMCs (cf. step 2D), in order to synchronize all the
remaining components of the controller.
Proposition 1: The splitting procedure executed by
Algorithm 1 is done in O(|P|) time, where |P| denotes the
number of the places in the net.
Proof: The first for loop (obtaining of the dynamic part) is
executed at most |P| times, where |P| denotes the number of
places in the net. Furthermore, the second for loop (addressed
for the static part) is also executed at most |P| times. Note that
neither inner conditional operations, nor final assignments to
the synchronization signals has any influence on the com-
plexity of the algorithm. Summarizing, the computational
complexity of the Algorithm 1 is O(|P|) by the number of |P|
places of the net.  place p2 (that is, by •• NOPD ) in the static module.
Note that the complexity of the complete design flow
also depends on the other steps (such as SM-decomposition,
c.f. [2], [25] for more details).
FIGURE 2. An example of splitting of a reconfigurable region.
Let us explain the above procedure by a brief example.
Figure 2 shows an exemplary reconfigurable module that
contains four places: PR = {p1 , . . . , p4 }, and M0R = p1 .
Assume that the designer selects the following reconfigurable
places: PDR = {p3 , p4 }. Therefore, the splitting operation
shall be executed as follows:
1) The set of places PR is split into two disjoint subsets,
in such a way, that PD = {p3 , p4 }, and PS = {p1 , p2 }.
2) The dynamic module is supplemented by NOPS .
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
3) Since M0R ∈/ PD , thus M0D = NOPS .
4) The static module is supplemented by NOPD .
5) Since M0R ∈ PD , thus M0S = p1 .
6) Ral signal is added as an output signal generated
by places p1 and p2 .
7) Synchronization signals are added to both modules:
– zD is assigned as a logical condition to t4 (that is,
to NOPD •) in the static module;
– zD is assigned as an output signal generated by
place p4 (• • NOPS ) in the dynamic module;
– zS is assigned as a logical condition to t20 (that is,
to NOPS •) in the dynamic module;
– zS is assigned as an output signal generated by
8) Req is assigned to t2 (input transition of NOPD ).
d: SUPPLEMENTATION OF ALL REMAINING COMPONENTS
BY THE RECONFIGURATION REQUEST SIGNAL
At the subsequent stage of the splitting procedure, all the
remaining SMCs (except the reconfigurable region) ought
to be supplemented by the reconfiguration request signal.
Recall, that such a signal is added as an input to the con-
trol system and it is activated by the operator in order to
initiate the partial reconfiguration procedure (cf. step 2C).
Simply, Req is assigned to all instances of the transition
• NOPD (if any exist). For example, if a system from Fig. 2.
shares transition t2 (which is an input transition of place
NOPD ) between two or more components, Req is assigned
as a logic condition to this particular transition in all those
SMCs, except the reconfigurable region (since the reconfig-
urable request signal is already assigned to t2 in the static
module).
e: FORMATION OF THE DYNAMIC AND STATIC PARTS
Finally, the dynamic and static parts are formed. The first
one, dynamic part, is simply formed from the dynamic mod-
ule obtained during step 2B. Furthermore, the static mod-
ule, together with other controller components (except the
dynamic module) form the static part of the system.
We shall follow the above notations in our further descrip-
tions. For better understanding of the splitting idea of the
reconfigurable module into static and reconfigurable parts
please also refer to Section 4, where a case-study of a practical
example is shown.
3) DESCRIPTION OF THE CONTROLLER IN HDLS,
SYNTHESIS AND LOGIC IMPLEMENTATION OF
THE FIRST VERSION OF THE SYSTEM
Once the controller is split into the dynamic and static parts,
it can be described in the hardware description languages.
Each of decomposed automata is encoded separately, thus
there is a possibility to apply various techniques or even
hardware languages. In our considerations we shall follow
recommendations proposed by Xilinx [7]. Furthermore, Ver-
ilog language shall be used to show a case-study example.
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
Next, the system is logically synthesized and logically
implemented. In order to perform this task, the selection of
the reconfigurable area of the destination FPGA ought to be
performed (not to be confused with step 2B, where the recon-
figurable region is selected). This operation is relatively easy,
and it is executed with the use of the device vendor’s tool.
The selection of the reconfigurable area indicates hardware
resources that will be utilized by the dynamic part, and it has
a strict influenced on the size of the generated data used to
program the FPGA device.
Once the selection of the reconfigurable area is done,
the whole controller (static and dynamic parts) is logically
implemented. As a result of this operation, the configuration
data for FPGA (called bit-streams) is produced. In the pre-
sented prototyping flow, two files are generated. The first
one contains the complete information about the controller
(that is, about both static and dynamic parts of the system).
It will be used for the initial programming of the FPGA.
The second file is a reduced bit-stream, and it contains
the reduced information about the dynamic part of the sys-
tem. Note that the above procedures (description in HDLs,
logic synthesis and implementation) can be easily automated,
cf. [45].
4) PHYSICAL IMPLEMENTATION OF THE CONTROLLER
The concurrent control system is ready for physical imple-
mentation. The programming of the FPGA is executed
according to the Xilinx guidelines [7]. The most popular
technique bases on the application of the traditional JTAG
(Joint Test Action Group) connector. However, a lot of
Xilinx FPGAs can be also programmed via a USB (Uni-
versal Serial Bus) port. At the current stage, the FPGA
device is configured with the use of full bit-stream (obtained
in the previous step). However, it should be pointed out,
that it is ready for further dynamic partial reconfiguration
(cf. Stage III).
Let us now describe steps required in order to prepare dif-
ferent versions of the dynamic module. Note that the designer
is able to create as many different versions of the dynamic part
as needed.
B. STAGE II: PROTOTYPING OF ADDITIONAL VERSIONS
OF THE DYNAMIC PART OF THE SYSTEM
1) SPECIFICATION OF THE NEW VERSION OF THE
DYNAMIC MODULE BY AN INTERPRETED PETRI NET
The new version of the dynamic part is specified with the use
of an interpreted Petri net. It is performed in the same way as it
was described in Subsection 2A. However, some restrictions
ought to be fulfilled:
– the module ought to be prepared as a state machine
component (to form a sequential automaton),
– NOPS , together with its incoming and outcoming tran-
sitions remain unchanged, that is, they are exactly the
same as obtained during step 2A,
– synchronization signal zD is assigned to the place
• • NOPS (i.e., to the former place of NOPS ),
VOLUME 6, 2018
– synchronization signal zS is assigned as a logical con-
dition to the transition NOPS • (i.e., output transition of
place NOPS ).
2) DESCRIPTION AND SYNTHESIS OF THE NEW VERSION
OF THE DYNAMIC PART, LOGIC IMPLEMENTATION
OF THE CONTROLLER
Once the new version of the dynamic module is specified,
it is described by the use of HDLs. The rules are exactly the
same as was shown in step 3. Next, the new version of the
dynamic part is logically implemented in order to generate
the final bit-streams. The static part is imported from the first
implementation of the controller (produced during step 3).
This operation results in two files. The first one contains
information about the complete system, and it can be used
as an initial bit-stream in the future. The second bit-stream
is a partial one, and it will be used for the dynamic partial
reconfiguration of the system.
C. STAGE III: DYNAMIC PARTIAL RECONFIGURATION
OF THE SYSTEM
1) DYNAMIC PARTIAL RECONFIGURATION OF
THE CONTROLLER
The concurrent controller system is ready for the dynamic
partial reconfiguration. It is assumed that dynamic partial
reconfiguration is executed on demand. Initially, Req signal
is activated by the operator. The controller responds with the
Ral signal, which means that the system can be safely recon-
figured. While the device is being reconfigured, the static part
of the system is still working and executing assigned tasks.
Once the partial reconfiguration is finished, the controller is
able to perform operations specified by the new version of the
dynamic module. Note that the above procedure can be easily
automated. Thus, the whole reconfiguration process can be
executed without human supervisor or operator. We shall
present this benefit by the case-study below.
IV. THE CASE-STUDY EXAMPLE
An example that illustrates the design method is a real-life
system, initially proposed in [20]. Figure 3 shows a model
of a milling process. The aim of the presented machine is
to cut required shapes from the wooden plank. The process
is driven by a concurrent control system that communicates
with the environment with the use of input X = {x1 , . . . , x20 }
and output signals Y = {y1 , . . . , y14 }. The description of all
the signals is listed in Table 1.
The behavior of the system can be described as follows.
Placement of a wooden plank on the tray (indicated by the
sensor x1 ) initializes the milling process. The plank is moved
(output signal y1 ) to the remaining positions of the drilling
station (signalized by a sensor x2 ). At the same time, a drill
(y2 ) is moved downwards, to the starting position (x3 ) local-
ized on the southeast corner of the cutting shape. When the
above two operations are completed, the machine is ready
for cutting the required shape from the wood. Five tasks are
executed concurrently:
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 R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems

TABLE 1. Description of input and output signals of the system.

FIGURE 3. Model of the milling machine.

1) The required shape is being cut out of the plank. This

process is executed by actions associated to output sig-
nals y3 , . . . , y8 . The required shape is achieved thanks
to sensors x5 , . . . , x8 localized at each side of the plank.
Four additional sensors x17 , . . . , x20 may be used in
order to cut out more advanced shapes (like ‘‘L’’-shape,
‘‘U’’-shape, etc.).
2) The assembly holes on the top of a wooden plank
are drilled by executing actions associated with output
signals y9 and y10 (according to sensors x10 and x11 ).
3) Assembly holes on the bottom of a wooden plank are
drilled (outputs y11 , y12 , and sensors x12 , x13 ).
4) Vacuum cleaner is turned on (output y13 ).
5) Depending on the light sensor (signal x14 ), the halogen
lamp is either turned on (y14 ) or off.
Finally, the ready (cut-out) shape is removed from the
machine (y15 ). Simultaneously, the drill is cooled down. After Initially, the system is decomposed into sequential automata.
completing the above operations, the system waits until the This process splits the net into state machine components.
wooden plank is taken away from the tray (x1 ), and the In our analysis, five SMCs S = {S1 , S2 , S3 , S4 , S5 } are
drilling process can be repeated for another plank. obtained:
The discussed system can be specified by an interpreted • S1 = {p1 , p2 , p3 , p6 , p7 , p8 , p9 , p10 , p11 , p12 , p23 , p24 },
Petri net, as shown in Fig. 4. The net consists of 26 places • S2 = {NOP1 , p4 , p5 , p13 , p14 , p15 , p25 , p26 },
and 21 transitions. In this version of the controller, the milling • S3 = {NOP2 , p16 , p17 , p18 },
machine cuts out square shapes from the wooden plank • S4 = {NOP3 , p19 },
(places p7 , . . . , p10 ). Input signals of the controller are asso- • S5 = {NOP4 , p20 , p21 , p22 .}
ciated with the transitions, while outputs are assigned to Figure 5 shows the decomposed and synchronized net.
the places. Note that signal x14 (light detector) determines There are four non-operational places, such that NOP1
whether the halogen lamp ought to be turned on (y14 ). Fur- replaces {p1 } in the second component, NOP2 replaces
thermore, transition t4 splits the functionality of the controller {p1 , p2 , p3 , p23 , p24 } in the third SMC, etc.
into five processes, while t18 joins them. The functionality of the achieved components can be
Let us now apply the proposed prototyping technique by described as follows. The first subnet (S1 ) controls the move-
splitting of the controller into the dynamic and static parts. ment of a wooden plank on a tray to the required position

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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
FIGURE 4. Interpreted Petri net that describes the milling machine.
(in both directions: left and right) and cutting-out the required
shape from the wood. The second component is responsible
for preparing the main drill to the starting position, drilling
of the assembly holes on the top of the wooden plank, and
cooling off the drill when the milling process fishes. Actions
performed by the third automaton prepares assembly holes on
the bottom of the plank, while the fourth subnet controls the
vacuum cleaner. Finally, the fifth component executes tasks
related to the halogen lamp.
VOLUME 6, 2018
FIGURE 5. Decomposed and synchronized net of milling machine.
According to the proposed method, one of the SMCs ought
to be selected as a reconfigurable region. In our consider-
ations, component S1 is chosen in order to exchange the
functionality of the process that is responsible for cutting
the shape. Note that particular places {p6 , . . . , p12 } are in
response to the cutting of the proper shape. Thus, we shall
select them as reconfigurable places: PDR = {p6 , . . . , p12 }.
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FIGURE 6. Splitting of S1 into static and dynamic modules.
Let us now apply Algorithm 1 to split the reconfigurable
region S1 into dynamic (SD ) and (SS ) static parts. We shall
follow the notations applied in Section 2 in order to present
the particular actions performed by the Algorithm 1.
The splitting procedure is executed as follows (Fig. 6):
1) The set of places of the reconfigurable region PR =
{p1 , p2 , p3 , p6 , . . . , p12 , p23 , p24 } is split into two sets:
PD = {p6 , . . . , p12 }, and PS = {p1 , p2 , p3 , p23 , p24 }.
2) The dynamic part is supplemented by NOPS .
3) Since M0R ∈ / PD , thus M0D = NOPS .
4) The static part is supplemented by NOPD .
5) Since M0R ∈ PD , thus M0S = p1 .
6) Signal Ral is added to all p ∈ PS ({p1 , p2 , p3 , p23 , p24 }).
7) Synchronization signals between both parts. Note that
there are already synchronization signals z3 and z2 gen-
erated by places • • NOPS and • • NOPD , respectively.
Those signals are used for proper synchronization of
SMCs. Let us use them instead of introducing addi-
tional signals zD and zS :
• z3 is generated by place p12 (• • NOPS ) in the
dynamic part, therefore it can be assigned as a
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
FIGURE 7. Sample Verilog code of module S3 .
logical condition to transition t18 (NOPD •) in the
static part;
• z2 is generated by place p2 (• • NOPD ) in the
static part, therefore it can be assigned as a logical
condition to t40 (NOPS •) in the dynamic part.
8) Req is assigned to t4 (input transition of NOPD ).
Once the splitting of the reconfigurable module is com-
pleted, all the remaining modules that share transition
• NOPD are supplemented by the Ral signal. In the pre-
sented example, transition t4 is shared by all remaining SMCs
(cf. Fig. 5). Thus, Req is added as a logical condition to all
those components.
Finally, the dynamic and static parts are formed. Simply,
the dynamic part consists of the dynamic module containing
places {p6 , . . . , p12 }. Furthermore, the static module, together
with all the remaining SMCs (that is components S2 , . . . , S5 )
form the static part.
At the next step of the prototyping procedure, each of
the decomposed components are modeled as finite state
machines and described in Verilog HDL. Internal states are
encoded with the use of Gray code. Figure 7 presents a sam-
ple Verilog code of module S3 . The remaining SMCs are
described in a similar manner. Then, both parts are synthe-
sized according to Xilinx guidelines [7]. The resulting files
are used as input data of the logic implementation. This
operation (including selection of the reconfigurable area of
an FPGA and generation of the output bit-streams) is per-
formed by the dedicated tool. In particular, we used Xilinx
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
FIGURE 8. New version of dynamic part (cutting of the ‘‘U’’-shape).
PlanAhead 14.7. As a result of the implementation process,
two files are produced. The first one, full bit-stream, contains
the complete information about the controller. The second
file, partial bit-stream, includes only reduced data about the
dynamic module.
The initial version of the controller is ready for physi-
cal implementation. At this step, the FPGA device is pro-
grammed with the use of full bit-stream. The system is ready
for further partial reconfiguration. Let us prepare an addi-
tional version of the dynamic part of the controller.
Let us modify the functionality of the controller. Now,
we shall prepare an alternate version of the dynamic mod-
ule, where the milling machine will be able to cut out a
‘‘U’’-shape from a wooden plank. Figure 8 shows the spec-
ification of the new version of the dynamic module. Note
that the required ‘‘U’’-shape is more complicated than the
previous one (square). Indeed, there are twelve places in the
net, four more than in the initial version (cf. Fig. 6).
The new version of the dynamic module is described in the
Verilog HDL. We shall apply exactly the same coding style,
as it was shown in Fig. 7. Note that there are 12 places in
the net, therefore the modelled module contains more states
compared to the initial version. Next, the dynamic module is
logically synthesized and implemented. These operations are
executed in order to generate the final bit-streams for the new
version of the controller.
VOLUME 6, 2018
Finally, the functionality of the controller can be dynam-
ically exchanged with the produced partial bit-streams. The
reconfiguration process is started by sending Req signal to
the implemented controller.
Note that there are no restrictions regarding this signal,
it can be set at any time. The functionality of the system can
be safely exchanged if Ral signal is active. In the presented
example, this signal is generated by the following places:
p1 , p2 , p3 , p23 , p24 (cf. Fig. 8). It means, that the controller
can be dynamically reconfigured, for example, during the
replacement of the wooden plank (p1 ), or while moving the
tray to the left (p2 ) or to the right (p23 ). Note that configu-
ration time does not influence on the behavior of the system
thanks to the synchronization signals. However, operations
that are executed in the remaining subnets may affect the
reconfiguration process. For example, moving of the drill to
the required position (p4 ) or cooling-off the drill (p25 ) are
executed concurrently to the static part. Thus, those opera-
tions are sequential to the dynamic part, which means that
the controller can be safely dynamically reconfigured.
V. EXPERIMENTAL RESULTS AND ANALYSIS
The proposed design flow was verified experimentally. First,
the milling machine system was implemented and dynam-
ically reconfigured. Furthermore, the set of representative
concurrent controllers was verified with the application of the
proposed prototyping flow. Each system was implemented in
the FPGA and reconfigured with at least one new version
of the dynamic module. Finally, the summarized results of
experiments are concluded by exposing the limitations and
scope of the proposed ideas.
A. HARDWARE VERIFICATION OF THE
CASE-STUDY EXAMPLE
For testing purposes, the system of the milling machine pre-
sented in the case study was used. In addition, a third version
of the dynamic module was prepared (cutting of ‘‘L‘‘-shape).
Furthermore, an appropriate emulator of the milling machine
was created. It was prepared as a digital system, described
in Verilog HDL. The complete system (controller and emu-
lator) was implemented with the use of the FPGA device
XC5VLX50 (Virtex-5 family, a part of the board ML501 Eval-
uation and Development Platform).
Figure 9 shows the logic schema of the verification system.
The appropriate shapes (cut out by the milling machine) are
represented by two 7-segment displays (PmodSSD from Dig-
ilent). Additionally, LEDs of the ML501 board were used to
represent the selected outputs of the controller (position of the
tray, mounting of the assembly holes on the top and bottom
of the wooden plank, activity of the vacuum cleaner, halogen
lamp, and Reconfiguration Allowed signal). Two external
inputs of the system (Reset and Reconfiguration Request)
were assigned to the external switches. Both components
(controller and emulator) were oscillated by the internal clock
signal of the ML501 board (100MHz). Figure 10 illustrates
the working system, while an ‘‘L’’ shape is being cut. The
32387

FIGURE 9. Logic schema of the verification system.
FIGURE 10. A photo of working system (cutting of the ‘‘L’’-shape).
functionality of the system was additionally checked by an
oscilloscope (MSO 2024 from Tektronix). Therefore, appro-
priate input and output signals were connected and measured.
Going into more details, the verification procedure
included the following steps:
1) Preparation of the first version of the controller (cutting
out of a square), according to Stage I of the proposed
design flow.
2) Preparation of the second version of the controller (cut-
ting out of a ‘‘U’’-shape), according to Stage II.
3) Preparation of the third version of the controller (cut-
ting out of an ‘‘L’’-shape), according to Stage II.
4) Preparation of the milling machine emulator (a digi-
tal system that emulates the behavior of the milling
machine by reacting to the input sensors with the appro-
priate outputs on the 7-segment displays and LEDs of
the ML501 board).
5) Programming of the FPGA with the use of the full bit-
stream produced at the first step (that is, programming
of the FPGA with the first version of the controller),
together with the emulator.
6) Dynamic partial reconfiguration of the system with the
use of all three partial bit-streams generated during
steps 1-3, according to Stage III of the flow.
Programming of the system, as well as dynamic partial recon-
figuration, was performed with the use of Xilinx Platform
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
FIGURE 11. Hardware results recorded by the oscilloscope.
Cable USB II. Figure 11 shows the hardware verification
results recorded by the oscilloscope. Three cycles of the
milling machine are presented. Initially, the ‘‘U’’-shape is cut
from the wood (outputs y4 , y5 , y6 , y7 ).
The first dynamic partial reconfiguration is performed dur-
ing movement of the tray to the right (y15 ). It can be noticed,
that signals y4 , . . . , y7 become unstable for a moment. This is
caused by exchanging the dynamic part of the system. Note
that static part of the controller is still working, which can be
observed by signals y1 , y2 , y15 , y16 . The system is now able to
cut square shapes. Finally, dynamic partial reconfiguration is
executed once more. After this operation, the milling machine
cuts an ‘‘L’’-shape from the plank.
B. EXPERIMENTAL VERIFICATION OF THE
PROPOSED TECHNIQUE
The proposed design flow was verified experimentally. The
representative concurrent control systems (denoted as bench-
marks) were split into the static and dynamic partitions and
implemented in the Xilinx FPGA devices. Next, their func-
tionality was modified with the use of the dynamic partial
reconfiguration technique. For each control system, at least
one additional version of the dynamic module was prepared.
The set of benchmarks included real systems, such as a HAN
(home area network) controller [46], a concrete mixer [25],
a milling machine or a system that coordinates traffic lights
(crossroad).
Furthermore, the hardware resource utilization of the
reconfigurable area consumed by the representative concur-
rent control systems was analysed. In particular, the number
of slices occupied by the reconfigurable area was determined.
Moreover, the size of the full bit-stream (containing the
description of the whole system), and the size of the partial
bit-stream (which holds information about the reconfigurable
part only) were compared.
Table 2 shows the results gained during the experiments.
The particular columns present the name of the benchmark,
the FPGA device (used to verify this benchmark), the number
of all slices available for the applied FPGA, the number of
slices directly utilized by the reconfigurable area, and the
sizes of the full and partial bit-streams. There were three
different FPGA devices applied in the performed experi-
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R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
TABLE 2. Hardware utilization of the reconfigurable area by the representative control systems and bit-streams sizes.
ments. Most of benchmarks were verified with the use of
XC5VLX50 (Xilinx Virtex-5 family) and XC7A100T (Xilinx
Artix-7 family) devices. Additionally, one of the controllers
was also implemented and dynamically reconfigured with the
application of high-performance FPGA XC7VX485T (Xilinx
Virtex-7 family), just for analytic purposes.
It can be observed that the size of the reduced bit-stream
(partial bit-stream) is much smaller than the full one. The
highest reduction was achieved for the Xilinx Virtex-7 device,
where the size of the partial bit-stream is over 670 times
smaller compared to the full data. Obviously, beside the
FPGA used, the reduction ratio is strictly related to the
implemented controller, and to the selected reconfigurable
region. Thus, the lowest values were achieved forHAN and
Counter systems, that utilized more than 20 FPGA slices
by the reconfigurable area. Nevertheless, even in those
cases, the partial bit-stream is much smaller (over 64 times)
than the full one.
C. LIMITATIONS AND SCOPE
Let us briefly summarize limitations of the proposed tech-
nique. Firstly, the presented approach applies Petri net theory
to describe the concurrent control system. For designers that
are not familiar with this methodology it can be embarrassing
to change their habits in order to apply Petri nets to specify
their systems. On the other hand, it is worth mentioning that
the presented design flow takes care of all the remaining steps
that are required to prepare the system for compatibility with
further dynamic reconfiguration in Xilinx FPGAs.
Furthermore, the selected set of reconfigurable places
should form a connected subnet. Clearly, this rule limits
the application of the presented technique, and additionally
enforces decomposition of the net into sequential automata.
Finally, the proposed prototyping technique is limited
to the interpreted Petri nets, that is, live and safe nets. Nev-
ertheless, it seems that it is possible to expand the presented
technique to the more general class of Petri nets. In particular,
extension of the safety aspects can be considered, as well as
inclusion of the flexible manufacturing systems based on the
Petri nets [37], [47]–[50].
The paper proposes a complete design path for the con-
current controllers specified by interpreted Petri nets and
VOLUME 6, 2018
implemented in Xilinx FPGA devices. The presented solution
permits further dynamic partial reconfiguration of the already
implemented system. The proposed technique is especially
applicable for controllers executing crucial operations that
cannot be interrupted. The functionality of one part of the
controller is modified while the rest of the system is still
working.
VI. CONCLUSIONS
The paper proposes a new design path for dynamically recon-
figurable logic controllers implemented in FPGA devices.
Contrary to the existing methods, the presented concept does
not require major changes to the design, nor the applica-
tion of specialized tools. The main idea of the proposed
method relies on the splitting of the controller into the
static (non-reconfigurable) and dynamic (reconfi-gurable)
parts. The presented design concept for reconfigurable logic
controllers has been successfully experimentally tested with
Xilinx FPGAs.
There are several benefits of the proposed method. First of
all, the complete prototyping flow of concurrent logic con-
trollers oriented for further partial reconfiguration is shown.
Furthermore, the designer is able to prepare as many versions
of the reconfigurable part, as needed. Moreover, there is no
limitation regarding execution times of the dynamic partial
reconfiguration. Therefore, the system can be partially recon-
figured as many times as it is required.
On the other hand, the proposed technique strictly refers
to the systems specified by an interpreted Petri net. Further-
more, the selection of the reconfigurable region is limited to
the single state machine component. Therefore, the enhance-
ment of the proposed design flow is considered for future
research. In particular, application of the presented technique
to other classes of Petri nets will be considered (bounded nets,
flexible manufacturing systems).
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VOLUME 6, 2018
R. Wiśniewski: Dynamic Partial Reconfiguration of Concurrent Control Systems
REMIGIUSZ WIŚNIEWSKI (M’17) received the
Ph.D. degree in computer science from the Univer-
sity of Zielona Góra in 2008 and the D.Sc. degree
in computer science from the Silesian University
of Technology in 2018. From 2000 to 2003, he was
with Aldec, Inc., Henderson, NV, USA, where
he conducted specialized training for companies,
such as Xilinx, San Jose, CA, USA, and Intel,
Austin, TX, USA.
VOLUME 6, 2018
He is currently an Assistant Professor with the Institute of Electrical
Engineering, University of Zielona Góra. He is a Co-founder and a Coor-
dinator of the research project Hippo (www.hippo.iee.uz.zgora.pl). He has
authored over 100 peer-reviewed research papers and books. His research
interests include the design of control systems, Petri nets, programmable
devices, field programmable gate arrays (FPGAs), partial reconfiguration
of FPGAs, perfect graph and hypergraph theories, and cryptology. He is a
member of IES and SMC societies. He is an Associate Editor of the IEEE
ACCESS journal.
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