STANDARD SEQUENTIAL MODULES

 REGISTERS
 SHIFT REGISTERS
 SYNCHRONOUS COUNTERS
 FOR EACH MODULE WE SHOW:
 SPECIFICATION
 IMPLEMENTATION WITH FFs AND GATES
 BASIC USES
 HOW TO IMPLEMENT LARGER MODULES

Introduction to Digital Systems 11 { Standard Sequential Modules

 REGISTERS
2

Data input x

Control inputs n
LD (Load)
CLK REGISTER
CLR (Clear)
n

Data output z
Figure 11.1: n-BIT REGISTER MODULE

Introduction to Digital Systems 11 { Standard Sequential Modules

 REGISTER: HIGH-LEVEL SPECIFICATION
3

INPUTS: x = (xn ; : : : ; x ); xi 2 f0; 1g

1 0
LD; CLR 2 f0; 1g
OUTPUTS: z = (zn ; : : : ; z ); zi 2 f0; 1g
1 0
STATE: s = (sn ; : : : ; s ); si 2 f0; 1g
1 0

FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS

8
x(t)>>
>< if LD(t) = 1 and CLR(t) = 0
s(t + 1) = s(t) >> if LD(t) = 0 and CLR(t) = 0
: : : 0)
>:
(0 if CLR(t) = 1
z (t) = s(t)

Introduction to Digital Systems 11 { Standard Sequential Modules

 IMPLEMENTATION OF 4-BIT REGISTER
4

x3 x2 x1 x0

1 0 1 0 1 0 1 0
MUX MUX MUX MUX
LD
CLK
CLR
D D D D
Q’ Q Q’ Q Q’ Q Q’ Q

z3 z2 z1 z0
Figure 11.2: IMPLEMENTATION OF 4-BIT REGISTER.

Introduction to Digital Systems 11 { Standard Sequential Modules

 TIME-BEHAVIOR OF REGISTER
5

Clock CLK

tsu setup time

Load LD

Input x

Output z

tp propagation delay

Figure 11.3: TIME-BEHAVIOR OF REGISTER.

Introduction to Digital Systems 11 { Standard Sequential Modules

 USES OF REGISTERS: Example 11.1
6

INPUT: x 2 f0; 1g
OUTPUT: (z ; z ); zi 2 f0; 1g
1 0
STATE: (s ; s ); si 2 f0; 1g
1 0
INITIAL STATE: (s ; s ) = (0; 0)
1 0

FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS:

PS Input
x=0 x=1
00 00 01
01 01 11
11 11 10
10 10 00
NS
z (t) = s(t)
Introduction to Digital Systems 11 { Standard Sequential Modules
 CANONICAL IMPLEMENTATION
7

Y = y x0 y x
1 1 0 Y = y x0 y 0 x
0 0 1

x x’ y 1 y’1

y1
x’
D flip-flops
y0 Y1
x y1
Y0
y0
y0
x’
y’1 CLK
x
(a)
Figure 11.4: NETWORKS FOR Example 11.1: a) NETWORK WITH STATE CELLS;

Introduction to Digital Systems 11 { Standard Sequential Modules

 IMPLEMENTATION WITH REGISTER
8

Y =y 1 0 Y = y0 LD = x
0 1

Y1 LD
y1

Y0 Register y0
CLR
CLK

(b) 0
Figure 11.4: NETWORKS for Example 11.1: b) NETWORK WITH STANDARD REGISTER MODULE

Introduction to Digital Systems 11 { Standard Sequential Modules

 SHIFT REGISTERS
9

Parallel data input x

Serial data input Serial data input

n
(right shift) (left shift)
xr xl
CLK SHIFT REGISTER
CTRL
2
n

Parallel data output z

Figure 11.5: SHIFT REGISTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 PARALLEL-IN/PARALLEL-OUT BIDIRECTIONAL SHIFT REGISTER
10

x n-1 x n-2 x0

xr xl
CLK n-1 n-2 0

CTRL
2
z n-1 z n-2 z0
Figure 11.6: PARALLEL-IN/PARALLEL-OUT BIDIRECTIONAL SHIFT REGISTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 HIGH-LEVEL SPECIFICATION
11

INPUTS: x = (xn ; : : : ; x ); xi 2 f0; 1g

1 0
xl; xr 2 f0; 1g
CTRL 2 fLOAD; LEFT; RIGHT; NONE g
STATE: s = (sn ; : : : ; so); si 2 f0; 1g
1
OUTPUT: z = (zn ; : : : ; z ); zi 2 f0; 1g
1 0

FUNCTIONS: STATE TRANSITION AND OUTPUT FUNCTIONS:

8
s(t)
>>
>> if CTRL = NONE
s(t + 1) = (xs(nt) ; : : : ; s ; xl) CTRL = LOAD
>< if
>>
>> 2 0 if CTRL = LEFT
(xr ; sn ; : : : ; s )
>:
1 1 if CTRL = RIGHT
z=s

Introduction to Digital Systems 11 { Standard Sequential Modules

 SHIFT REGISTER CONTROL
12

Control s(t + 1) = z (t + 1)
NONE 0101
LOAD 1110
LEFT xl = 0 1010
LEFT xl = 1 1011
RIGHT xr = 0 0010
RIGHT xr = 1 1010

CTRL c c
1 0

NONE 0 0
LEFT 0 1
RIGHT 1 0
LOAD 1 1

Introduction to Digital Systems 11 { Standard Sequential Modules

 4-BIT BIDIRECTIONAL SHIFT-REGISTER
13

x3 x2 x1 x0
xl
xr

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
MUX MUX MUX MUX
c1
c0

D D D D
Q Q Q Q

CK

z3 z2 z1 z0

Figure 11.7: IMPLEMENTATION OF A 4-BIT BIDIRECTIONAL SHIFT REGISTER WITH D FLIP-FLOPS.

Introduction to Digital Systems 11 { Standard Sequential Modules

 SERIAL-IN/SERIAL-OUT UNIDIRECTIONAL SHIFT REGISTER
14

z (t) = x(t n)

xr
CLK n-1 n-2 0

CTRL
z
(a)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: a) SERIAL-IN/SERIAL-OUT

Introduction to Digital Systems 11 { Standard Sequential Modules

 PARALLEL-IN/SERIAL-OUT UNIDIRECTIONAL SHIFT REGISTER
15

x n-1 x n-2 x0

CLK n-1 n-2 0

CTRL
2
z
(b)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: b) PARALLEL-IN/SERIAL-OUT

Introduction to Digital Systems 11 { Standard Sequential Modules

 SERIAL-IN/PARALLEL-OUT UNIDIRECTIONAL SHIFT REGISTER
16

xr
CLK n-1 n-2 0
CTRL
z n-1 z n-2 z0

(c)
Figure 11.8: COMMON UNIDIRECTIONAL SHIFT REGISTERS: c) SERIAL-IN/PARALLEL-OUT

Introduction to Digital Systems 11 { Standard Sequential Modules

 SUMMARY OF SHIFT-REGISTER TYPES
17

xr
CLK n-1 n-2 0

CTRL
(a) z

x n-1 x n-2 x0

CLK n-1 n-2 0

CTRL
2
z
(b)

xr
CLK n-1 n-2 0
CTRL
z n-1 z n-2 z0
(c)

COMMON UNIDIRECTIONAL SHIFT REGISTERS: a) SERIAL-IN/SERIAL-OUT; b) PARALLEL-IN/SERIAL-OUT; c)

Figure 11.8:
SERIAL-IN/PARALLEL-OUT

Introduction to Digital Systems 11 { Standard Sequential Modules

 USES OF SHIFT REGISTERS
18

 SERIAL INTERCONNECTION OF SYSTEMS

System A System B
x n-1 x n-2 x0
xr

CLK n-1 n-2 0 CLK n-1 n-2 0

CTRL CTRL
2 z
z n-1 z n-2 z0

Figure 11.9: SERIAL INTERCONNECTION OF SYSTEMS USING SHIFT REGISTERS

 BIT-SERIAL OPERATIONS

Introduction to Digital Systems 11 { Standard Sequential Modules

 19

x 31 x 30 x0

CLK 31 30 0 Operand X
Clock
CTRL Action
2 Cycle

y 31 y 30 y0 1 Load,
clear carry FF

2-33 Add and shift

CLK 31 30 0 Operand Y

carry-in

FA
Result Z
carry-out sum
Q D 31 30 0
CLK
Q’ CTRL
z 31 z 30 z0

CLR

Figure 11.10: BIT-SERIAL ADDER.

Introduction to Digital Systems 11 { Standard Sequential Modules

 USES OF SHIFT REGISTERS: STATE REGISTER
20

sn (t + 1) = x(t)
1

si(t + 1) = si (t)
+1 for i = n 2; : : : ; 0

 FINITE-MEMORY SEQUENTIAL SYSTEM

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.2: SHIFT REGISTER AS STATE REGISTER
21

s (t + 1) = x(t)
7

si(t + 1) = si (t) for i = 6; : : : ; 0

+1

z (t) = x(t)s (t) 0

z(t)

x(t) x(t-8)
CTRL 8-bit SHIFT REGISTER

CLK
Figure 11.11: IMPLEMENTATION OF NETWORK IN Example 11.2

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.3: SHIFT REGISTER AS STATE REGISTER
22

8
if s(t) = 01101110 and x(t) = 1
z (t) = 01
><
>: otherwise

x
CTRL 8-BIT SHIFT REGISTER
CLK

z
Figure 11.12: IMPLEMENTATION OF NETWORK IN Example 11.3

Introduction to Digital Systems 11 { Standard Sequential Modules

 NETWORKS OF SHIFT REGISTERS
23

CTRL

CLK serial-in
8-BIT SHIFT 8-BIT SHIFT 8-BIT SHIFT 8-BIT SHIFT (left shift)
serial-in REGISTER REGISTER REGISTER REGISTER
(right shift) 7 0 7 0 7 0 7 0

serial-out serial-out
(left shift) (right shift)

Figure 11.13: NETWORK OF SERIAL-INPUT/SERIAL-OUTPUT SHIFT REGISTER MODULES

Introduction to Digital Systems 11 { Standard Sequential Modules

 COUNTERS
24

 MODULO-p COUNTER
s(t + 1) = (s(t) + x) mod p

(state/output) 1/1
s/z

1/0 1/0 1/0 p-1

0/0 1/1 2/2
/p-1

x/TC = 0/0 0/0 0/0 0/0

(input/terminal count)

Figure 11.14: STATE DIAGRAM OF A MODULO-p COUNTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 A HIGH-LEVEL DESCRIPTION OF A MODULO-p COUNTER
25

INPUT: x 2 f0; 1g
OUTPUTS: z 2 f0; 1; : : : ; p 1g
TC 2 f0; 1g
STATE: s 2 f0; 1; : : : ; p 1g
FUNCTION: STATE TRANSITION AND OUTPUT FUNCTIONS
s(t + 1) = (s(t) + x) mod p
z (t) = 8s(t)
>< 1 if s(t) = p 1 and x(t) = 1
TC (t) = >: 0 otherwise

Introduction to Digital Systems 11 { Standard Sequential Modules

 TYPES OF COUNTERS
26

 UP or DOWN COUNTERS

State Binary BCD Excess-3 Gray Ring Twisted Tail

0 000 0000 0011 000 00000001 0000
1 001 0001 0100 001 00000010 0001
2 010 0010 0101 011 00000100 0011
3 011 0011 0110 010 00001000 0111
4 100 0100 0111 110 00010000 1111
5 101 0101 1000 111 00100000 1110
6 110 0110 1001 101 01000000 1100
7 111 0111 1010 100 10000000 1000
8 1000 1011
9 1001 1100

Introduction to Digital Systems 11 { Standard Sequential Modules

 RING and TWISTED-TAIL COUNTERS
27

0 0 0 1

CLK xl
3 2 1 0
LOAD
x
(COUNT)
0 1 0 0 State = 2

(a) z3 z2 z1 z0
0 0 0 0

xl
CLK
3 2 1 0
LOAD
x
(COUNT)
0 0 1 1 State = 2
(b) z3 z2 z1 z0

Figure 11.15: a) MODULO-4 RING COUNTER; b) MODULO-8 TWISTED-TAIL COUNTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 BINARY COUNTER WITH PARALLEL INPUT
28

INPUTS: I = (I ; : : : ; I ); Ij 2 f0; 1g; I 2 f0; 1:::; 15g

3 0
CLR; LD; CNT 2 f0; 1g
STATE: s = (s ; : : : ; s ); sj 2 f0; 1g; s 2 f0; 1; :::; 15g
3 0
OUTPUT: s = (s ; : : : ; s ); sj 2 f0; 1g; s 2 f0; 1; :::; 15g
3 0
TC 2 f0; 1g
FUNCTION: STATE-TRANSITION AND OUTPUT FUNCTIONS
8>
>>
>>
0 if CLR = 1
s(t + 1) = I(s(t) + 1) mod 16
<
>>
if LD = 1
if CNT = 1 and LD = 0
>>
s(t) >:
otherwise
8>
if s(t) = 15 and CNT = 1
TC = 10 <
>: otherwise

Introduction to Digital Systems 11 { Standard Sequential Modules

 MODULO-16 COUNTER
29

Outputs
Clear

Terminal
S3 S2 S1 S0 CLR
count
Count enable
TC MODULO-16 CNT
COUNTER
CLK
I3 I2 I1 I0 LD

Load inputs

Inputs
Figure 11.16: A MODULO-16 BINARY COUNTER WITH PARALLEL INPUT

Introduction to Digital Systems 11 { Standard Sequential Modules

 MODULO-k COUNTER (1  k  16)
30

CNT = x
8
if (s = k 1) and (x = 1)
LD = 01
><
>: otherwise
I=0

TC = LD

Introduction to Digital Systems 11 { Standard Sequential Modules

 MODULO-k COUNTER (1  k  16)(cont.)
31

0/0

1/0
1/0 1/0
0 1 k-1 k 14 15

0/0 0/0 0/0 0/0 0/0 0/0

1/1
(a)

clear

S3 S2 S1 S0 CLR
CLK
MODULO-16 CNT x
State 9 10 11 0 1
COUNTER
CLK
I3 I2 I1 I0 LD LD(TC)
s0
s1
s3
0 0 0 0
TC (b)

a) STATE DIAGRAM OF MODULO-k COUNTER

Figure 11.17: (1  k  16); b) MODULO-12 COUNTER AND ITS TIME
BEHAVIOR (x = 1)

Introduction to Digital Systems 11 { Standard Sequential Modules

 a-to-b COUNTER (0  a; b  15) 32

CNT = x
8
if (s = b) and (x = 1)
LD = 01
><
>: otherwise
I=a

Introduction to Digital Systems 11 { Standard Sequential Modules

 33

1/0

1/0 1/0 1/0 1/0

0 a a+1 b b+1 14 15

0/0 0/0 0/0 0/0 0/0 0/0

0/0
1/1
(a)

clear

S3 S2 S1 S0 CLR

MODULO-16 CNT x (b)

COUNTER
CLK
I3 I2 I1 I0 LD

s2
s3
0 0 0 1
TC

Figure 11.18: a) STATE DIAGRAM OF a-to-b COUNTER; b) A 1-to-12 COUNTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 MODULO-k FREQUENCY DIVIDER (1  k  16)
34

CNT = x
8
if TC = 1
LD = 01 otherwise
><
>:

I = 16 k
z = TC

Introduction to Digital Systems 11 { Standard Sequential Modules

 35

1/0 1/0 1/0 clear

0 16-k 14 15
S3 S2 S1 S0 CLR

z TC MODULO-16 CNT x
0/0 0/0 0/0 0/0 COUNTER
1/1 CLK
I3 I2 I1 I0 LD

(a)

0 1 1 1

CLK

State 13 14 15 7 8 13 14 15 7

z(TC)

(b)

a) STATE DIAGRAM OF MODULO-k FREQUENCY DIVIDER; b) MODULO-9 FREQUENCY DIVIDER AND ITS
Figure 11.19:
TIME BEHAVIOR (x = 1)

Introduction to Digital Systems 11 { Standard Sequential Modules

 USES OF COUNTERS
36

 COUNT THE NUMBER OF TIMES THAT A CERTAIN EVENT TAKES

PLACE;

 CONTROL A FIXED SEQUENCE OF ACTIONS

 GENERATE TIMING SIGNALS

 GENERATE CLOCKS OF DIFFERENT FREQUENCIES

 STATE REGISTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 37

ENTRANCE
SENSOR UP
CLK COUNTER
EXIT DOWN
SENSOR MAX NUMBER
OF SPACES

COMPARATOR
> <

LOT FULL FREE SPACE

(a)

Sequence of actions:
CLEAR
0
0: CLEAR ALL REGISTERS 1 INPUT A

DECODER
COUNTER
modulo-6

BINARY
1: INPUT A 2 INPUT B
2: INPUT B 3
3: COMPUTE COMPUTE
4
4: COMPUTE
CLK 5 OUTPUT C
5: OUTPUT C

(b)

Figure 11.20: a) EXAMPLE OF EVENT COUNTER; b) EXAMPLE OF CONTROLLER.

Introduction to Digital Systems 11 { Standard Sequential Modules

 USES OF COUNTERS (cont.)
38

S Q TS0

0 R Q’ CLK0

Binary Counter
1 S0

BINARY DECODER

Modulo-4
CLK2
Binary Counter
S0 2
TS1
Modulo-8

S Q S1
S1 3
CLK4
4
S2 R Q’
5
6
CLK
7 S Q TS2

CLK
R Q’
CLK CLK0

7 0 1 2 3 4 5 6 7 0
State CLK2

TS0 CLK4

TS1
(b)

TS2
(a)

Figure 11.21: EXAMPLES OF NETWORKS FOR GENERATING a) TIMING SIGNALS; b) CLOCKS WITH DIFFERENT FREQUEN-
CIES.

Introduction to Digital Systems 11 { Standard Sequential Modules

 COUNTER AS STATE REGISTER
39

Counting s(t + 1) = (s(t) + 1) mod p

No change s(t + 1) = s(t)
Arbitrary s(t + 1) 6= (s(t) + 1) mod p and s(t + 1) 6= s(t)

Output
Combinational z
Network

s
n
CLK
n
Modulo- 2
Combinational
CNT Counter
Network for
x CNT(Count)
LD
n I

Combinational Combinational
Network for Network for
LD(Load) Parallel Inputs

Figure 11.22: IMPLEMENTATION OF SEQUENTIAL SYSTEM WITH COUNTER AND COMBINATIONAL NETWORKS.

Introduction to Digital Systems 11 { Standard Sequential Modules

 COUNTER AS STATE REGISTER (cont.)
40

8
if s(t + 1) = (s(t) + 1) mod p and x = 1
CNT = 01 otherwise
><
>:
8
1 if s(t + 1) 6= s(t) and
>>
><
LD = 6 (s(t) + 1) mod p and x = 1
s(t + 1) = >>
0 otherwise >:
8
I = s(t + 1) ifotherwise
LD = 1
><
>:

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.4
41

a’/0

S0

a/0 b/0

S1 S6
b’/0

-/0
-/0

S2 c/0 S5

-/0 c’/0

b’/1 S3 S4
b/0

Figure 11.23: STATE DIAGRAM for Example 11.4

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.4 (cont.)
42

CNT = S a S S S b S c0 S
0 1 2 3 4 5

LD = 8>CNT 0
>> (0; 0; 0; 0) if S a0 S b
0 6
(I ; I ; I ; I ) = <>> (0; 0; 0; 1)
3 2 1 0 if S c S b0
4 6
>: (0; 0; 1; 1) if S b03

SWITCHING EXPRESSIONS FOR PARALLEL INPUTS

I 3 = 0
I 2 = 0
I 1 = Q 0

I 0 = Q Q Q0 Q b0
0 2 1 2

OUTPUT z
z = Q Q b0
1 0

Introduction to Digital Systems 11 { Standard Sequential Modules

 43

Q Q Q Q
3 2 1 0
a 0

1 1

1 2 CK
Modulo- 16
b 3 CNT Counter
MUX
c’ 4
LD I I I I
1 5 3 2 1 0

0 6
0 0
d.c. 7
2 1 0

Q Q Q
2 1 0

Q
1
Q z
0
b’
Q b’ Q 2 Q’
0 1

Figure 11.24: SEQUENTIAL NETWORK FOR Example 11.4

Introduction to Digital Systems 11 { Standard Sequential Modules

 NETWORKS OF COUNTERS
44

 CASCADE COUNTERS
8
>< 1 if (s = p 1) and (CNT = 1)
TC = >: 0 otherwise

 FOR THE i-th MODULE

8
>>
>< 1 if (s j = p 1) and (x = 1)
( )

CNT i = >> ( for all j < i)

>:
0 otherwise
where s(j) is the state of counter j .

Introduction to Digital Systems 11 { Standard Sequential Modules

 CASCADE COUNTERS (cont.)
45

TC Q CNT TC Q CNT TC Q CNT x

k-1 k-2 0
I LD I LD I LD

CLK
LOAD

Figure 11.26: CASCADE IMPLEMENTATION OF A MODULO-pk COUNTER

 THE WORST-CASE DELAY

T = (k 1)ttc + tsu + tp
worst case

 THE MAXIMUM CLOCK FREQUENCY POSSIBLE

fmax = 1=[(k 1)ttc + tsu + tp]

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.5
46

tsu = 4:5[ns] (including the delay of the gates used

to produce the inputs to the cells)
tp = 2[ns]
ttc = 3:5[ns]

MIN CLOCK PERIOD:

with one module T = 6:5[ns] (153[MHz ])
with 8 modules T = 31[ns] (32[MHz ])

Introduction to Digital Systems 11 { Standard Sequential Modules

 FASTER COUNTERS
47

 INTRODUCE CEF (Count Enable First)

8
s(t + 1) = s(s(t()t) + 1) mod p if CEF = 1 and CNT = 1
><
>: otherwise

 TC SIGNAL NOT INFLUENCED BY CEF ,

8
>< 1 if (s(t) = p 1) and (CNT = 1)
TC = >: 0 otherwise

Introduction to Digital Systems 11 { Standard Sequential Modules

 FASTER CASCADE COUNTER
48

Q CEF Q CEF Q CEF Q CEF 1

k-1 CNT TC k-2 CNT TC 1 CNT TC 0 CNT x
I LD I LD I LD I LD
"1"
LOAD
CLK

Figure 11.27: A FASTER VERSION OF A CASCADE COUNTER

Introduction to Digital Systems 11 { Standard Sequential Modules

 WORST-CASE DELAY
49

Tworst case = (k 2)ttc + tsu + tp

) SMALL REDUCTION IN THE DELAY
* Note: propagation of TC can span several clock cycles

CONSEQUENTLY, IF T IS THE CLOCK PERIOD,

pT  (k 2)ttc + tsu + tp
T  ttc + tsu + tp
COMBINING
T  max(ttc + tsu + tp; ((k 2)ttc + tsu + tp)=p)

Introduction to Digital Systems 11 { Standard Sequential Modules

 50
p-2 p-1 0 1
Q (0)

p-1 0
Q (1)

p-1 0
Q (k-2)

TC (0)
tp

CNT (k-1)
Time available to propagate TC t su

r r+1
Q (k-1)

(a)

p-2 p-1 0 1 2 p-2 p-1 0 1 2

Q (0)

p-2 p-1 0
Q (1)

TC (0)
= CEF

TC (1)

CNT (k-1)
tp t su

Time available to propagate TC

r r+1
Q (k-1)

(b)

Figure 11.28: TIMING RELATIONS: a) Without CEF ; b) With CEF

Introduction to Digital Systems 11 { Standard Sequential Modules

 PARALLEL COUNTERS
51

Modulo-504 counter: 7  8  9 states

000; 111; 222; 333; 444; 555; 666; 077; 108; 210; 321; 432; :::

Introduction to Digital Systems 11 { Standard Sequential Modules

 PARALLEL MODULO-(7  8  9) COUNTER
52

x CNT
Modulo-7
Modulo-(7x8x9)
COUNTER COUNTER

CNT
Modulo-8
COUNTER
CLK

CNT
Modulo-9
COUNTER

Figure 11.29: PARALLEL IMPLEMENTATION OF MODULO-(7  8  9) COUNTER.

Introduction to Digital Systems 11 { Standard Sequential Modules

 MULTIMODULE SYSTEMS
53

 Complex sequential system ) several interacting sequential subsystems

Example 11.6: BLOCK PATTERN RECOGNIZER

 INPUT SEQUENCE: blocks of k symbols

 FUNCTION: check for pattern P in each block
 IMPLEMENTATION: counter + recognizer
 OUTPUT OF THE COUNTER:
8
>< 1 if t mod k = k 1 and check = 1
TC (t) = >: 0 otherwise
 OUTPUT OF THE SYSTEM: z(t) = p(t)
TC (t)

Introduction to Digital Systems 11 { Standard Sequential Modules

 54

INITIALIZE

MODULO - k TC
check
COUNTER

z(t)

PATTERN
x(t)
RECOGNIZER p

CLK

(a)

Figure 11.30: BLOCK PATTERN RECOGNIZER

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.6: ILLUSTRATION
55

t 0 1 2 3 4 5 6 7 8 9 10 11
x 5 3 7 4 1 0 3 7 4 3 7 4
TC 0 0 1 0 0 1 0 0 1 0 0 1
p 0 0 0 1 0 0 0 0 1 0 0 1
z 0 0 0 0 0 0 0 0 1 0 0 1

Introduction to Digital Systems 11 { Standard Sequential Modules

 Example 11.7
56

 count the number of instances of pattern P in blocks of k symbols

INITIALIZE

MODULO - k TC
check
COUNTER

z(t) MODULO - N
COUNTER

PATTERN
x(t)
RECOGNIZER p
Count
of instances of P

CLK
(b)

Figure 11.30: BLOCK PATTERN RECOGNIZER.

Introduction to Digital Systems 11 { Standard Sequential Modules