CONTENTS

1. SAFETY PRECAUTIONS……………………………………………………… .. 1
1.1 GENENRAL GUIDELINES……………………………………………………… .. 1
2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD) TO ELECTROSTATICALLY
SENSITIVE(ES) DEVICES………………………………………………………. 1
3. PRECAUTION OF LASTER DIODE……………………………………………. 2
4. GENERAL DESCRIPTION……………………………………………………… 3
5. PREVENTION OF STATIC ELECTRICITY DISCHARGE…………………… .. 5
5.1 GROUNDING FOR ELECTROSTATIC BREAKDOWN PREVENTION……… 5
5.1.1 WORKTABLE GROUNDING…………………………………………………… 5
5.1.2 HUMAN BODY GROUNDING…………………………………………………. 5
5.1.3 HANDING OF OPTICAL PICKUP……………………………………………… 5
5.2 HANDING PRECAUTIONS FOR TRAVERSE UNIT(OPTICAL PICKUP).. 5
6. ASSENBLING AND DISASSEMBLING THE MECHANISM UNIT…… .. 6
6.1 DISASSEMBLY PROCEDURE………………………………………………… 6
6.2 TERMINAL P.C.B………………………………………………………………. 6
6.3 CLAMP PLATE UNIT………………………………………………………… .. 7
6.4 TRAY…………………………………………………………………………… 7
6.5 TRAVERSE BLOCK…………………………………………………………… 8
6.6 TRAVERSE GEAR……………………………………………………………… 8
6.7 OPTICAL PICKUP UNIT……………………………………………………… 9
6.7.1 PRECAUTIONS IN OPTICAL PICKUP REPLACEMENT…………………… 9
6.8 DISASSEMBLING THE MIDDLE CHASSIS…………………………………. 11
6.9 DISASSENBLING THE TRAVERSE GRAR A……………………………… ... 11
6.10 DISASSEMBLING THE SPINDLE MOTOR UNIT…………………………… 11
7 Electrical Confirmation………………………………………………………… .. 12
7.1 VIDEO OUTPUT(LUMINANCE SIGNAL) CONFIRMATION………………… 12
7.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION……………. 13
8. MPEG CHECK WAVEFORM 14
9 IC BLOCK DIAGRAM & DESCRIPTION………………………………… .. 16
10 BLOCK DIAGRAM…………………………………………………………… 35
11 SCHEMATIC & PCB WIRING DIATRAM....................................................................36
12 EXPODED VIEWS……………………………………………………………. 48
13. SPARE PARTS LIST.................................................................................. 51
13. SPARE PARTS LIST.................................................................................. 55
1.SAFETY PRICAUTIONS
1.1 GENERAL GUIDELINES
1.When servicing,observe the original lead dress.ifa short circuit is found,replace all parts which have
been overheated or damaged by the short circuit.
2.After servicing,see to it that all the protective devices such as insulation bamiers,insulation papers
shields are properly installed.
3.After servicing,make the following leakage current checks to prevent the customer from being exposed
to thock hazards.
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD) TO ELECTROSTATECALLY
　ＳＥＮＳＩＴＩＶＥ（ＥＳ）　ＤＥＶＩＣＥＳ
Some semiconductor(solid state)devices can be damaged easily by static electricity.Such components
commonly are called Electrostatically Sensitive(ES)Devices.Examples of typical ES devices are integrated
circuits and some field-effect transistorsand semiconductor chip components.The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1.Immediately before handling any semiconductor component or semiconductor-equipped assembly,drain
off any ESDon your body by touching a known earth ground.Alteatively,obtain and wear a commercially
availabel discharging ESD wrist strap,which should be removed for potential shock reasons prior to
applying power to the unit under test.
2.After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil,to prevent electrostatic charge buildup or exposure of the assembly.
3.Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4.Use only an anti-static solder removal device.Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5.Do not use freon-propelled chemicals.These can generate electrical charges sufficient to damage ES
devices.
6.Do not remove a replacement ES device from its protective package until immediately before you are
ready to install if.(Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam,alminum foil or comparable conductive material).
7.Immediately before removing the protective material from the leads of a aeplacement ES device,touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit,and observe all other safety precautions.
8.Minimize bodily motions when handling unpackaged replacement ES devices.(Otherwise hamless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD)

1
3. Precaution of L aster Diode

２
4.GENERAL DESCRIPTION
4.1

DVD-AB908S
OPEN CLOSE PLAY PAUSE STOP

ON
POWER
OFF 1

DVD / Super VCD / VCD / CD / MP3 PLAYER

1 MIC 2 1 VOL 2
REV FWD

3
4.2

EJECT AUDIO SUBTITLE OSD

36
2 35
GOTO L/R ANGLE MUTE
3 34

4 33
1 2 3

4 5 6
5

7 8 9

6 32
CLEAR
0 ENTER

TITLE MENU

7 31

8
SELECT 30

SETUP REALSONIC

9 29
SING READ MANUAL AUTO DIGEST

10 28
11 STOP PLAY PAUSE STEP 27

12 26

13 REV FWD SKIP

14 25

15
P/N A-B REPEAT RETURN
24

16 ZOOM SLOW PROG REMAIN

23
17 22
18 21
19 20

4
5.PREVERTION OF STATIC ELECTRICITY DISCHARGE
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human body.
Use due caution to electrostatic breakdown when servicing and handling the laser diode.
5.1.Grounding for electrostatic breakdown prevention
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged by
static electricity in the working environment.Proceed servicing works under the working environment where grounding
works is completed.
5.1.1. Worktable grounding
1.Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the sheeet.

5.1.2.Human body grounding

1 Use the anti-static wrist strap to discharge the static electricity form your body.

safety_3 (1577x409x2 tiff)

5.1.3.Handing of optical pickup

1.To keep the good quality of the optical pickup maintenance parts during transportation and before
installation,the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure.(See this Technical Guide).
2.Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.

5.2.Handing precautions for Traverse Unit (Optical Pickup)

1.Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2.When replacing the optical pickup,install the flexible cable and cut is short land with a nipper.See the
optical pickup replacement procedure in this Technical Guide.Before replacing the traverse unit,remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
3.The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
4.The half-fixed resistor for laser power adjustment cannot be adjusted.Do not turn the resistor.

5
6.ASSEMBLING AND DISASSENBLING THE MECHANISM UNIT
6.1Disassembly Procedure

6.2 Terminal P.C.B.

1.Unscrew the screws.
2.Remove the solders.
3.Remove the connectors

6
6.3 Clamp Plate Unit
1.Spread the stopper with hand to silde the tabs and remove the clamp plate unit.

6.4 Tray
1.Lift the tray.

7
6.5 Traverse Block
1.Lift the traverse block while spreading the hook of the mechanical chassis chassis unit.
2.Disengage the tabs from the holes of the mechanical chassis unit.

6.6. Traverse Gear

1.Disengage the tabs from the traverse gear
2.Remove the traverse gears B and C.

8
 5.6 Mechanism Unit
1.Unscrew the screws.
2.Remove the connectors.

6.7. Optical Pickup Unit

1. Unscrew the screws.
5.7 Terninal P.C.B.
2.Remove the spring holders and the springs.
3.Pull out of the
1.Unscrew the screws
drive shaft and guide shaft.
2.Remove the solders.
3.Remove the connectors.

6.7.1. Precautions in optical pickup replacement

9
The optical pickup can be damaged by static electricity from you body.Be sure to take static electricity countermeasures
when working around the optical pickup.(Refer to the related page in this Manual about the countermeasures.
1.Do not touch laser diode,actuator and their peripheries.
2.Do not use tester to check laser diode.(Laser diode can be damaged easily.)
3.The use of soldering iron with anti-static feature is recommended when providing short-circuit to laser diode or when
removing it.
4.Solder the land on flexible cable of optical pickup unit.

-When using the soldering iron without anti-static feature,short-circuit the flexible cable terminal with a clip before
short-circuiting the land.

-After intended repair is finished.remove the solder for short-circuit of laser diode in a correct way following the

procedures described in this Manual.

10
6.8. Disassenbling the Middle Chassis
1.Remove the holders pins.
2.Remove the tab.
3.It lifts while pulling it in the direction of the arrow.

6.9. Disassenbling the Traverse Gear A

1.Remove the traverse gear A.

11
 6.10. Disassembling the Sprindle Motor Unit
1.Remove the floating rubbers.

7. Electrical Confirmation
7.1. Video Output (Luminance Signal) Confirmation
DO this confirmation after replacing a P.C.B.
Measurement point Mode Disc

Color bar 75% DVDT-S15

Video output terminal PLAY(Title 46):DVDT-S15 or
PLAY(Title 12):DVDT-S01 DVDT-S01

Measuring equipment,tools Confirmation value

200mV/dir,10 sec/dir 1000mVp-p±30mV

Purpose:To maintain video signal output compatibility.

1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV

１２
7.2. Video Output (Chrominance Signal) Confirmation

Do the confirmation after replacing P.C.B.

Measurement point Mode Disc

Color bar 75% DVDT-S15

Video output terminal PLAY(Title 46):DVDT-S15 or
PLAY(Title 12):DVDT-S01 DVDT-S01

Measuring equipment,tools Confirmation value

Screwdriver,Oscilloscope
200mV/dir,10 sec/dir 621mVp-p±30mV
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV

13
8. MPEG BOARD CHECK WAVEFORM

1.X204 WAVEFORM DIAGRAM

2.ZIVA-4.1 PIN.173/STRMCS WAVEFORM DIAGRAM

14
3.IC5L0380R PIN.2 WAVEFORM DIAGRAM

4.VIDEO OUPUT WAVEFORM DIAGRAM

15
5.ZIVA-4.1PIN.172/DVDREQ WAVEFORM DIAGRAM

16
9. IC BLOCK DIAGRAM & DESCRIPTION
IC U217 ZIVA-4.1
1 Typical ZiVA-4.1 DVD Decoder Application SDRAM

Video Out
Front-End
Loader
Chip Set

ZiVA-4.1
2/6/2+6
2/6/2+6 Channel Channel
Audio DAC Out
ROM
0220c

Host Digital Audio Input

RAM

2 General Description
The ZiVA-4.1 DVD Decoder is the fourth generation in
C-Cube’s ZiVA family of highly integrated,high-performance
DVD decodersfor the consumer DVD player market.
The ZiVA-4.1 maintains the same high-level application pro-
gram ni terface (API) asearlier decoders. Therefore,system
host codedeveloped forprevious products is fully compati-
ble with the ZiVA-4.1 API. This compatibility preserves soft-
ware investment ni designsand will be maintained n i future
generations of the decoder fami ly. Figure 2shows the data
flow of the ZiVA-4.1 Decoder.

SDRAM Memory
Interface OSD
Controller Decoder

Digital
Subpicture Video Video
Video
Host Decoder Mixer Out
Host Encoder
Interface
Interface
Control Logic MPEG V
ideo
Decoder
SecureView
CSS CD-DA and LPCM
Descrambling Program Decoder
DVD/CD Stream
Interface Bus Key Decoder Dolby Digital Audio Digital Audio
Audio
Authentication Decoder Audio Interface
DSP
(optional) Interface
MPEG Audio
Decoder
0221d

Figure 2 ZiVA-4.1 DVD Decoder Dat

a Flow Diagram
Digital Audio Input

17
IC BLOCK DIAGRAM & DESCRIPTION
3 Pin Descriptions
The ZiVA-4.1 decoder is packaged in a 208-pin Plastic Quad Flat Pack (PQFP) package. Figure 3 shows the
pin-out and Table 1
lists the pin number, pin name, and I/O voltage and I/O type.

CVBS + sync
VDD_ VIDEO
VDD_VIDEO

VDD_VIDEO

VDD_VIDEO
VSS_VIDEO

VSS_VIDEO

VSS_VIDEO

VSS_VIDEO

RESERVED
RESERVED
RESERVED

RESERVED

RESERVED
VDD_RREF

VSS_RREF

DA-DATA0
DA-DATA1
DA-DATA2
DA-DATA3
VDD_DAC

VDD_DAC

VDD_DAC

VDD_DAC

DAI-DATA
VSS_DAC

VSS_DAC

VSS_DAC

VSS_DAC

DAI-LRCK
CVBS/G/Y

DA-LRCK

DAI-BCK
VDD_2.5

VDD_3.3

VDD_3.3
DA-BCK
DA-XCK
DA-IEC
Y/B/U
C/R/V
RREF

VSS

VSS

VSS
NC

NC

NC

NC

NC

NC
NC
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
A_VSS 157 104 MADDR3
SYSCLK 158 103 MADDR2
VCLK 159 102 MADDR1
A_VDD 160 101 VSS
DVD-DATA0/CD-DATA 161 100 VDD_3.3
DVD-DATA1/CD-LRCK 162 99 MADDR0
DVD-DATA2/CD-BCK 163 98 MADDR10
DVD-DATA3/CD-C2P0 164 97 SD-BS
DVD-DATA4/CDG-SDATA 165 96 SD-CS1/MADDR11
VSS 166 95 SD-CS0
VDD_3.3 167 94 SD-RAS
DVD-DATA5/CDG-VFSY 168 93 VSS
DVD-DATA6/CDG-S0S1 169 92 VDD_3.3
DVD-DATA7/CDG-SCLK 170 91 SD-CAS
VDACK 171 90 MWE
VREQUEST 172 89 MADDR4
VSTROBE 173 88 VSS
ERROR 174 87 VDD_2.5
VDD_3.3 175 86 MADDR5
RESERVED 176 85 MADDR6
VDD_3.3 177 84 MADDR7
VSS 178 83 VSS
NC 179 82 VDD_3.3
NC 180 81 MADDR8
NC
HADDR0
181
182
ZiVA-4.1 Decoder 80
79
MADDR9
CLKSEL
HADDR1
HADDR2
183
184
Top View 78
77
SD-CLK
LDQM
RESERVED 185 76 MDATA8
RESERVED 186 75 VSS
RESERVED 187 74 VDD_3.3
VSS 188 73 MDATA9
VDD_2.5 189 72 MDATA10
RESERVED 190 71 MDATA11
VSS 191 70 MDATA12
VDD_3.3 192 69 MDATA13
RESERVED 193 68 VSS
RESERVED 194 67 VDD_2.5
RESERVED 195 66 MDATA14
RESERVED 196 65 VSS
HDATA7 197 64 VDD_3.3
VSS 198 63 MDATA15
HDATA6 199 62 MDATA7
HDATA5 200 61 MDATA6
HDATA4 201 60 MDATA5
HDATA3 202 59 MDATA4
HDATA2 203 58 MDATA3
VDD_3.3 204 57 MDATA2
VSS 205 56 VSS
HDATA1 206 55 VDD_3.3
HDATA0 207 54 MDATA1
CS 208 53 MDATA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
VDD_3.3
WAIT*

VDD_3.3
INT*

VDD_2.5

VDD_3.3
VDATA0
VDATA1
VDATA2
VDATA3
VDATA4
VDATA5
VDATA6
VDATA7

VDD_3.3

VDD_2.5

PIO0

VDD_3.3
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7
RD

RESERVED
RESERVED
RESERVED

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VSS

NC
NC
NC
NC

VSS
NC
NC
NC
NC
VSS

VSYNC
HSYNC
VSS

VSS

VSS
RESET
R/W

* These pins must be pulled up to 3.3 volts through an external 4.7K resistor

18
IC BLOCK DIAGRAM & DESCRIPTION

Table 1 ZiVA-4.1 Decoder Pin List Table 1 ZiVA-4.1 Decoder Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type Pin No. Pin Name I/O Voltage I/O Type
1 RD 3.3V I 49 PIO4 3.3V I/O
2 R/W 3.3V I 50 PIO5 3.3V I/O
3 VDD_3.3 3.3V — 51 PIO6 3.3V I/O
4 WAIT 3.3V O, OD, PU 52 PIO7 3.3V I/O
5 RESET 3.3V I 53 MDATA0 3.3V I/O
6 VSS GROUND — 54 MDATA1 3.3V I/O
7 VDD_3.3 3.3V — 55 VDD_3.3 3.3V —
8 INT 3.3V O, OD, PU 56 VSS GROUND —
9 NC No Connect O 57 MDATA2 3.3V I/O
10 NC No Connect O 58 MDATA3 3.3V I/O
11 NC No Connect O 59 MDATA4 3.3V I/O
12 NC No Connect O 60 MDATA5 3.3V I/O
13 VDD_2.5 2.5V — 61 MDATA6 3.3V I/O
14 VSS GROUND — 62 MDATA7 3.3V I/O
15 NC No Connect O 63 MDATA15 3.3V I/O
16 NC No Connect O 64 VDD_3.3 3.3V I/O

E
17 NC No Connect O 65 VSS GROUND I/O
18 NC No Connect O 66 MDATA14 3.3V I/O
19
20
VSS
VDD_3.3
GROUND
3.3V
—
—
C 67
68
VDD_2.5
VSS
2.5V
GROUND
—
—
N
21 VDATA0 3.3V O 69 MDATA13 3.3V I/O
22 VDATA1 3.3V O 70 MDATA12 3.3V I/O
A
23 VDATA2 3.3V O 71 MDATA11 3.3V I/O
24 VDATA3 3.3V O 72 MDATA10 3.3V I/O
DV

25 VDATA4 3.3V O 73 MDATA9 3.3V I/O

26 VDATA5 3.3V O 74 VDD_3.3 3.3V —
27 VDATA6 3.3V O 75 VSS GROUND —
A

28 VDATA7 3.3V O 76 MDATA8 3.3V I/O

29 VSYNC 3.3V I/O 77 LDQM 3.3V O
30 HSYNC 3.3V I/O 78 SD-CLK 3.3V O
31 VSS GROUND — 79 CLKSEL 3.3V I
32 VDD_3.3 3.3V — 80 MADDR9 3.3V O
33 RESERVED 3.3V I 81 MADDR8 3.3V O
34 RESERVED 3.3V I 82 VDD_3.3 3.3V —
35 RESERVED 3.3V I 83 VSS GROUND —
36 VDD_2.5 2.5V — 84 MADDR7 3.3V O
37 VSS GROUND — 85 MADDR6 3.3V O
38 RESERVED 3.3V I 86 MADDR5 3.3V O
39 RESERVED 3.3V I 87 VDD_2.5 2.5V —
40 RESERVED 3.3V I 88 VSS GROUND —
41 RESERVED 3.3V I 89 MADDR4 3.3V O
42 RESERVED 3.3V I 90 MWE 3.3V O
43 PIO0 3.3V I/O 91 SD-CAS 3.3V O
44 VSS GROUND — 92 VDD_3.3 3.3V —
45 VDD_3.3 3.3V — 93 VSS GROUND —
46 PIO1 3.3V I/O 94 SD-RAS 3.3V O
47 PIO2 3.3V I/O 95 SD-CS0 3.3V O
48 PIO3 3.3V I/O 96 SD-CS1/MADDR11 3.3V O

19
IC BLOCK DIAGRAM & DESCRIPTION

Table 1 ZiVA-4.1 Decoder Pin List (Continued) Table 1 ZiVA-4.1 Decoder Pin List (Continued)

Pin No. Pin Name I/O Voltage I/O Type Pin No. Pin Name I/O Voltage I/O Type
97 SD-BS 3.3V O 144 VSS_VIDEO ANALOG GND —
98 MADDR10 3.3V O 145 Y/B/U 3.3V ANALOG O
99 MADDR0 3.3V O 146 VDD_DAC 3.3V ANALOG —
100 VDD_3.3 3.3V — 147 VDD_VIDEO 3.3V ANALOG —
101 VSS GROUND — 148 NC No Connect O
102 MADDR1 3.3V O 149 VSS_DAC ANALOG GND —
103 MADDR2 3.3V O 150 VSS_VIDEO ANALOG GND —
104 MADDR3 3.3V O 151 C/R/V 3.3V ANALOG O
105 RESERVED ANALOG GND — 152 VDD_DAC 3.3V ANALOG —
106 NC No connect O 153 VDD_VIDEO 3.3V ANALOG —
107 NC No connect O 154 VSS_RREF ANALOG GND —
108 RESERVED 3.3V I 155 RREF 3.3V ANALOG O
109 NC No connect O 156 VDD_RREF 3.3V ANALOG —
110 RESERVED 3.3V I 157 A_VSS GROUND —
111 RESERVED 3.3V ANALOG — 158 SYSCLK 3.3V I
112 RESERVED 3.3V I 159 VCLK 3.3V I

E
113 DAI-LRCK 3.3V I/O 160 A_VDD 3.3V ANALOG —
114 DAI-BCK 3.3V I/O 161 DVD-DATA0/CD-DATA 3.3V I
115
116
VDD_3.3
VSS
3.3V
GROUND
—
—
C 162
163
DVD-DATA1/CD-LRCK
DVD-DATA2/CD-BCK
3.3V
3.3V
I
I
N
117 DAI-DATA 3.3V I/O 164 DVD-DATA3/CD-C2P0 3.3V I
118 DA-DATA3 3.3V O 165 DVD-DATA4/CDG-SDATA 3.3V I
A
119 DA-DATA2 3.3V O 166 VSS GROUND —
120 DA-DATA1 3.3V O 167 VDD_3.3 3.3V —
DV

121 DA-DATA0 3.3V O 168 DVD-DATA5/CDG-VFSY 3.3V I

122 DA-LRCK 3.3V O 169 DVD-DATA6/CDG-S0S1 3.3V I
123 VDD_3.3 3.3V — 170 DVD-DATA7/CDG-SCLK 3.3V I
A

124 VSS GROUND — 171 VDACK 3.3V I

125 DA-XCK 3.3V I/O 172 VREQUEST 3.3V O
126 DA-BCK 3.3V O 173 VSTROBE 3.3V I
127 DA-IEC 3.3V O 174 ERROR 3.3V I
128 VDD_2.5 2.5V — 175 VDD_3.3 3.3V —
129 VSS GROUND — 176 RESERVED GROUND —
130 NC No Connect O 177 VDD_3.3 3.3V —
131 VSS_DAC ANALOG GND — 178 VSS GROUND —
132 VSS_VIDEO ANALOG GND — 179 NC No connect O
133 CVBS + sync 3.3V ANALOG O 180 NC No connect O
134 VDD_DAC 3.3V ANALOG O 181 NC No connect O
135 VDD_VIDEO 3.3V ANALOG — 182 HADDR0 3.3V I
136 NC No Connect O 183 HADDR1 3.3V I
137 VSS_DAC ANALOG GND — 184 HADDR2 3.3V I
138 VSS_VIDEO ANALOG GND — 185 RESERVED 3.3V I
139 CVBS/G/Y 3.3V ANALOG O 186 RESERVED 3.3V I
140 VDD_DAC 3.3V ANALOG — 187 RESERVED 3.3V I
141 VDD_VIDEO 3.3V ANALOG — 188 VSS GROUND —
142 NC No Connect O 189 VDD_2.5 2.5V —
143 VSS_DAC ANALOG GND — 190 RESERVED 3.3V I

20
IC BLOCK DIAGRAM & DESCRIPTION

Table 1 ZiVA-4.1 Decoder Pin List (Continued) Table 1 ZiVA-4.1 Decoder Pin List (Continued)

Pin No. Pin Name I/O Voltage I/O Type Pin No. Pin Name I/O Voltage I/O Type
191 VSS GROUND — 199 HDATA6 3.3V I/O
192 VDD_3.3 3.3V — 200 HDATA5 3.3V I/O
193 RESERVED 3.3V I 201 HDATA4 3.3V I/O
194 RESERVED 3.3V I 202 HDATA3 3.3V I/O
195 RESERVED 3.3V I 203 HDATA2 3.3V I/O
196 RESERVED 3.3V I 204 VDD_3.3 3.3V —
197 HDATA7 3.3V I/O 205 VSS 3.3V —
198 VSS GROUND — 206 HDATA1 3.3V I/O
207 HDATA0 3.3V I/O
208 CS 3.3V I
Note: The ZiVA-4.1 core operates at 2.5V ± 10%. Most I/O interface pins can be interfaced with 3.3-V or 5-V devices depending on the voltage applied to the VDD pins associated
with them. Refer to the Application Note for more information.

Signal Descriptions
Table 2 provides the pin name, pin number, type, and description of each signal.

Table 2 ZiVA-4.1 DVD Pin Descriptions

E
Name Pin No. Type1 Description
RESET 5
C I Active Low Reset. Assert for at least 5-milliseconds in the presence of clock to
reset the entire chip
N
SYSCLK 158 I Optional System Clock. Tie to A_VDD through a 1K Ohm resistor
CLKSEL 79 I Selects SYSCLK or VCLK as clock source. Normal operation is to tie HIGH.
System Services

A
VCLK 159 I System clock that drives internal PLLs and internal DENC. ZiVA-4 requires an
external 27-MHz TTL oscillator.
DV

PIO[7:0] 52-46, 43 I/O Programmable I/O pins.

NC 181-179, 148, 142, 136, 130, 109, 107, O No connect.
106, 18-15, 12-9
RESERVED 196-193, 190, 187-185, 176, 112, 111, 110, I Tie to VSS or VDD_3.3 as specified in Table 1.
A

108, 105, 42-38, 35-33

VDD_3.3 3, 7, 20, 32, 45, 55, 64, 74, 82, 92, 100, 115, Power 3.3-V supply voltage for I/O signals.
123, 167, 175, 177, 192, 204
VDD_2.5 13, 36, 67, 87, 128, 189 Power 2.5-V supply voltage for core logic
VDD_VIDEO 135, 141, 147, 153 Power 3.3-V Analog Video Power
Power and Grounds

VDD_DAC 134, 140, 146, 152 Power Analog Video DAC Power
A_VDD 160 Power 3.3-V Analog PLL Power
VDD_RREF 156 Power 3.3V Analog Video Power
VSS 6, 14, 19, 31, 37, 44, 56, 65, 68, 75, 83, 88, Ground Ground for core logic and I/O signals
93, 101, 116, 124, 129, 166, 178, 188, 191,
198, 205
VSS_VIDEO 132, 138, 144, 150 Ground Analog Video Ground
VSS_DAC 149, 143, 137, 131 Ground Analog Video DAC Ground
A_VSS 157 Ground Analog PLL Ground
VSS_RREF 154 Ground Video Analog Ground

21
IC BLOCK DIAGRAM & DESCRIPTION

Table 2 ZiVA-4.1 DVD Pin Descriptions (Continued)

Name Pin No. Type1 Description

CS 208 I Host chip select. Host asserts CS to select the decoder for a read or write oper-
ation. The falling edge of this signal triggers the read or write operation.
HADDR[2:0] 184-182 I Host address bus. 3-bit address bus selects one of eight host interface registers.
HDATA[7:0] 197, 199-203, 206, 207 I/O HDATA[7:0] is the 8-bit bi-directional host data bus through which the host
writes data to the decoder Code FIFO. MSB of the 32-bit word is written first.
The host also reads and writes the decoder internal registers and local
Host Interface

SDRAM/ROM via HDATA[7:0].

INT 8 O, OD, PU Host interrupt. Open drain signal, must be pulled-up via 4.7kΩ to 3.3 volts.
Driven high for 10 ns before tristate.
RD 1 I Read strobe in I mode. Must be held HIGH in M Mode.
R/W 2 I Read/write strobe in M mode. Write strobe in I mode. Host asserts R/W LOW
to select Write and LOW to select Read for M Mode only.
WAIT 4 O, OD, PU Transfer not complete / data acknowledge. Active LOW to indicate host initiated
transfer is not complete. WAIT is asserted after the falling edge of CS and reas-
serted when decoder is ready to complete transfer cycle. Open drain signal,
must be pulled-up via 1kΩ to 3.3 volts. Driven high for 10 ns before tristate.
DVD-DATA7/CDG-SCLK 170 I DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Clock indicat-
ing subcode data clock input or output.
DVD-DATA6/CDG-S0S1 169 DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Block Sync

E
indicating block-start synchronization input.
DVD-DATA5/CDG-VFSY 168 DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) Frame Sync

DVD-DATA4/CDG-SDATA 165
C indicating frame-start or composite synchronization input.
DVD parallel compressed data from DVD DSP. Or CD+G (Subcode) data indicat-
N
Parallel DVD/CD or Serial CD Interface

ing serial subcode data input.

DVD-DATA3/CD-C2P0 164 I Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid pic-
A
ture on-screen until the next valid picture is decoded. This pin is shared with
DVD compressed data DVD-DATA3.
DV

DVD-DATA2/CD-BCK 163 I CD bit clock. Decoder accept multiple BCK rates. This pin is shared with DVD
compressed data DVD-DATA2.
DVD-DATA1/CD-LRCK 162 I Programmable polarity 16-bit word synchronization to the decoder (right chan-
nel HIGH). This pin is shared with DVD compressed data DVD-DATA1.
A

DVD-DATA0/CD-DATA 161 I Serial CD data. This pin is shared with DVD compressed data DVD-DATA0.
ERROR 174 I Error in input data. If ERROR signal is not available from the DSP it must be
grounded.
VDACK 171 I In synchronous mode, bitstream data acknowledge. Asserted when DVD data is
valid. Polarity is programmable.
VREQUEST 172 O Bitstream request. Decoder asserts VREQUEST to indicate that the bitstream
input buffer has available space. Polarity is programmable.
VSTROBE 173 I Bitstream strobe. Programmable dual mode pulse. Asynchronous and synchro-
nous. In Asynchronous mode, an external source pulses VSTROBE to indicate
data is ready for transfer. In synchronous mode, VSTROBE clocks data.
SD-CAS 91 O Active LOW SDRAM Column Address
SD-RAS 94 O Active LOW SDRAM Row Address
SD-CS0 95 O Active LOW SDRAM Chip Select 0
SD-CS1/MADDR11 96 O Active LOW SDRAM Chip Select 1 or use as MADDR11 for larger SDRAM
SDRAM Interface

(64 Mbits).
LDQM 77 O SDRAM Lower or Upper Mask
SD-BS 97 O SDRAM Bank Select
MADDR[10:0] 98, 80, 81, 84-86, 89, 104-102, 99 O SDRAM Address
MDATA[15:0] 63, 66, 69-73, 76, 62-57, 54, 53 I/O SDRAM Data
MWE 90 O SDRAM Write Enable
SD-CLK 78 O SDRAM Clock

22
IC BLOCK DIAGRAM & DESCRIPTION

Table 2 ZiVA-4.1 DVD Pin Descriptions (Continued)

Name Pin No. Type1 Description

C/R/V 151 Analog O DAC video output format. Macrovision encoded.
Y/B/U 145 Analog O DAC video output format. Macrovision encoded.
Analog Video Output

CVBS/G/Y 139 Analog O DAC video output format. Macrovision encoded.

CVBS + sync 133 Analog O DAC video output format: Composite + sync. Macrovision encoded.
RREF 155 Analog O Reference Resistor. Connecting to pin 154 through a 1.18K+/- 1% resistor is rec-
ommended
VCLK 159 I System clock that drives internal PLLs. ZiVA-4 requires an external 27-MHz TTL
oscillator.
HSYNC 30 I/O Horizontal sync. The decoder begins outputting pixel data for a new horizontal
line after the falling (active) edge of HSYNC.
Digital Video Output

VCLK 159 I Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz.
VDATA[7:0] 28-21 O Video data bus. Byte serial CbYCrY data synchronous with VCLK. At power-up,
the decoder does not drive VDATA. During boot-up, the decoder uses configura-
tion parameters to drive or 3-state VDATA.
VSYNC 29 I/O Vertical sync. Bi-directional, the decoder outputs the top border of a new field
on the first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an external source.
(VSYNC HIGH = bottom field. VSYNC LOW = Top field)

E
DA-DATA[3:0] 118, 119, 120, 121 O PCM Data Out. Eight channels. Serial audio samples relative to DA_BCK and
DA_LRCK.
DA-BCK 126
C O PCM Bit Clock. Divided by 8 from DA_XCK. DA_BCK can be either 48 or 32 times
Audio Interface

the sampling frequency

N
DA-LRCK 122 O PCM Left Clock. Identifies the channel for each sample. The polarity is program-
mable
DA-XCK 125 I/O Audio External Frequency Clock input or output. DA_BCK and DA_LRCK are
A

derived from this clock. DA_XCK can be 384 or 256 times the sampling fre-
quency
DV

DA-IEC 127 O PCM data out in IEC-958 format or compressed data out in IEC-1937 format.
Digital Mic In

DAI-DATA 117 I PCM data input.

DAI-BCK 114 I PCM input bit clock.
A

DAI-LRCK 113 I PCM left/right clock.

1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.

Table 3 lists the pins that have Schmitt Trigger inputs when programmed as inputs.

Table 3 Schmitt Trigger Inputs

Pin No. Pin Name Pin No. Pin Name

173 VSTROBE 165 DVD-DATA4/CDG-SDATA
171 VDACK 168 DVD-DATA5/CDG-VFSY
174 ERROR 169 DVD-DATA6/CDG-S0S1
161 DVD-DATA0/CD-DATA 170 DVD-DATA7/CDG-SCLK
162 DVD-DATA1/CD-LRCK 5 RESET
163 DVD-DATA2/CD-BCK 29 VSYNC
164 DVD-DATA3/CD-C2P0 30 HSYNC

23
IC BLOCK DIAGRAM & DESCRIPTION
IC U204 CY37032

UltraLogicTM 32-Macrocell ISRTM CPLD

Features — tS = 3.0 ns
— tCO = 4.0 ns
• 32 macrocells in two logic blocks
• Product-term clocking
• In-System Reprogrammable™ (ISR™)
• IEEE 1149.1 JTAG boundary scan
— JTAG-compliant on-board programming
• Programmable slew rate control on individual I/Os
— Design changes don’t cause pinout changes • Low power option on individual logic block basis
— Design changes don’t cause timing changes • 5V and 3.3V I/O capability
• Up to 32 I/Os • User-Programmable Bus Hold capabilities on all I/Os
— Plus 5 dedicated inputs including 4 clock inputs • Simple Timing Model
• High speed • PCI compliant
— fMAX = 222 MHz • Available in 44-Lead TQFP and PLCC packages
— tPD = 5.0 ns • Pinout compatible with the CY37032V, CY37064/
CY37064V, CY7C371i

Clock/
Logic Block Diagram Input Input
TDI
JTAG Tap
TCLK TDO
4 Controller
1 TMS

JTAGEN
4 4
36 36
16 I/Os LOGIC LOGIC 16 I/Os
I/O0−I/O15 BLOCK 16 PIM 16 BLOCK I/O16−I/O31
A B

37032-1
Pin Configurations 16 16
44-Lead TQFP (A44)
44-Lead PLCC (J67) Top View
Top View

I/O31
I/O30
I/O29
I/O28
VCCO
GND
I/O 0
I/O4
I/O3
I/O2
I/O1
VCCO
I/O31
I/O30
I/O29
I/O28
GND
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0

44 43 42 41 40 39 38 37 36 35 34
6 5 4 3 2 1 44 43 42 41 40 I/O5 /TCLK 1 33 I/O27 /TDI
39 I/O27 /TDI I/O6 2 32 I/O26
I/O 5 /TCLK 7
38 I/O26 I/O 7 3 31 I/O25
I/O6 8
37 I/O25 CLK2/I 0 4 I/O24
I/O7 9 30
36 I/O24
CLK2/I0 10 JTAGEN 5 29 CLK1/I 4
JTAGEN 35 CLK1/I 4 6 28 GND
11 GND
34 GND I3
GND 12 CLK0/I 1 7 27
33 I3
CLK0/I 1 13 I/O8 8 26 CLK3/I2
32 CLK3/I2
I/O8 14 I/O9 9 25 I/O23
31 I/O23
I/O9 15 I/O10 10 24 I/O22
30 I/O22
I/O10 16 I/O11 11 23 I/O21
29 I/O21
I/O11 17 12 13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
37032-2 37032–3
GND
I/O12

I/O14
I/O15

I/O16
I/O17
I/O18

I/O20
I/O19 /TDO
I/O /TMS

GND
I/O12

I/O14
I/O15

I/O16
I/O17
I/O18

I/O20
I/O19 /TDO
VCC

VCC
I/O13 /TMS
13

Selection Guide
CY37032-222 CY37032-200 CY37032-154 CY37032-125
Maximum Propagation Delay, tPD (ns) 5.0 6.0 7.5 10
Minimum Set-Up, tS (ns) 3.0 4 5 5.5
Maximum Clock to Output, tCO (ns) 4.0 4 4.5 6.5
Typical Supply Current, ICC (mA) in Low Power Mode 15 15 15 15
Shaded areas contain advance information.

24
IC BLOCK DIAGRAM & DESCRIPTION

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA 2.4 V
(Com’l/Ind)[2]
VOHZ Output HIGH Voltage with Out- VCC = Max. IOH = 0 µA (Com’l)[3] 4.0 V
put Disabled[6]
IOH = 0 µA (Ind) [3]
4.3 V
IOH = –50 µA (Com’l) [3]
3.6 V
IOH = –100 µA (Ind)[3] 3.6 V
[2]
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind) 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage 2.0 VCCmax V
for all inputs[4]
VIL Input LOW Voltage Guaranteed Input Logical LOW voltage −0.5 0.8 V
for all inputs[4]
IIX Input Load Current VI = GND OR VCC, Bushold Disabled −10 10 µA
IOZ Output Leakage Current VO = GND or VCC, Output Disabled, −50 50 µA
Bushold Disabled
IOZBH Output Leakage Current VCC = Max., VO = 3.3V, Output 0 −70 −125 µA
Disabled[3], Bus-Hold Enabled
IOS Output Short Circuit VCC = Max., VOUT = 0.5V −30 −160 mA
Current[5, 6]
IBHL Input Bus Hold LOW Sustaining VCC = Min., VIL = 0.8V +75 µA
Current
IBHH Input Bus Hold HIGH VCC = Min., VIH = 2.0V −75 µA
Sustaining Current
IBHLO Input Bus Hold LOW Overdrive VCC = Max. +500 µA
Current
IBHHO Input Bus Hold HIGH Overdrive VCC = Max. -500 µA
Current

Inductance[6]
Parameter Description Test Conditions 44-Lead TQFP 44-Lead PLCC Unit
L Maximum Pin Inductance VIN = 5.0V at f = 1 MHz 2 5 nH

Capacitance[6]
Parameter Description Test Conditions Max. Unit
CI/O Input/Output Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 8 pF
CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz at TA = 25°C 12 pF

Endurance Characteristics[6]
Parameter Description Test Conditions Min. Typ. Unit
[1]
N Minimum Reprogramming Cycles Normal Programming Conditions 1,000 10,000 Cycles
Notes:
2. I OH = –2 mA, IOL = 2 mA for TDO.
3. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered
significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note “Understanding Bus Hold”
for additional information.
4. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
5. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.

25
IC BLOCK DIAGRAM & DESCRIPTION
IC U214 Am29F002B/Am29F002NB

2 Megabit (256 K x 8-Bit)

CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F002 device
■ High performance
— Access times as fast as 55 ns
■ Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Top or bottom boot block configurations available
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■ Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)

26
IC BLOCK DIAGRAM & DESCRIPTION
PRODUCT SELECTOR GUIDE
Family Part Number Am29F002B/Am29F002NB

VCC = 5.0 V ± 5% -55

Speed Option
VCC = 5.0 V ± 10% -70 -90 -120

Max access time, ns (tACC) 55 70 90 120

Max CE# access time, ns (tCE) 55 70 90 120

Max OE# access time, ns (tOE) 30 30 35 50

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM
DQ0–DQ7
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
n/a Am29F002NB

WE# State
Control

Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#

Y-Decoder Y-Gating
STB
Address Latch

VCC Detector Timer

X-Decoder Cell Matrix

A0–A17

27
IC BLOCK DIAGRAM & DESCRIPTION
CONNECTION DIAGRAMS
NC on Am29F002NB NC on Am29F002NB

RESET#
RESET#
NC 1 32 VCC

WE#
A16 2 31 WE#

A16

A17
VCC
A12
A15
A15 3 30 A17
A12 4 29 4 3 2 1 32 31 30
A14
A7 5 29 A14
A7 5 28 A13
A6 6 28 A13
A6 6 27 A8
A5 7 27 A8
A5 7 26 A9
A4 8 26 A9
A4 8 PDIP 25 A11 PLCC
A3 9 25 A11
A3 9 24 OE# A2 10 24 OE#
A2 10 23 A10 A1 11 A10
23
A1 11 22 CE# A0 12 22 CE#
A0 12 21 DQ7 DQ0 13 21 DQ7
DQ0 13 20 DQ6 14 15 16 17 18 19 20
DQ1 14 19 DQ5

VSS
DQ3

DQ6
DQ1
DQ2

DQ4
DQ5
DQ2 15 18 DQ4
VSS 16 17 DQ3

A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 28 DQ6
A17 6 27 DQ5
WE# 7 26 DQ4
VCC 8 25 DQ3
Standard TSOP
NC on Am29F002NB RESET# 9 24 VSS
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3

28
IC BLOCK DIAGRAM & DESCRIPTION

PIN CONFIGURATION LOGIC SYMBOL

A0–A17 = 18 addresses
18
DQ0–DQ7 = 8 data inputs/outputs A0–A17 8
CE# = Chip enable DQ0–DQ7
OE# = Output enable
WE# = Write enable CE#
RESET# = Hardware reset pin, active low OE#
(not available on Am29F002NB)
WE#
VCC = +5.0 V single power supply
RESET#
(see Product Selector Guide for
device speed ratings and voltage N/C on Am29F002NB

supply tolerances)
VSS = Device ground
NC = Pin not connected internally

29
IC BLOCK DIAGRAM & DESCRIPTION

IC U206 SDRAM-HY57V65162B

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hyundai HY57V651620B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applica-
tions which require low power consumption and extended temperature range. HY57V651620B is organized as 4banks
of 1,048,576x16.

HY57V651620B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)

FEATURES

• Single 3.3V ± 10% power supply • Auto refresh and self refresh

• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms

• JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock - 1, 2, 4 or 8 for Interleave Burst

• Data mask function by UDQM or LDQM • Programmable CAS Latency ; 2, 3 Clocks

• Internal four banks operation

ORDERING INFORMATION

Part No. Clock Frequency Power Organization Interface Package

HY57V651620BTC-7I 143MHz
Normal
HY57V651620BTC-75I 133MHz
power
HY57V651620BTC-10SI 100MHz 4Banks x 1Mbits
LVTTL 400mil 54pin TSOP II
HY57V651620BLTC-7I 143MHz x16
Lower
HY57V651620BLTC-75I 133MHz
Power
HY57V651620BLTC-10SI 100Mhz

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4/Nov.00

30
IC BLOCK DIAGRAM & DESCRIPTION

PIN CONFIGURATION
VDD 1 54 VSS
DQ0 2 53 DQ15
VDDQ 3 52 VSSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 VDDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 VSSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 VDDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 VSS
LDQM 15 0.8mm pin pitch 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 VSS

PIN DESCRIPTION

PIN PIN NAME DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock
rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

BA0,BA1 Bank Address
Selects bank to be read/written during CAS activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

A0 ~ A11 Address
Auto-precharge flag : A10

Row Address Strobe,

RAS, CAS and WE define the operation
RAS, CAS, WE Column Address Strobe,
Refer function truth table for details
Write Enable

LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers

VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

31
 IC BLOCK DIAGRAM & DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh logic Internal Row

& timer counter

CLK 1Mx16 Bank 3

Row active Row 1Mx16 Bank 2

CKE Pre
X decoders

Decoders 1Mx16 Bank 1

X decoders

CS 1Mx16 Bank 0
State Machine

X decoders

RAS DQ0

Sense AMP & I/O Gate

X decoders

Memory DQ1

I/O Buffer & Logic

CAS refresh Cell
Array
WE Column Column
Active
Pre
UDQM Decoders DQ14
DQ15
LDQM Y decoders

Column Add
Bank Select Counter

A0 Address
A1 Registers
Address buffers

Burst
Counter

A11
BA0
CAS Latency
BA1 Mode Registers Data Out Control Pipe Line Control

32
IC BLOCK DIAGRAM & DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

Ambient Temperature TA -40 ~ 85 °C

Storage Temperature TSTG -55 ~ 125 °C

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD 1 W

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION (TA= -40 to 85°C)

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.3 3.6 V 1

Input High Voltage VIH 2.0 3.0 VDDQ + 2.0 V 1,2

Input Low Voltage VIL VSSQ - 2.0 0 0.8 V 1,3

Note :
1.All voltages are referenced to V SS = 0V
2.VIH (max) is acceptable 4.7V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION (TA= -40 to 85°C, VDD=3.3V ± 0.3V, VSS=0V)

Parameter Symbol Value Unit Note

AC Input High / Low Level Voltage VIH / VIL 2.4/0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise / Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL 50 pF 1

Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit

33
IC BLOCK DIAGRAM & DESCRIPTION

IC WS7805 POSITIVE-VOLTAGE REGULATORS

! 3-Termainal Regulators TO-252
! Output Current Up to 1.5 A WS7805DP
! No External Components
! Internal Thermal Overload Protection
! High Power Dissipation Capability O
I C
! Internal Shot-Circuit Current Limiting
(TO-252)
! Output Transistor Safe-Area
Compensation
DESCRIPTION
O
This series of fixed-voltage monolithic integrated-circuit
C
voltage regulators designed for a wide range of I
applications. These applications include on-card
TO-220
regulation for elimination of noise and distribution
WS7805CV
problems associated with single-point regulation. Each

of these regulators can deliver up to 1.5 amperes of

output current. The internal current limiting and thermal

shutdown features of these regulators make them

essentially immune to overload.

ABSOLUTE MAXIMUM RATINGS OVER OPERATING TENPERATURE

RANGE (UNLESS OTHERWISE NOTE)
WS7805 PARAMETER UNIT
Input voltage, VI 35 V
Continuous total dissipation at 25℃ free-air temperature 2 W
Lead temperature 1.6mm (1/16 inch) from case 10 seconds 260 ℃
Storage temperature range, Tstg -65 to 150 ℃

RECOMMEMDED OPERATING CONDITIONS MIN MAX UNIT

Input voltage, VI 7 25 V
Output current, IO 1.5 A
Operating virtual junction temperature, TJ 0 70 ℃

34
 10. Decode Board Block Diagram

Mixed Separate Dolby

2CH 5.1CH
S Complex Video
LPF

LPF 27MHz
MIC INPUT OSC
CS4228
ANALOG SIGNALS Simulate video
output

8 Bit Data I2 S
SDRAM
UDE
STRMREQ ZiVA 4.1 1 16Mbits
ITERFACE DSTROBE DVDREQ CSTROBE
BUFFER
16 ﾎｻ
STRMDMA CY37032 RAS/CAS

SDRAM
ｴｮ 1 16Mbits
ｿﾚ 8 Bit host interface

REMOTE INPUT
V8000 FLASH
DRAM
MMORY

3 LINE

I2 C
OUTPUR FRONT

DECODE BOARD DIAGRAM

35
11 SCHEMATIC & P.C.B WIRING DIAGRAM

11.1 FRONT SCHEMATIC DIAGRAM

SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
VCC
VFD401

22
21
20
19
18
17
16
15
14
13
12
1 FIL+

KEY4
KEY3
S8
S7
S6
S5
S4
S3
S2
S1
VDD
F1
2
F1
R401 33K KEY4
4 GRID1 R402 33K KEY3
5G
5 GRID2 SEG9 23 11 R403 33K KEY2
4G S9 KEY2
6 GRID3 SEG10 24 10 R404 33K KEY1
3G S10 KEY1
7 GRID4 SEG11 25 9 VFDST
2G S11 STB
8 GRID5 SEG12 26 8
1G S12/G1 CLK R417
9 -25V 27 7 GND VCC C406
NC VEE VSS 10K
10 SEG13 28 U401 6 101
NC S13/G1 DIN R411 R412 R413 R414
11 SEG14 29 UPD16312 5
NC S14/G9 DO R416 33K 33K 33K 33K
12 SEG15 30 4
NC S15/G8 SW4 10K
13 SEG16 31 3
NC S16/G7 SW3
14 SEG16 32 2 VCC
P1 G6 SW2
15 SEG15 GRID5 33 1 VFDCK
P2 G5 SW1
16 SEG14 VFDAT
P3

MSW
17 SEG13

SW2
SW3
SW4
P4
18 SEG12

LED4
LED3
LED2
LED1
VDD

OSC
P5

VSS
19 SEG11 R406 10K

G4
G3
G2
G1
P6 C404 C403
20 SEG10 R407 10K
P7 101 101
21 SEG9 R408 10K
P8 U403
22 SEG8 R409 10K

34
35
36
37
38
39
40
41
42
43
44
P9 HS0038A2
23 SEG7 R410 10K
P10
24 SEG6 R405 IR 3
P11
25 SEG5 33K C405

GRID4
GRID3
GRID2
GRID1
P12

GND
VCC
26 SEG4 VCC 1
P13
27 SEG3 2
P14
28 SEG2 104
P15 C402
29 SEG1 C401 100uF/16V
P16
104 C407
31 R415 100uF/16V
F2 100
32 FIL- VCC
F2

VFD-32
XS401
VCC 1
GND 2
SEG1

SEG2

SEG3

SEG4
-25V 3
R418 FIL- 4
D401 D402 D403 D404 100
FIL+ 5
1N4148 1N4148 1N4148 1N4148
XS05

K401 K405 K409 K413

XS402
KEY1 IR 1
K402 K406 K410 K414 GND 2
VFDST 3
KEY2 VFDCK 4
K403 K407 K411 K415 VFDAT 5
XS05
KEY3
K404 K408 K412 K416

KEY4

36
11.2 FRONT P.C.B. WIRING DIAGRAM

37
11.3 P.W. & OK. SCHEMATIC DIAGRAM

OK

R609 10K

R607
TC605 1K C605 101P
22uF/16V
R613
24K
TC603

4
4.7uF/16V
MIC602 9 C607 100P
8 TC601 R603 2
7 4.7uF 560R 1 -9VA
6 3
VR602

1
5
L602 10K

4
4 R612
U601A
3 R614

8
4.7K
2 R601 C603 R605 4558 2 2 1K
1 22K 103 10k 1
+9VA 3
U602A TC613 R617

3
4558 4.7uF/16V C608 100K

8
102
+5V

+9VA
R615
R610 VR601 100K
10K 10K R611
R608
4.7K
TC606 1K
MIC601 22uF/16V C606 R616
9 101P 1K VD601
8 1N4148 VD603
7 U601B TC604 1N4158
6 TC602 R604 6 4558 4.7uF/16V 6
5 L601 560R 7 7 R619 VOICE-DET
4.7u
4 5 5
330
3 U602B
2 4558
1 VD602 TC611 R620
R602 C604 R606 R618 R623 1N4148 47uF/16V 6.8K
22K 103 10K 10K 10K

R621 R622
10ohm1/6W 10ohm1/6W
+9V +9VA -9V -9VA

TC615 C601 TC616 C602

100uF/25V 104 100uF/25V 104

38
11.4 P.W. & OK. SCHEMATIC DIAGRAM

L504
C510 10uH/1A
101 +9V

C501 C514
D507 DGND 6
HER105 470uF/25V 470uF/25V XS502
S+12V 1 SD+5V 5
C511 DGND 2 DGND 4
101 D513 DGND 3 SA+5V 3 CN502
R502 C504 R507 L505 IN4001 S+5V 4 DGND 2 XS06
10K/2W 103/1KV 270K/2W ! D508 10uH/2A
XS04
S+8V 1
D501 D504 T501 17

R501 18 HER105
C516 1 3 SA+5V

GND
82K/2W D509 L508 IN OUT
2 15 470uF/25V C517
FB C528 C508
C503 D505 470uF/25V
470uF/16V U504
C502 101/1KV HER107 3 16 SR560 100uF/16V
L506 10uH/2A LM7805

2
D502 D503 47uF/400V R503 D506 13 +5V
10ohm HER105 4
8 C512
14 C536 C519 C520 VOICE-DET 1
C505 C509 1000uF/16V 1000uF/16V OK 2
BCN502
104 47uF/50V AGND 3
SW-SPST ! 7 12
L507
10uH/1A
+9V 4
CN503
! BC505 C506
101
11
D510
-9V
DGND
5
6 XS09
~275V 104
L503 R504 10 HER105 DGND 7
FB 1M C522 C521 +5V 8
330uF/25V 330uF/25V +5V 9
D511
L502
HER105

BC502
~400V 102 C537 C524
3

101 100uF/50V
!
BC501
! 4 D512
VCC

BC503
D

FB

330
~400V 102 HER105
! ~400V 102
GND
1 R514 R510
1K 10K

R509
U501 C538 C525
5L0380R 101 220uF/16V R513 ZD501
L501 5.1V
4.7K
C527
104
! BC504
~275V 104 CN501
+5V 5
RV501 ! DGND 4
! 14D471 C507 U502 -21V 3
223 U503 K R512 FL- 2
! R505 2501
LM431A R 10K FL+ 1
470K 2W
XS05
! A

F501
T1.6A/250V

BC506
! ~400V 222
! BCN501
~220V

39
11.5 P.W. & OK. WIRING DIAGRAM

40
11.6 MIAN SCHEMATIC DIAGRAM

/CPU_RST
/CPU_RST
VD202 D+3V D+5V
1N4148 AD[15..0]
D+5V D+5V
R201 10K R2105 0R

AD7

AD6

AD5

AD4

AD3

AD2
11 10 AD0 JP201 S1_AD0 R248 22K

AD15

AD14

AD13

AD12

AD11

AD10
Q211 P+5V AD1 JP202 S1_AD1 R247 22K 1 3.3V R2106 0R

AD9
TC201 S9015 R240 C212 2 D+5V

CSADAC
10uF/16V 10K 150pF U205E R253 3 GND
HC14 XS207 4 SDA
4.7K
R202 XS05 5 CLKSER
33ohm C201 +9V D+5V

47K

47K
XS201 104

33ohm
R249
XS05 D+5V R2107 0R

R241

R242
5 P+5V
4 TXD R228 33ohm 1 R2165 0R
3 RXD 2 D+5V
2 R252 33ohm C204 C205 TC203 3 GND
1 104 104 47uF/16V 4 L219 FB VOUT/G
5 GND

98 MTXD
6 L227 FB YOUT/B
7 GND
FB

100
P+5V DATA XS206 8 L228 COUT/R

99

97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DATA
XS15 9 GND
10 L229 FB ROUT
R210 R209 R219 11 GND

SDATA

VCC5
UZI

AD7

AD6

AD5

AD4

AD3

AD2
AD9
GND5
TXD

S6/CLKDIV2
RXD

AD15

AD14

AD13

AD12

AD11

AD10
47K 47K 4.7K R257 12 FB LOUT
0ohm L239
13 GND
14 SCLOCK
SDA R258 33ohm 1 80 AD1 15 SDATA
SDEN1 AD1
CS R204 33ohm MSCK 2 79 AD8
SDEN0 AD8
CLKSER R214 33ohm 3 78 AD0
SCLK AD0
4 77 STRMDMA XS205
33ohm BHE/ADEN DRQ0 STRMDMA
/WR R207 /WR1 5 76
33ohm WR DRQ1 22 21
/RD R208 /RD1 6 75 SCK VCK
RD TMRIN0 SCK 20 19
7 74 /MSYSRST R239 33ohm /SYSRST HSYNC VSYNC
ALE TMROUT0 /SYSRST 18 17
8 73 /MLDR_RST R238 33ohm /LDRRST VDATA7
ARDY TMROUT1 16 15
9 72 VDATA6
S2 TMRIN1 14 13
10 71 /CPU_RST VDATA5
S1 U201 RES 12 11
11 70 VDATA4
S0 GND4 10 9
12 69 VDATA3
GND0 MCS3/RFCH 8 7
CPUCLK27 13 AM186EM-33KC 68 MCSADAC R237 33ohm MCS2 VDATA2
X1 MCS2 MCS2 6 5
14 67 VDATA1
X2 VCC4 4 3
15 66 VDATA0
R213 VCC0 PCS0 2 1
CLKOUTA CLKOUTA1 16 65
CLKOUTA PCS1
75ohm 17 64 XS20
CLKOUTB GND3 33ohm
18 63 /MROMACS R233 /ROMACS
GND1 PCS2 33ohm /ROMACS
19 62 /MSTRMCS R231 /STRMCS
A19 PCS3 /STRMCS
20 61
A18 VCC3 33ohm
21 60 /MDVDCS R232 /DVDCS
VCC1 PCS5/A1 /DVDCS
P+5V D+5V A17 22 59
L201 A17 PCS6/A2
23 58 /MLCS R230 33ohm LCS
A16 LCS/ONCE0 LCS
A15 24 57 /MUCS R229 33ohm /UCS
FB A15 UCS/ONCE1 /UCS
A14 25 56 DVDINT
A14 INT0
A13 26 55
A13 INT1/SELECT
A12 27 54 /LDRRDY
A12 INT2/INTA0
A11 28 53 MATN_FM
A11 INT3/INTA1/IRQ 0ohm
A10 29 52 R250 VOICE-DET
A10 INT4 33ohm FB FB
A9 30 51 R227 MCS1 /LDRRST L256 L274 SDD7
A9 MCS1 FB 1 2 FB
SDD6 L257 L273 SDD5
FB 3 4 FB
SDD4 L258 L272 SDD3
FB 5 6 FB
HLDA
HOLD
SRDY

MCS0
P+5V SDD2 SDD1
VCC2

GND2

L259 L271
WHB

DT/R
WLB

7 8

DEN
NMI
R225 R226 SDD0 L260 FB
A8
A7
A6
A5
A4
A3
A2

A1
A0

9 10 FBSMT
1K 1K DACK L261 FB L270 DSTROBE
FB 11 12 DSTROBE
XSTRMREQ L262 L269 STRMERR
13 14 FB/DECSEL STRMERR
C202 C203 L268
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
FB 15 16 FBRXD /DECSEL
R222 /HOSTSEL L263 L267
33ohm FB 17 18 FB/HOSTRDY
104 104 /H-RDY TXD L264 L266
FB 19 20
U205A L265
MNMI

21 22
R221 D-MUTE
PA4
PA3
PA2

PA1

33ohm D-MUTE FB
2 1 L202
XS202 FB
XS22 L203
R220 L204 FB
R215
R216
R217

R218

33ohm HC14

U205C R223
A4 33ohm
A3 33ohm
A2 33ohm

A1 33ohm

33ohm
IR 5 6
IR
A8
A7
A6
A5

HC14 R224
A[3..1] 0ohm
A[15..1]

U205D
/DVDWAIT
/DVDWAIT
/DVDINT 9 8
/DVDINT
D+5V
HC14

1 L249 FB IR
2 L250 FB GND
XS203 3 FB CS TC202
L251
FB 10uF/16V
XS05 4 L252 SCK
5 L253 FB DATA

To VFD board

41
MIAN SCHEMATIC DIAGRAM

MADDR[11..0]

MDATA]15..0]

U206 U207
U214 1 50 1 50
VCC0 GND5 VCC0 GND5
AM29F800BT-120SC MDATA0 2 49 MDATA15 MDATA0 2 49 MDATA15
DQ0 DQ15 DQ0 DQ15
MDATA1 3 48 MDATA14 MDATA1 3 48 MDATA14
DQ1 DQ14 DQ1 DQ14
A1 11 15 AD0 4 47 4 47
A0 D0 GND0 GND4 GND0 GND4
A2 10 17 AD1 MDATA2 5 46 MDATA13 MDATA2 5 46 MDATA13
A1 D1 DQ2 DQ13 DQ2 DQ13
A3 9 19 AD2 MDATA3 6 45 MDATA12 MDATA3 6 45 MDATA12
A2 D2 DQ3 DQ12 DQ3 DQ12
A4 8 21 AD3 7 44 7 44
A3 D3 VCC1 VCC5 VCC1 VCC5
A5 7 24 AD4 MDATA4 8 43 MDATA11 MDATA4 8 43 MDATA11
A4 D4 DQ4 DQ11 DQ4 DQ11
A6 6 26 AD5 MDATA5 9 42 MDATA10 MDATA5 9 42 MDATA10
A5 D5 DQ5 DQ10 DQ5 DQ10
A7 5 28 AD6 10 41 10 41
A6 D6 GND1 GND3 GND1 GND3
A8 4 30 AD7 MDATA6 11 40 MDATA9 MDATA6 11 40 MDATA9
A7 D7 DQ6 DQ9 DQ6 DQ9
A9 42 16 AD8 MDATA7 12 39 MDATA8 MDATA7 12 39 MDATA8
A8 D8 DQ7 DQ8 DQ7 DQ8
A10 41 18 AD9 13 38 13 38
A9 D9 VCC2 VCC4 VCC2 VCC4
A11 40 20 AD10 14 37 14 37
A10 D10 DQML NC1 DQML NC1
A12 39 22 AD11 15 36 15 36
A11 D11 WE DQMU WE DQMU
PWR-U214 A13 38 25 AD12 16 35 16 35
A12 D12 CAS CLK CAS CLK
A14 37 27 AD13 17 34 17 34
A13 D13 RAS CKE RAS CKE
A15 36 29 AD14 /SD_CS1 18 33 18 33
R254 A14 D14 CS NC0 CS NC0
LA16 35 31 AD15 MADDR11 19 32 MADDR9 MADDR11 19 32 MADDR9
0ohm A15 D15 BA A9 BA A9
LA17 34 MADDR10 20 31 MADDR8 MADDR10 20 31 MADDR8
A16 R255 A10 A8 A10 A8
LA18 3 2 A18-U220 LA19 MADDR0 21 30 MADDR7 MADDR0 21 30 MADDR7
A17 A18 A0 A7 A0 A7
1 0ohm MADDR1 22 29 MADDR6 MADDR1 22 29 MADDR6
NC A1 A6 A1 A6
33 PWR-U214 MADDR2 23 28 MADDR5 MADDR2 23 28 MADDR5
C215 /BYTE A2 A5 A2 A5
/UCS 12 MADDR3 24 27 MADDR4 MADDR3 24 27 MADDR4
/CE A3 A4 A3 A4
104 /RD 14 23 25 26 25 26
/OE VCC VCC3 GND2 VCC3 GND2
/WR 43
/WE C213 C217
/CPU_RST 44 13 TC237 SDRAM-2X512KX16-8A SDRAM-2X512KX16-8A
/RESET GND1 1000pF 0.1uF
32 47uF/16V
GND2
SDRAM0 PWR

C228 C229 C230 C231 C232 C233 C234 C235 C236 C237 C238 C239
104 104 104 104 104 104 104 104 104 104 104 104

TC207
47uF/16V
SD_CLK
D+5V

U205B L/UDQM

GND
14

OUT
U211
HC14 /MWE

IN
AS2815
/SD_CAS D+3V
PWR-U214 PWR_HST_DRAM 3 4 C206 /SD_RAS
104 /SD_CS0

1
2
3
L238
ZV+5V VD214 VD215 D+3V ZV+5V

7
FB L207 D+3V
FB
C226 TC205 TC206 C227
D+5V 1N5401 1N5401 104 47uF/10V 47uF/10V 104
/RD
R234 33ohm /RD
CSTROBE MCS2
L255 MCS2
DVDREQ MCS1
FBSMT MCS1
DACK

U208
SDD7 D+5V PWR_HST_DRAM
C209 C210 SDD6 L206 424260-70
TC240
102 102 47uF/16V LA19 SDD5 FBSMT 1 40
VCC1 GND3
LA18 SDD4 AD0 2 39 AD8
D0 D15
AD1 3 38 AD9
D1 D14
AD2 4 37 AD10
44
43
42
41
40
39
38
37
36
35
34

D2 D13
AD3 5 36 AD11
D3 D12
6 35
VCC2 GND2
AD4 7 34 AD12
I/O4
I/O3
I/O2
I/O1
I/O0
GND

I/O31
I/O30
I/O29
I/O28
VCC

D4 D11
AD5 8 33 AD13
D5 D10
LA17 1 33 SDD3 AD6 9 32 AD14
I/O5 I/O27 D6 D9
LA[19..16] LA16 2 32 SDD2 AD7 10 31 AD15
I/O6 I/O26 D7 D8
3 31 SDD1 11 30
I/O7 I/O25 NC1 NC4
/ROMACS 4 30 SDD0 12 29 MCS2
CLK2/10 I/O24 NC2 CASL
5 U204 29 /H-RDY SDD[7..0] /WR 13 28 MCS1
JTAG CLK1/14 /WR WE CASH
6 28 LCS 14 27
GND GND LCS RAS OE
CLKOUTA 7 CY37032-QFP44 27 RXD R235 15 26 A17
CLK0/11 13 0ohm NC3 A8
/CPU_RST 8 26 DSTB DSTROBE A1 16 25 A15
I/O8 CLK3/12 A0 A7
/RD 9 25 STRMRQ XSTRMREQ A3 17 24 A13
I/O9 I/O23 A1 A6
/STRMCS 10 24 /DECSEL R236 A5 18 23 A11
I/O10 I/O22 33ohm A2 A5
STRMDMA 11 23 /HOSTSEL A7 19 22 A9
I/O11 I/O21 A3 A4
20 21
I/O12
I/O13
I/O14
I/O15

I/O16
I/O17
I/O18
I/O19
I/O20
GND
VCC

VCC3 GND1
R212
R246
100ohm
750ohm
C219 C220 C221 TC204
12
13
14
15
16
17
18
19
20
21
22

102 102 102 47uF/16V

/HOSTRDY

A[19..0]
AD7
AD6
AD5
AD4

AD3
AD2
AD1
AD0

AD[7..0]

42
MIAN SCHEMATIC DIAGRAM

STRMERR CSTROBE
STRMERR CSTROBE
DVDREQ
A[3..1] DVDREQ
DACK D+3V
L212 FB
SDD[7..0]
AD[7..0] R265
R264

SDD7
SDD6
SDD5

SDD4
SDD3
SDD2
SDD1
SDD0
4.7K VCK

AD0
AD1

AD2
AD3
AD4
AD5
AD6

AD7
VCK

A3
A2
A1
D+3V D+2.5V 4.7K ZV-AVCC
D+3V
TC214 C268 C269
R262 R263 R266 1 K 102
47uF/16V 104
4.7K 1K

208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
/DVDCS D+3V
/DVDCS
/RD 1 156 VDD-RREF

HDATA0
HDATA1

HDATA2
HDATA3
HDATA4
HDATA5
HDATA6

HDATA7

A-VDD
VREQUEST

DVD-DATA4/CDG-SDATA

DVD-DATA0/CD-DATA
DVD-DATA1/CD-LRCK

VCLK
DVD-DATA2/CD-BCK

SYSCLK
RESERVED21
RESERVED20
RESERVED19
RESERVED18

RESERVED17

RESERVED16
RESERVED15
RESERVED14

RESERVED13
VDD255
VDD3317

VDD3316

VDD3315

VDD3314

VDD3313
NC17
NC16
NC15

A-VSS
DVD-DATA7/CDG-SCLK

DVD-DATA5/CDG-VFSY
VDACK

DVD-DATA3/CD-C2PO
DVD-DATA6/CDG-S0S1
HADDR2
HADDR1
HADDR0

ERROR
VSTROBE
/RD RD

CS
VDD-RREF

VSS22

VSS21

VSS20

VSS19

VSS18

VSS17
/WR 2 155
/WR R/W RREF L211
3 154 C267 FBSMT
VDD330 VSS-RREF TC213
/DVDWAIT 4 153 R267
/DVDWAIT WAIT VDD-VIDEO3 47uF/16V 104
/SYSRST 5 152 1.18K/1%
/SYSRST RESET VDD-DAC3
6 151
VSS0 C/R/V L210
7 150 VGND
VDD331 VSS-VIDEO3 FBSMT
/DVDINT 8 149
/DVDINT INT VSS-DAC3
9 148 D+3V
NC0 NC14
10 147 AVCC-ENC
NC1 VDD-VIDEO2
11 146
NC2 VDD-DAC2 C263 C264 C265 C266 L209
12 145 TC212
NC3 Y/B/U 104
13
VDD250 VSS-VIDEO2
144 47uF/16V 104 104 104 FBSMT
D+3V 14 143 VGND
VSS1 VSS-DAC2
15 142 L208
NC4 NC13 FBSMT
16 141 VID_C
C246 C245 C244 C243 C242 C241 C240 NC5 VDD-VIDEO1 VID_C
TC209 17 140 VID_Y
NC6 VDD-DAC1 VID_Y
47uF/16V 104 104 104 104 104 104 104 18 139 VID_COMP
NC7 CVBS/G/Y VID_COMP
19 138
VSS2 VSS-VIDEO1
20 137
VDD332 VSS-DAC1 R268 R269 R270
VDATA0 21 136
VDATA0 NC12 75ohm 75ohm 75ohm
VDATA1 22 135
VDATA1 VDD-VIDEO0
VDATA2 23 134
VDATA2 VDD-DAC0
VDATA3 24 133
VDATA3 U217 CVBS+SYNC
VDATA4 25 132
VDATA4 VSS-VIDEO0
VDATA5 26 131 VGND
VDATA5 VSS-DAC0
D+3V VDATA6 27 ZIVA-4.1 130
VDATA6 NC11
VDATA7 28 129
VDATA7 VSS16
VSYNC 29 128
VSYNC VDD254
C223 C224 C274 HSYNC 30 127 R271 33R IEC958
104 104 104 HSYNC DA-IEC 33R IEC958
31 126 R272 DA_BCK
VSS3 DA-BCK 22R DA_BCK
32 125 R273 DA_XCK
VDD333 DA-XCK DA_XCK
33 124
RESERVED0 VSS15
34 123
RESERVED1 VDD3312 33R
35 122 R274 DA_LRCK
RESERVED2 DA-LRCK DA_LRCK
36 121
VDD251 DA-DATA0 33R
37 120 R275 DA_DATA1
VSS4 DA-DATA1 33R DA_DATA1
38 119 R276 DA_DATA2
RESERVED3 DA-DATA2 DA_DATA2
39 118 R277 33R DA_DATA3
RESERVED4 DA-DATA3 DA_DATA3
40 117 DAI_DATA
RESERVED5 DAI-DATA DAI_DATA
41 116
RESERVED6 VSS14
42 115
RESERVED7 VDD3311 R2170 33ohm
43 114 CPUCLK27
PIO0 DAI-BCK
44 113
VSS5 DAI-LRCK
45 112
VDD334 RESERVED12 VCK

SD-CS1/MADDR11
46 111 33ohm
PIO1 RESERVED11 R211

4
47 110 D+5V
PIO2 RESERVED10
48 109
PIO3 NC10
49 108 U218B

MADDR10
MDATA15

MDATA14

MDATA13
MDATA12
MDATA11
MDATA10
PIO4 RESERVED9 C2149

VDD3310
MADDR9
MADDR8

MADDR7
MADDR6
MADDR5

MADDR4

MADDR0

MADDR1
MADDR2
MADDR3
MDATA0
MDATA1

MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7

MDATA9

MDATA8
50
VDD335

VDD336

VDD252

VDD337

VDD338

VDD253

VDD339
107 14 HCU04
7

CLKSEL
SD-CLK

SD-CAS

SD-RAS
SD-CS0
PIO5 NC9

VSS10

VSS11

VSS12

VSS13
LDQM

SD-BS
51 106

MWE
VSS6

VSS7

VSS8

VSS9
PIO6 NC8 104
52 105 U218A
PIO7 RESERVED8

3
1 2
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
HCU04 R259
220

R2110
R296
R295

R294
R293

R292
R291
R290

R289
R288
R287

R286
R285
R284
R283
R282
R281

R280
R279
R278
4.7K
MDATA15

MDATA14

MDATA13
MDATA12
MDATA11
MDATA10
MDATA0
MDATA1

MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7

MDATA9

MDATA8

X204
33R
33R

MADDR9 33R
MADDR8 33R

MADDR7 33R
MADDR6 33R
MADDR5 33R

MADDR4 33R
33R
33R

33R
MADDR11 33R
MADDR10 33R
MADDR0 33R

MADDR1 33R
MADDR2 33R
MADDR3 33R
33R
33R
27MHz
C293 C294
MDATA[15..0] 20P 20P
L/UDQM
L/UDQM
SD_CLK
SD_CLK

MADDR[11..0]
/SD_CS1
/SD_CS1
/SD_CS0
/SD_CS0
/SD_RAS
/SD_RAS
/SD_CAS
/SD_CAS
D+3V /MWE D+2.5V
/MWE

C247 C248 C249 C250 C251 C252 C253 C254 C255 C256 TC210 VD213 C257 C258 C259 C260 C261 C262 TC211
104 104 104 104 104 104 104 104 104 104 1N4001 104 104 104 104 104 104
47uF/16V 47uF/10V

43
MIAN SCHEMATIC DIAGRAM

JK202
V-OUT5 5

Power Connector
-9V +9V ZV+5V D+5V

7
1 L240 FBSMT VOICE-DET
2 L213 FBSMT OKA
3 AGND
D+3V 4 L214 FBSMT
XS204 5 L215 FBSMT
C276 C278 XS09 6
15

VD207 7
L254 IN4148 8 L216 FB
22P 22P 9 FB
FBSMT L217
VIDEO-OUT VOUT/G L221 L222 VID_COMP
1.8uH 1.8uH VID_COMP
12 Y/G
GREEN VD208 C275 C277 C279 C270 C271 C272 C273
IN4148 330P 270P 330P 104 104 104 104
14 GND
TC217 TC218
220uF/16V 220uF/16V
11 VGND
BLUE L243 L220
D+3V
FBSMT FB
13 C281 C283 VGND AGND
VD209
IN4148 22P 22P
10
RED YOUT/B L223 L224 VID_Y
VID_Y
1.8u 1.8uH
VD210 C280 C282 C284
330P 270P 330P
L244 IN4148
JK201 VGND
V-OUT2 FB
VGND
D+3V
2

L231 C286 C288

3 U/B VD211
JK202 IN4148 R298 R2102 Q203
LUMA FBSMT 22P 22P
S-VIDEO 1K D+5V +9V 1 K 1015
L230 L225 L226
CHROMA 4 V/R COUT/R VID_C MUTE-1 Q204 VD203
VID_C
FBSMT 1.8uH 1.8uH 1015 1N4148 +9V
VD212 C285 C287 C289 Q201
IN4148 330P 270P 330P 1015
1

R299 TC216
IO-GND R297 1K 47uF/16V
1K Q202 VD205
VGND 2SC1815-Y 1N4148
15

D-MUTE
R2101 R2100
-9V 330ohm 10K

WHITE 12 Lt R2104 VD204

VD206 100ohm 1N4148
W05Z4.5V TC215 R2103
14 100uF/16V 10K

11 Rt
RED

13

C291 U218E HCU04 U218F HCU04

10 R2109 10 11 12 13 IEC958
BLACK 330ohm
104
R2108
91ohm
JK203
V-OUT2 L245

FB
IO-GND2

JK204 U218C HCU04 U218D HCU04

1 6 5 8 9
VIN
2 D+5V
VCC L218
3 FB
GND
OPTICAL C2133 TC234
104 1uF/16V

44
MIAN SCHEMATIC DIAGRAM

+9V U222 ADI+5V

NJM78L05A
1 3
IN OUT

GND
ADI+5V L205 AD+3V
FB TC235 TC236 C297 R256
C298

2
R2129 20K
10uF/16V 0.1uF 47uF/16V0.1uF 220K
AGND
C2111 150PF TC233
R251 TC231 C2139

8
100uF/16V
+9V 510ohm1uF/16V 104
TC219 2 R2130 R2131 R2132 C2137
1 U212 104 AGND
4.7K 4.7K 6.8K
3 DA_DATA1 1 28
C2112 C2113 SDIN3 AOUT6
10uF/25V U219A DA_DATA2 2 27
1000PF 1200PF SDIN2 AOUT5
4580 DA_DATA3 3 26
-9V SDIN1 AOUT4
DAI_DATA R244 150ohm 4 25

4
SDOUT AOUT3
DA_BCK 5 24
SCLK AOUT2
20K AGND DA_LRCK 6 23
R2133 LRCK AOUT1
GND 7 22
DGND AGND

10uF/16V
JK201 R243 ADI+5V 8 21
C2114 150PF VD VA R206 C208

TC239
10K R245 9 20
L232 R2117 VL AINL+ 150ohm 0.47u

8
ROUT CH-R DA_XCK 2.2K 10 19 OKA
+9V DA-XCK AINL-
FB 1K CLKSER 11 18
Q205 R2134 R2135 R2136 MCLK FILT
7 Rt 6 SDA 12 17 OKA
2SC1815-Y MDIO AINR-
TC220 7 4.7K 4.7K 6.8K CSADAC 13 16 C207
C299 R2111 C2100 R2118 MCS AINR+
CH-L 5 /SYSRST 14 15 R205 0.47u
RST MUTEO
47pF 100K 1nF C2115 C2116 150ohm
1K U219B R203 0ohm
8 10uF/25V 4580 1000PF 1200PF GND CS4228
-9V C2138

4
AGND AGND 104
AGND R2137 20K TC22510uF/16V C218 C222 TC232
9 Lt C2101R2112 R2119 103 103 100uF/16V
R
47pF 100K C2102
1K R2153
L233 1nF Q206 C2117 150PF 560 TC22610uF/16V
R2120

8
FB 2SC1815-Y 1K L
+9V
LOUT
TC221 2 R2138 R2139 R2140 R2154
L234 R2121 560
CH-SR 1 R2155
4.7K 4.7K 6.8K C2129 C2130100K
FB 1K 3
4 10uF/25V C2118 C2119 1000P 1000P
R2122 U220A
C2103R2113 C2104 4580 1000PF 1200PF AGND
47pF 100K 1nF -9V
1K R2156

4
Q207 AGND 100K
5 R2157
2SC1815-Y SR
R214120K TC227
560
AGND 10uF/16V
R2123 MUTE-1 R2158
C2120 SL
6 C2105R2114 C2106 150PF 560 TC228
1K

8
47pF 100K 1nF Q208 10uF/16V
+9V
2SC1815-Y
L235 R2124 R2142 R2143 R2144 C2131 C2132 R2159 R2160
TC222 6
FB CH-SL 7 1000P 1000P 100K 100K
1K 4.7K 4.7K 6.8K
5 AGND
L236 R2125 10uF/25V U220B C2121 C2122
FB 4580 1000PF 1200PF
1K -9V
1

4
C2107R2115 C2108 R2126 R2161
SW
47pF 100K 1nF R2145 20K AGND TC229
1K 560
Q209 10uF/16V
L248 C2123 150PF R2162
2 2SC1815-Y C

8
FBSMT R2127 +9V 560
IO-GND2 AGND
1K TC223 2 R2146 R2147 R2148 R2164 TC230
3 C2109R2116 C2110 CH-SW 1 100K 10uF/16V
4.7K 4.7K 6.8K
47pF 100K 1nF Q210 3
2SC1815-Y 10uF/25V U221A C2124 C2125 AGND
L237 1000PF 1200PF
-9V 4580
FB R2128 4 C2134 C2135 R2163
A/V-O3 1000P 1000P 100K
1K
R2149 AGND
20K
C2126
150PF
8

+9V
TC224 6 R2150 R2151 R2152
CH-C 7 4.7K 4.7K 6.8K
5
10uF/25V C2127 C2128
4580 1000pF 1200pF
-9V
U221B
4

+9V
AGND

C214 C216 C2143

0.1uF 0.1uF 0.1uF

AGND

-9V

C2145 C2146 C2144

0.1uF 0.1uF 0.1uF

AGND

45
 11.7 MAIN PCB TOP SILK DIAGRAM
45

46
11.8 MAIN P.C.B. BOTTOM SILK DIAGRAM

47
12 Packing & Accessories Section Exploded View

48
 13. The component list of electric part

PCB type Power OK PCB PCB type Power OK PCB

Component Specification Position Component Specification Position
Carbon film
1/6W10 ±5% figuration 7.5 R621,R622 CD CD11 25V100U±20%6×12 2.5 TC615,TC616
resistor
Carbon film
1/6W330 ±5% figuration 7.5 R619 CD CD11 25V470U±20%10×16 5 C516,C517,C501,C514
resistor
Carbon film
1/6W560 ±5% figuration 7.5 R603,R604 CD CD11 16V4.7U±20%5×11 2 TC601~TC604,TC613
resistor
Carbon film
1/6W1K±5% figuration 7.5 R607,R608,R614,R616 CD CD11 16V22U±20%5×11 2 TC605,TC606
resistor
Carbon film
1/6W6.8K ±5% figuration 7.5 R620 CD CD11 25V22U±20%5×11 2 *
resistor
Carbon film R605,R606,R609,R61
1/6W10K±5% figuration 7.5 CD CD11 50V47U±20%6×12 2.5 C509
resistor 0,R618,R623
Carbon film
1/6W22K±5% figuration 7.5 R601,R602 CD CD11 16V1000U±20%10×20 5 C519,C520
resistor
Carbon film
1/6W100K±5% figuration 7.5 R615,R617 CD CD110 16V1000U±20%10×16 5 *
resistor
Carbon film
1/4W10 ±5%figuration10 R503 CD CD11 16V1000U±20%10×16 5 *
resistor
Carbon film
1/4W330 ±5% figuration 10 R509 CD GZ 16V1000U±20%10×20 5 *
resistor
Carbon film
1/6W4.7K±5% figuration 7.5 R611,R612, CD CD11 50V100U±20%8×12 C5 C524
resistor
Carbon film
1/4W4.7K±5% figuration 10 R513 CD CD11 25V330U±20%10×12 5 C521,C522
resistor
Carbon film
1/4W1M ±5% figuration 10 R504 CD LP3 400V47U±20%22×28 10 C502
resistor
Carbon film
1/6W24K±5% figuration 7.5 R613 CD LS 400V47U±20%22×25 10 C502*
resistor
Metal film Bead
1/4W10K±1% figuration 10 R512 RH354708 L601,L602,L503,L508
resistor inductor
Metal film
2W10K±1% figuration 15 R502 Choke 立式 10UH 1A 5mm L504,L507
resistor
Metal film
2W82K±1% figuration 15 R501 Choke 立式 10UH 2A 5mm L505,L506
resistor
Switch
Metal film
2W270K±1%X R507 power BCK-4025B-2811A T501
resistor
transformor
Metal film
1/4W9.4K ±1% R510 Diode 1N4148 VD601~VD603
resistor
Rotatable D506~D508,D510~D51
R0901N-BA1-B10K VR601,VR602 Diode HER105
electrograph 2
Rotatable
A091NOXA-V1B103-003 VR601,VR602 * Diode HER107 D505
electrograph
Rotatable Zenner
W109-1A-B10K-F20 * 5.1V 1/2W ZD501
electrograph diode
Ceramic disc
50V 47P ±5% NPO 5mm C605,C606 Diode 1N4007 D501~D504
capacitor
Ceramic disc
50V 47P ±5% 5mm * Diode SR560 DO-27 D509
capacitor

49
Ceramic disc
50V 47P ±10% 5mm * IC NJM4558D DIP U601,U602
capacitor
C506,C538,C537,C53
Ceramic disc
50V 100P ±10% 5mm 6,C512,C511,C607, IC KA4558 DIP *
capacitor
C510
Ceramic disc
50V 103 ±10% 5mm C603,C604, IC LM7805 金封 TO-220 U504
capacitor
Ceramic disc C527,C601,C602,C50
50V 104 ±20% 5mm IC 5L0380R YDTU U501
capacitor 5,
Ceramic disc
50V 102 ±20% 5mm C608 IC LM431ACZ TO-92 U503
capacitor
Ceramic disc 1000V 103 +80%-20%
C504 IC TL431C TO-226AA(LP) *
capacitor 7.5mm
Ceramic
CT81 400V 221±20% 10mm BC506 IC 431L TO-92 *
capacitor
Ceramic
CT81 400V221±10% 10mm * IC KA431AZ TO-92 *
capacitor
Ceramic disc Electric net
1000V 101 ±10% 7.5mm C503 UT-20 40mH ±20% 10×13 L501,L502
capacitor filter
Terylene
100V 223 ±10% 5mm C507 Varistor 7D 471 ±10% 5mm RV501
capacitor
Terylene
275V 104 ±20% 15mm BC504,BC505 CCD NEC2561 U502
capacitor
Terylene
275V 104 ±10% 15mm BC504,BC505 * CCD PC817 *
capacitor
CD11 16V100U±20%6×12
CD C508 CCD NEC2501 *
2.5
CD11 16V220U±20%6×12
CD C525 CCD HS817 *
2.5

CD CD11 16V470U±20%8×123.5 C528 CCD 817D *

CD CD11 25V47U±20%5×11 2 TC611 MIC socket CK3-6.35-106 MIC601,MIC602

Wire ０．６　ｆｉｇｕｒａｔｉｏｎ　１０ｍｍ J502,J504,D513 Wire ０．６　ｆｉｇｕｒａｔｉｏｎ　７．５ｍｍ J601~J607
Wire ０．６　ｆｉｇｕｒａｔｉｏｎ　１２．５ｍｍ J501,J503,J505~J507

50
 Decoding PCB Decoding PCB
Component Specification Position Component Specification Position
C201~C206,C214,C216~C21
7,C223~C233,C240~C268,C
Chip
Chip resistor 1/16W 220 ±5% R259 25V 104 +80%-20% 0603 270~C274,C291,C297,C298,
capacitor
C2133,C2137~C2141,C2143
~C2146,C2149
C201~C206,C214,C216~C21
R250,R255,R258,L256~L261,L2 7,C223~C233,C240~C268,C
Chip
Chip resistor 1/16W 0 ±5% 65,L267,L271~L274,R234,R235, 50V 104 +80%-20% 0603 270~C274,C291,C297,C298,
capacitor
R2171,R2182,R2183 C2133,C2137~C2141,C2143
~C2146,C2149
Chip
Chip resistor 1/16W 22 ±5% R273 50V 20P ±5% NPO 0603 C293,C294,C2150,C2151
capacitor
Chip C276,C278,C281,C283,C286
Chip resistor 1/16W 3.3K ±5% R298,R225 50V 22P ±5% NPO 0603
capacitor ,C288,C211
R2153,R2154,R2157,R2158,R21 Chip C299,C2101,C2103,C2105,C
Chip resistor 1/16W 560 ±5% 50V 47P ±5% NPO 0603
61,R2162 capacitor 2107,C2109
R204,R226,R238,R263,R266,R2 Chip
Chip resistor 1/16W 1K ±5% 50V 271 ±5% NPO 0603 C277,C282,C287
99,R2102,R2117~R2128 capacitor
Chip C275,C279,C280,C284,C285
Chip resistor 1/16W 2.2K ±5% R245,R2172 50V 331 ±5% NPO 0603
capacitor ,C289
R219,R253,R262,R264,R265,R2
L201,L205,L206,L207,L209,
110,R2130,R2131,R2134,R2135, Bead
Chip resistor 1/16W 4.7K ±5% RH354708 L213~L218,L232~L238,L240
R2138,R2139,R2142,R2143,R21 inductor
,L255
46,R2147,R2150,R2151
L202,L203,L208,L210~L212,
L230,L231,L249,L251~L254,
Chip resistor 1/16W 10K ±5% R201,R240,R243,R2100,R2103 Chip bead FCM1608K-221T05
L270,L245,R213,L262,L264,
L266
Chip
Chip resistor 1/16W 22K ±5% R241,R242,R247,R248 1.8UH ±10% 1608 L221~L226
inductor
Chip resistor 1/16W 47K ±5% R209.R210,R246 Diode 1N4001 VD213
R2111~R2116,R2155,R2156,R21
Chip resistor 1/16W 100K ±5% Diode 1N5401 VD214,,VD215
59,R2160,R2163,R2164
VD202~VD205,VD207~VD2
Chip resistor 1/16W 150 ±5% R205,R206,R244,R2104 Chip diode 1N4148
12
Chip resistor 1/16W 75 ±5% R268,R269,R270 Chip diode LS4148 *
R202,R207,R208,R211,R214~R2
18,R220,R221,R223,R227~R229,
Chip resistor 1/16W 33 ±5% R231~R233,R236,R237,R239,R2 Chip diode LL4148 *
52,R271,R272,R274~R296,R216
6~R2169,R2177,R2179,R222
Chip resistor 1/16W 1.2K ±5% R267 Dynatron 2SA1015 Q203,Q204
R2132,R2136,R2140,R2144,R21
Chip resistor 1/16W 6.8K ±5% Dynatron 9015C Q211
48,R2152
R2129,R2133,R2137,R2141,R21
Chip resistor 1/16W 20K ±5% Dynatron C1815Y Q202,Q205~Q210
45,R2149
Chip resistor 1/16W 100 ±5% R212,R2176 IC HY514264B SOJ U208
Chip resistor 1/16W 330 ±5% R2101,R2109 IC V53C16258HK50 SOJ *
Chip resistor 1/16W 91 ±5% R2108 IC NJM4558M SOP U219,U220,U221
CD11 16V1U±20%5×
CD TC231 IC 4580 SOP *
11 2
CD11 16V220U±20%6
CD TC217,TC218 IC 4558 SOP *
×12 2.5
CD11 16V10U±20%5× TC201,TC202,TC219~TC230,T
CD IC MM74HCU04M SOP U218
11 2 C235,TC239

Decoding PCB Front Panel PCB

51
Component Specification Position Component Specification Position
Carbon film
IC RDC V8000 QFP U201 1/4W100 ±5% R415
resistor
CS4228A-KS EP Carbon film 1/4W100 ±5% figuration
IC U212 *
SSOP resistor 10
Carbon film
IC ZIVA-4.1 QFP U217 1/4W10K±5% R406 R410,R416,R417
resistor
Software
Carbon film 1/4W10K±5% figuration
program JED DU5 *
resistor 10
CPLD
Software
ROM908S2-0A Carbon film
program 1/4W33K±5% R401~R405,R411~R414
8M resistor
FLASH
Crystal Carbon film 1/4W33K±5% figuration
40.00MHZ 49-U X201 *
resonator resistor 10
Crystal Metal film
27.00MHz 49-U X204 1/4W6.8 ±5% R418
resonator resistor
Optical Ceramic
transmitting GP1F32T JK204 disc 50V 100P ±10% 5mm C403,C404,C406
module capacitor
Optical Ceramic
transmitting TX178A * disc 50V 104 ±20% 5mm C401,C405
module capacitor
11 ;in 1.0mm double CD11C 10V100U±20%5×
Cable socket XS202 CD C402,C407
line direct insertion 72
Socket AV12-8.4-2G JK201 Diode 1N4148 D401 D404
Socket CS-09 JK202 IC D16312GB QFP U401
CD11C 16V47U± TC203~TC207,TC209~TC216,T
CD IC PT6312LQ QFP *
20%5×7 2 C234,TC236,TC237,TC240
CD11C 16V100U±
CD TC232,TC233 Display HNV-05SS32 U402
20%6×7 2.5
CD11 16V100U±20%6 Light tough
CD * 卧式6×6×1 K401 K416
×12 2.5 reset switch
Chip 50V 151 ±5% NPO C212,C2111,C2114,C2117,C212
Wire ０．６　ｆｉｇｕｒａｔｉｏｎ　１０ｍｍ J402
capacitor 0603 0,C2123,C2126
Chip 10V 105 +80%-20% ０．６　　ｆｉｇｕｒａｔｉｏｎ
C207,C208 Wire J401
capacitor 0603 １２．５ｍｍ
Chip C2113,C2116,C2119,C2122,C21 Receiving
50V 122 ±10% 0603 HS0038A2 U403
capacitor 25,C2128 head
C209,C210,C213,C218~C222,C2
69,C2100,C2102,C2104,C2106,C
Chip
50V 102 ±10% 0603 2108,C2110,C2112,C2115,C2118
capacitor
,C2121,C2124,C2127,C2129~C2
132,C2134,C2135
IC HCU04 SOP U218
IC 74HC14D SOP U205
IC MM74HC14M SOP *
IC D4564163G5-A80 U206
MT48LC4M16A2-
IC *
75C SOP
IC HY57V641620HG *
IC HC574A SOP U202,U203

52