AEC Lab Manual - Complete

Dept.
Of Electrical & Electronics Engineering
GOVERNMENT ENGINEERING COLLEGE PALAKKAD
DEPARTMENT OF ELECTRICAL AND ELECTRONICS

ENGINEERING
ANALOG ELECTRONIC CIRCUITS LAB
S3 Electronic Circuits Lab Manual i

Dept. Of Electrical & Electronics Engineering
CONTENTS
I. Vision, Mission, PEO and PSO ........................................................................... v

II. Program Outcomes ............................................................................................. vi
III. Syllabus ......................................................................................................... ix
IV. Course outcome ................................................................................................... xi
V. General laboratory instructions ............................................................................ xii
VI. List of experiments .............................................................................................. xv
S3 Electronic Circuits Lab Manual ii

Department of Electrical & Electronics Engineering
Vision:
Be a centre of excellence in Electrical and Electronics Engineering having strong learning and
research environment, capable of making significant contributions for sustainable development.
Mission:
To generate world-class engineers to meet challenges in the field of Electrical and Electronics
Engineering through innovations and pursuit of new knowledge and make them ethically sound and
professionally competent to provide service to the society.
Program Educational Objectives (PEOs)

1. To mould the students with global standards by providing knowledge in Basic sciences and
Mathematics in general and Electrical & Electronics Engineering in particular.
2. To impart necessary skill and practical knowledge to design, analyze and synthesize Electrical
& Electronic systems using modern problem solving tools and techniques.
3. To equip the students with effective oral and written communication skills, professional ethics
and team work capabilities for a successful professional career.
4. To instill in students self confidence and leadership qualities to become innovative engineers
and entrepreneurs, with an enthusiasm for lifelong learning.
Program Specific Outcomes (PSOs)

At the end of the course the Electrical & Electronics Engineering graduates are able to:
1. Design and analyze the performance of Electric Power system, Electrical Machines, Control
systems, Electronic and Power Electronic Systems.
2. Attain technical competence in developing, testing and implementing Electrical and/or
Electronic systems with effective use of relevant Processors/Controllers and Application
software.
3. Apply theoretical concepts and practical skills in providing Electrical and/or Electronics
Engineering solutions with a view of energy conservation and sustainability.
PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
S3 Electronic Circuits Lab Manual v

EE 221 ELECTRONIC CIRCUITS LAB
SYLLABUS
List of Experiments : ( Out of 18 experiments listed, 12 experiments are mandatory)
1. Study & Use of CRO: Measurement of current voltage, frequency and phase shift.
2. Half wave and Full wave (Centre-tapped and bridge) Rectifiers with and without filters -
Calculation of Ripple factor, Rectification efficiency, and % regulation.
3. Clipping circuits using diodes
4. Clamping circuits using diodes
5. RC coupled amplifier using BJT in CE configuration- Measurement of gain, input and
output impedance and frequency response
6. JFET amplifier- Measurement of voltage gain, current gain, input and output impedance
7. Design and testing of simple zener voltage regulators
8. OPAMP circuits – Design and set up of inverting and non-inverting amplifier, scale
changer, adder, integrator, differentiator
9. Precision rectifier using Op-amps
10. Phase shift oscillator using OPAMPs.
11. Wein’s Bridge oscillator using OPAMPs.
12. Waveform generation – Square, triangular and sawtooth wave form generation using
OPAMPs.
13. Basic comparator and schmitt trigger circuits using Op-amp
14. Design and testing of series voltage regulator using zener diode
15. Astable and monostable circuit using 555 IC
16. RC phase shift oscillator using BJT
17. Introduction to circuit simulation using any circuit simulation software.
18. Introduction to PCB layout software
S3 Electronic Circuits Lab Manual vii

As per the B.Tech ordinance Scheme of evaluation for laboratory/ Practical/workshop courses
is as follows.
(i) Practical records/ output 60 Marks (internally by the college)
(ii) Regular class viva10 Marks (internally by the college)
(iii) Practical examination internally conducted by the college out of 30 marks.
25 marks for practical examination and 5 marks for the Viva.
The practical Examination shall be conducted as per the schedule in the academic calendar
with two examiners (need not be faculty member engaging the practical classes.) from the department.
There is no need of writing fair records. Only one record is needed which is to be written in
the lab class itself after the completion of the experiments. No pre-printed records shall be used
S3 Electronic Circuits Lab Manual viii

COURSE OUTCOME(CO)
After successful completion of this course, a student will be able to
1. Use an oscilloscope (CRO or DSO) to view and measure signals
2. Design and develop regulated DC power supplies
3. Analyze amplifier circuits using BJT and JFET
4. Develop circuits to generate common signals using OPAMPs and other ICs
5. Create wave shaping circuits using diodes
6. Prepare simulation models of analog circuits
MAPPING OF COURSE OUTCOME WITH PO
PO PO PO PO PO PO PO PO PO
PO10 PO11 PO12
1 2 3 4 5 6 7 8 9
CO1
CO2
CO3
CO4
CO5
CO6
S3 Electronic Circuits Lab Manual ix

GENERAL LABORATORY INSTRUCTIONS
PRECAUTIONS FOR ELECTRICAL SAFETY
01. Wear shoes compulsorily

02. Girl students should put up their hair
03. Students should wear neat and tight dress
04. Remove metal jewelry, watches, rings, etc., before working on electrical
circuits
05. Do not lean over rotating machinery
06. Turn off power and unplug from the wall before working on electric or
electronic circuits except when absolutely necessary
07. Do not connect more than one wire to each terminal of ammeters and
voltmeters
08. Never defeat the purpose of a fuse or circuit breaker. Never install a fuse of
higher amperage rating than that specifically listed for your circuit
09. All connections should be tight
10. Check the position of autotransformer, rheostats and switches before turning
ON
11. Immediately report and do not use defective cords and plugs
12. Turn off power and unplug equipment before checking or replacing fuses
13. Never overload circuits
14. When a setup or circuit is to be reconfigured or rewired, turn the power
supply off. It is also a good practice to disconnect it from the power supply
15. While doing break tests on motors, pour water to the brake drum to avoid
overheating
16. Energize the circuit only after getting approval from the faculty-in-charge
S3 Electronic Circuits Lab Manual x

RECORD
1. Write Name of the experiment with number & date.

2. Each record should contain the following on the RIGHT side
◦ Aim of the experiment
◦ Apparatus required
◦ Design
◦ Result (at the end)
3. On LEFT side
◦ Neat circuit diagram with PEN
◦ Tabulations
◦ Sample Calculation (on the left side if possible; if calculations are too long, write on the
right side so that no pages on the right side are left blank)
◦ Graph (draw with PEN if possible; use different colors for different graphs on the same
graph sheet). Take at least six sets of readings, if possible. Each student in a group should
do sample calculations for different sets.
4. Get signature of the faculty-in-charge after completing the rough record.
Do experiment TODAY; Get Rough Record attested before the NEXT CLASS
S3 Electronic Circuits Lab Manual xi

S3 Electronic Circuits Lab Manual xii

Electronic Circuits laboratory offers opportunities to design and evaluate a wide range of
analog electronic circuits and provide software tools to simulate the same. Electronic circuits form
the backbone of modern life in the form of personal gadgets and industrial control equipments.
Electronic components and basic application circuits are familiarized in this laboratory.
LIST OF EXPERIMENTS
CYCLE 1
1. Study of CRO ……………………………………………………...……….. 1

2. Rectifiers and filters ……………………………………………..….……… 5
3. RC coupled amplifier using BJT ……………………..…………….………. 15
CYCLE 2
4. A) Diode clipping circuits ……………………………………..…………… 21

B) Diode clamping circuits ……………………………………..………..… 27
5. Operational amplifier circuits 1 …………………………………..……...… 37
6. FET source follower amplifier …………………………………..……….… 43
CYCLE 3
7. A) Zener voltage regulator ……………………...…………….………….… 49

B) Series voltage regulator ………...……………………………………….. 53
8. Operational amplifier circuits 2 …………………………………………….. 57
9. A) RC phase shift oscillator …………………………………………...….… 63
B) Wien bridge oscillator ………………………………………….…..….… 67
CYCLE 4
10. A) Waveform generation using OPAMP – Square wave……….…..……..… 71

B) Waveform generation using OPAMP – Triangular wave……….…..….… 75
C) Waveform generation using OPAMP – Sawtooth wave……….…..…..… 79
11. A) Astable Multivibrator using 555…………………………………....….… 87
B) Monostable Multivibrator using 555…………………………...…..….… 91
12. Simulation of analog circuits ……….….……………………………..….… 99
S3 Electronic Circuits Lab Manual xiii

Dept. of Electrical and Electronics Engineering
Block Diagram of Cathode Ray Oscilloscope
Block Diagram of Digital Storage Oscilloscope
S3 Electronic Circuits Lab Manual 1

Experiment No. 1
STUDY OF CRO
Aim
To study the working of a Cathode Ray Oscilloscope (CRO) and a Digital Storage
Oscilloscope (DSO) and to view and measure various signals and Lissajous pattern.
Components and Equipments Required
Pot - 1 kΩ
Capacitor - 1 μF
Function Generator
CRO (or DSO)
Principle
An oscilloscope is an electronic device used to view and measure varying signal voltages. An
oscilloscope is called the eye of an electronic engineer for this reason. There are two main types of
oscilloscopes based on their display technology – Cathode Ray Oscilloscope (CRO) and Digital
Storage Oscilloscope (DSO).
The CRO uses a cathode ray tube to display the input signals. A heater element in the tube
emits electrons, that are deflected by two set of plates – an X plate that deflects the ray in the X axis
and a Y plate that deflects the ray in the Y axis. Their combined effect traces the shape of the signal
on a phosphorescent coated screen. When an electron hits the phosphorescent coating, it produces a
point of light for a short duration. When no voltage is applied to both X & Y plates, the electron beam
produces a point at the center of the screen.
A voltage applied to the X plate deflects the electron beam to a point along the X axis
according to the potential applied. When a ramp signal is applied to the X plate, the electron beam
traces a line from left to right on the screen. This is called sweep. The frequency of the ramp signal
determines the speed of motion of trace.
When a voltage signal is applied to the Y plates, the electron beam moves up and down, the
amplitude of which is proportional to the applied voltage at Y plates. This movement creates a vertical
line of varying amplitude in the Y axis. To stretch out the voltage signal pattern over time for
observation, the ramp signal is applied to the X plates. The frequency of the X plate signal determines
the horizontal zoom of the signal.
A Digital Storage Oscilloscope samples the input voltage signal at a high rate (usually 1 Giga
samples /sec or more), digitizes the values and stores them in an internal memory. The display is
usually a TFT screen. The stored values are given to a processor, which also receives the X axis zoom
ratio and plots the samples according to this ratio in the screen.

Circuit Diagram
Lissajous Pattern
x2
x1
Phase difference between X plate and Y plate signals,

𝑥1
φ = sin−1 ( )
𝑥2

The presence of a processor offers a wide range of possibilities to a DSO compared to a CRO.
Since the voltage levels of the samples are available in the memory, measurement is easier and also
a range of mathematical operations like rms value, average value, FFT analysis etc can be performed
and the results displayed.
These obvious advantages of DSO have made it more popular in the recent years.
Procedure
To view and measure signals
Switch ON the CRO or DSO. Apply a sine wave of frequency 1kHz and amplitude 1V (peak
to peak) from the function generator. Change the Volts/div scale from 0.5 V/div to 10 V/div and
observe the change in the displayed waveform. Now change the Time/div scale from 2 ms/div to 20
ms/div and observe the change in the displayed waveform.
To view Lissajous pattern and measure phase difference
Setup the circuit shown in figure. Apply a sine wave of frequency 1kHz and amplitude 1V (p-
p) across the series RC combination. Connect a probe across the terminals marked A & B and give it
as input to first CRO channels. Connect a probe across the terminals marked M & N and give it as
input to the second CRO channel. Both waveforms now appear on screen. Adjust volts/div and
time/div to get a good view of both signals. Make the traces of both channels coincide, by adjusting
the position knob on each channel. Note the phase difference between them. Vary the pot and observe
the change in phase difference.
Now push the XY button in CRO (change Display to X–Y from Y–T in DSO). The elliptical
pattern obtained is called Lissajous pattern. Measure the phase difference between the two signals as
shown in figure. Vary the pot and observe the change in shape of the pattern.
Result
Various voltage signals were observed and their measurements taken using a CRO & DSO.
Also setup a circuit to view Lissajous pattern and measured the phase difference between signals.

Circuit Diagrams
Fig. 1: Half wave rectifier without filter

MC
MC
0
Fig. 2: Half wave rectifier with Capacitor filter
Fig. 3: Full wave rectifier without filter

MC
MC
BY127

Experiment No. 2
RECTIFIERS AND FILTERS
Aim
To study the waveforms of half wave, full wave and bridge rectifiers with and without
capacitor filter and to calculate the percentage regulation and ripple factor at various load currents.
Diode - BY 127 / 1N4007 (4 Nos.)

DC Ammeter - 0 – 300mA MC
DC Voltmeter - 0 – 10V MC
Rheostat - 500Ω, 1.2A
Capacitor - 1000μF
Transformer - Center- tapped, 230V / 6 – 0 – 6 V, 500 mA
DMM
DSO
Principle
Rectifier is a device capable of converting a bidirectional input wave into a unidirectional

waveform with a non-zero average value. In a half wave rectifier the current flows through the load
only during the positive half cycle. During the negative half cycle the diode is reverse biased and
there is no load current. In a full wave rectifier, current flows through the load during both half cycles
in the same direction. One of the two diodes conduct during the negative half cycle and the other one
conducts during the positive half cycle. Ripple factor is a measure of amount of the pulsating
components present in the rectified output. It is defined as the ratio of the rms value of the ripple
components in the output to the average value of the output.
𝑉𝑟.𝑟𝑚𝑠
Ripple factor, r = 𝑉𝑑𝑐
This can be reduced to the form
𝑉2
r = √ 𝑉𝑟𝑚𝑠
2 −1
𝑑𝑐
Ripple factor can be reduced by connecting a capacitor across the load. This capacitor will
provide a low impedance path to the ac components in the rectifier output and will bypass the
pulsating components. The ripple component in the output can now be approximated to a triangular
waveform and the rms value of the ripple component can be derived to be
𝑉𝑟.𝑝−𝑝
Vr.rms = 2√3

Fig. 4: Full wave rectifier with Capacitor filter
Fig. 5: Full wave Bridge rectifier with Capacitor filter
Tabulations and Sample Calculations
Half Wave Rectifier without Filter
Sl. Idc Vdc Vm Vrms Ripple Voltage Rectification

No. mA Volts Volts Volts Factor regulation Efficiency
IL = ; Vdc = ; Vm = ; VNL = ;
Vrms = Vm / 2 =
𝑉2
Ripple Factor = √ 𝑉𝑟𝑚𝑠
2 −1
𝑑𝑐
𝑉𝑁𝐿 −𝑉𝐿
% Regulation = x 100
𝑉𝑁𝐿

Therefore the ripple factor for a rectifier with capacitor filter is

r = 2√3
As the load current increases, the terminal voltage drops. This change is indicated by the parameter
called voltage regulation.
𝑉 −𝑉𝐿
Voltage regulation = 𝑁𝐿
𝑁𝐿𝑉
Procedure
Do the connections as shown in the figure 1. Switch on the supply with the rheostat in the
maximum resistance position. Note the voltmeter reading for zero reading in the ammeter. This is
VNL. Increase the load current starting from 40 mA by adjusting the rheostat , in steps of 40 mA.
Readings may be taken up to a current of about 280 mA. For each ammeter reading, note the voltmeter
reading, the maximum value of the waveform from the CRO.
Repeat the procedure with connections done as shown in figures 2, 3, 4 and 5. For connections
with capacitor filter, measure the peak to peak value of the output waveform from the CRO.
Calculate the ripple factor and voltage regulation and plot the ripple factor and % regulation
vs. load current graphs.

Half Wave Rectifier with Filter
Sl. Idc Vdc Vr.p-p Vr.rms Ripple Voltage Rectification

IL = ; Vdc = ; Vr.p-p = ; VNL = ;

Vr.rms = 2√3
𝑉𝑟.𝑟𝑚𝑠
Ripple Factor = 𝑉𝑑𝑐
𝑉𝑁𝐿
Full Wave Rectifier without Filter
Sl. Idc Vdc Vm Vrms Ripple Factor Voltage Rectification

No. mA Volts Volts Volts regulation Efficiency
IL = ; Vdc = ; Vm = ; VNL = ;
𝑉𝑚
Vrms = =
√2
𝑉2
Ripple Factor = √ 𝑉𝑟𝑚𝑠
2 −1
𝑑𝑐
𝑉𝑁𝐿

Full Wave Rectifier with Filter
Sl. Idc Vdc Vr.p-p Vr.rms Ripple Factor Voltage Rectification

No. mA Volts Volts Volts regulation Efficiency
IL = ; Vdc = ; Vr.p-p = ; VNL = ;

Vr.rms = 2√3
𝑉𝑟.𝑟𝑚𝑠 𝑉𝑁𝐿 −𝑉𝐿
Ripple Factor = ; % Voltage regulation = x 100
𝑉𝑑𝑐 𝑉𝑁𝐿
Full Wave Bridge Rectifier with Filter
Sl. Idc Vdc Vr.p-p Vr.rms Ripple Voltage Rectification

IL = ; Vdc = ; Vr.p-p = ; VNL = ;

Vr.rms = 2√3
𝑉𝑟.𝑟𝑚𝑠 𝑉𝑁𝐿 −𝑉𝐿
Ripple Factor = ; % Voltage regulation = x 100
𝑉𝑑𝑐 𝑉𝑁𝐿

Waveforms
Vm
Input Waveform
Output Waveforms
Vm
0
Half wave rectifier without filter
Vr.p-p
Half wave rectifier with filter
Vm
Full wave rectifier without filter

Vr.p-p
Full wave and Bridge rectifier

with filter


Result
Half wave, full wave and bridge rectifier circuits with and without capacitor filter were setup.
The percentage regulation and ripple factor at various load currents were calculated and plotted the
following curves:
(i) % Regulation vs. Load current
(ii) Ripple factor vs. Load current

Circuit Diagram
Vout
V1
V2
V1
Transistor Specifications
BC 108B NPN Silicon Transistor
Maximum power dissipation : 300mW
Maximum collector current : 200mA
VCEmax : 30V
Design
Given VCC = 6V, IC = 1mA

From the datasheet, for BC108B corresponding to IC = 1mA,
hFE = 260; hfe = 330, hie = 7.5kΩ
Assumptions
To fix the operating point in the middle of the active region. Take VCE = 50% of VCC ,
VRE = 10% of VCC and VRC = 40% of VCC .
VCE = 0.5 x 6 = 3V ; VRE = 0.1 x 6 = 0.6V ; VRC = 0.4 x 6 = 2.4V

𝑉𝑅𝐶 2.4
RC = = 10−3= 2.4kΩ
𝐼𝐶
𝐼 10−3
IB = ℎ 𝐶 = = 0.003846mA
𝐹𝐸 260

Experiment No. 3
RC AMPLIFIER USING BJT IN CE CONFIGURATION
Aim
To design and setup a BJT common emitter amplifier and to measure it's voltage gain, current
gain, input impedance and output impedance.
BJT - BC 108B
Resistors - 560 Ω
1k
2.2k
10k
33k
47k
110k
Capacitors - 1 μF (2 Nos.)
400 μF
Function Generator
CRO
DMM
Principle
In common emitter amplifier, AC input signal to be amplified is applied between the base and
the emitter. The output is taken across the collector and the emitter. Hence emitter is common to both
input and output. This amplifier has large voltage gain and current gain and hence large power gain.
Its medium input impedance and output impedance lie between those of CC and CB amplifiers. The
output voltage is 180o out of phase with the input voltage.
Active region is the linear region of operation of a transistor and it is necessary that the
transistor operates in this region for the entire excursion of the input signal to avoid distortion of the
output signal. So the operating point is fixed at the center of the active region to permit the maximum
possible swing of the input signal. Applying suitable values of DC voltages and currents to fix the
operating point appropriately is called biasing the transistor.
VCE is fixed as 50% of VCC to fix the operating point at the center of the active region. To
incorporate a negative feedback (to improve the bias stability), a resistor RE is connected between the
emitter terminal and the ground and 10% of VCC is dropped across the resistor.

Since IB is negligible compared to IC and IE, take IE = IC = 1mA
𝑉𝑅𝐸 0.6
RE = = 10−3 = 600Ω
𝐼𝐸
For effective biasing, let the resistor R2 carry current equal to 10 times the base current, IB .
10 IB = 0.03846mA; Therefore, IR1 = IR2 + IB = 11 IB = 0.0423mA
VR2 = VBE + VRE = 0.7 + 0.6 = 1.3V
𝑉𝑅2 1.3
R2 = = 0.03846x10−3= 33.8kΩ
𝐼𝑅2
VR1 = VCC – VR2 = 6 – 1.3 = 4.7V

𝑉𝑅1 4.7
R1 = = 0.0423x10−3= 111.11kΩ
𝐼𝑅1
RB = R1||R2 = 33.8||111.11 = 25.92kΩ

R = (RB||hie) + RS = (25.92||7.5) + 1 = 6.8168kΩ
1
CC = 2𝜋𝑓 𝑅= 1.16μF
𝐿
1+ℎ
RB||hie = 2𝜋𝑓 𝑓𝑒
𝐶 𝐿 𝑒
1+ℎ𝑓𝑒
CE = 2𝜋𝑓 = 453.6μF
𝐿 (𝑅𝐵 ∥ℎ𝑖𝑒 )

Procedure
Checking the DC conditions

Connect the transistor, resistors R1, R2, RC, RE and the DC source as in figure. Adjust the DC
voltage to 6V (VCC). Measure the voltages VBE, VCE, VR1, VR2, VRC and VRE. See that they agree with
the designed values.
After checking the DC conditions, assemble the rest of the circuit. Apply the AC signal as
specified in the circuit. Measure the voltages V1 and V2. Measure the output voltage without
connecting any resistance across the output. This is VNL. Connect R01 and R02 alternately and measure
V01 and V02 respectively.
Observe the input and output voltage signals on a CRO and observe the phase difference.
Calculate voltage gain, current gain, input impedance and output impedance.

Observations
DC Conditions:
Parameter VCC VBE VCE VRE VRC VR1 VR2

Designed values
Observed values
CE Amplifier:
V1 (mV) V2 (mV) VNL (V) V01 (V) V02 (V)
Calculations
V1 = ; V2 = ; R = 1kΩ
𝑉 −𝑉
I1 = ( 1 𝑅 2 )
𝑉
Input Impedance = 𝐼2 =
1
𝑉𝑁𝐿
No load output voltage, VNL = ; Voltage gain = =
𝑉2
𝑉 𝐼
Output current, Io = 𝑅01 ; Current gain = 𝐼0
01 1
(𝑉01 −𝑉02 )
Output Impedance, R = 𝑉02 𝑉01
−
𝑅02 𝑅01

Result
Designed and setup a CE amplifier circuit and the following parameters were obtained.
Voltage gain =
Current gain =
Input impedance =
Output impedance =

Circuit Diagrams
Fig. (a) Upper level clipping
Fig. (b) Lower level clipping
Fig. (c) Clipping at two independent levels (Vγ2 > Vγ1)

Experiment No. 4A
DIODE CLIPPING CIRCUITS
Aim
To design and setup clipping circuits using diodes and to observe the input voltage, output
voltage and transfer characteristics on CRO.
Diode - 1N4007 (2 Nos.)

Zener Diode - 5.1 V (2 Nos.)
Resistor - 10k
Transformer - 230/6- 0- 6 V
Function Generator
CRO
Principle
Clipping circuits are used to transmit, that part of an arbitrary waveform which lies above or
below some reference level. Clipping circuits are also referred to as voltage limiters, amplitude
selectors or slicers.
i) Upper level clipping [Fig. (a)]

When Vi < VR + Vγ, the diode is in OFF position and VO = Vi. When Vi > VR + Vγ, the diode
is ON and the increments Vi in the input are attenuated and appear at the output as increments
𝑅𝑓 𝑅𝑓
VO = Vi x 𝑅 +𝑅 . This verifies the linear portion of the slope 𝑅 +𝑅 for Vi > VR + Vγ in the transfer
𝑓 𝑓
curve.
ii) Lower level clipping [Fig. (b)]

When Vi < VR + Vγ the diode is ON and hence the transfer characteristics appear as shown.
When Vi > VR + Vγ, the diode is OFF and Vi = VO
iii) Clipping at two independent levels [Fig. (c) & Fig. (d)]
This is similar to both upper level and lower level clipping circuits combined. In fig. (c), the
voltages are different, but of same polarity. The clipped waveform will have it's upper and lower
levels above zero volts. For this, the upper level voltage Vγ2 must be greater than Vγ1
Fig. (d) Clipping at two independent levels (Vγ1 = Vγ2)
Fig. (e) Zener diode clipping

In fig. (d), the voltages are same, but of different polarity. Thus, the upper level will be of
positive polarity and lower level will be of negative polarity. Both these levels will be of same
magnitude.
iv) Zener diode clipping (Double ended clipping)[Fig (e)]

When the input is greater than (VZ + Vγ), D1 will be under reverse breakdown and D2 will be
forward biased. Hence, the output will be constant at (VZ + Vγ). When input is less (more negative)
than (VZ + Vγ ), D1 will be forward biased and D2 will be under reverse breakdown with the result
that the output will be constant at -(VZ + Vγ).
Design
1. Selection of R
In the transmission region of all diode clipping circuits, we require that Rr >> R. Let Rr = KR,
where K is a large number. In the attenuation region, we require that R >> Rf. Let R = KRf. From the
two equations, we deduce that 𝑅 = √𝑅𝑓 𝑅𝑟 where Rr is the reverse resistance of the diodes and Rf is
the forward resistance of the diode.
Typical value of Rf = 10Ω
Typical value of Rr = 10MΩ
So, 𝑅 = √𝑅𝑓 𝑅𝑟 = 10kΩ
2. Selection of Diodes
Diode is selected such that during the ON period, the current through it and power dissipation
must be below the rated value. During OFF period, the maximum reverse voltage across it must be
below the breakdown voltage.
3. Design of Zener diode circuit
Breakdown voltage of Zener diode = VZ

Maximum load current = IL
Cut in voltage = Vγ
Maximum input voltage = Vimax = √2𝑉𝑖𝑟𝑚𝑠
𝑉𝑖𝑚𝑎𝑥 −(𝑉𝑍 +𝑉𝛾 )

Resistance in series with Zener diode = 𝐼𝐿
6√2−(5.1+0.7)
= = 268.5Ω
10𝑥10−3
Waveforms
Procedure
Set up the circuit as shown. Observe the input in one channel and output in another channel.
To observe the transfer characteristics, the input is given to the X- plate and output to the Y- plate of
CRO. By cutting the time base, the CRO is operated in X-Y mode. The clipped voltage level is
measured from the CRO.
Result
The various clipping circuits were designed and set up. The input, output waveforms and
transfer characteristics were observed on the CRO.
Circuit Diagrams
Fig. (a) Negative clamping
Fig. (b) Positive clamping
Fig. (c) Clamping to a reference voltage negatively
Fig. (d) Clamping to a reference voltage positively

Experiment No. 4B
DIODE CLAMPING CIRCUITS
Aim
To design and setup clamping circuits using diodes
Diode - 1N4007 (2 Nos.)

Capacitor - 0.1F
Resistor - 100k
Function Generator
CRO
Principle
Circuits used for adding or subtracting a DC voltage to a given waveform without changing
the shape of the waveform are known as clamping circuits. A capacitor which is charged to voltage
and subsequently prevented from discharging is the main component of the clamper. Let the input
signal applied be a sine wave given by Vm sint. Fig. (a) shows a clamper clamping negatively at
zero volt. The drops across the diodes are neglected in the ideal case. But practically, the drop across
the diode will be present and clamped level will not be exactly zero. The working of the circuit is as
follows:
During the first positive half cycle of the input sine wave, the diode conducts and the capacitor
charges to Vm at the end of the quarter cycle with polarity shown. During the negative half cycle of
the input, capacitor cannot discharge, since the diode does not conduct.
The output voltage, VO= –Vm + Vm sint.
When the amplitude of the input is zero, the output will be (– Vm ) and when the input is +Vm, the
output will be zero. When the input changes to (–Vm ), the output becomes (– 2 Vm) and the ideal
output will be as shown.
Fig. (b) shows a clamper clamping positively at zero volt. During the negative half cycle of
the input, the diode conducts and the capacitor cannot discharge since the diode does not conduct.
The output voltage, VO= Vm + Vm sint.
Hence the output waveform will be as shown, with maximum voltage at 2Vm .
The clamping level can be changed to any voltage level by biasing the diode as shown in Fig.
(c). Such a set up is called biased clamper. During the positive half cycle of the input, the capacitor
charges through the diode and the battery up to (Vm – 2) volts.
The output voltage, VO= – (Vm – 2) – VY + Vm sint,
by taking the drop across the diode into account.
Fig. (d) shows the clamper clamping positively at +2 volts. The capacitor charges during the
negative half cycle upto a voltage of (Vm + 2).
The output voltages, (Vm +2) – VY + Vm sint.
Design
For faithful clamping, the RC time constant of the clamping circuit must be far less than the
time period of the applied input waveform.
Rf C << T
For an input signal of 1kHz frequency, T = 1ms
Typical value of Rf = 100Ω
Take Rf C = 0.01T = 0.01ms = 10-5 s
Hence, C = 0.1 μF
Input – Output voltage characteristics
Fig. (a) Negative clamping

Procedure
Observe the output waveforms for sinusoidal and square inputs for all the clamping circuits.
Note the clamped voltage levels and record it. The output shown here are by taking the drop across
the diode. In practical case, the drop across the diode will be there and the clamped level will be 0 for
the first two set ups.
Fig. (b) Positive clamping
Fig. (c) Clamping to a reference voltage

negatively
Fig. (d) Clamping to a reference voltage positively
Result
The various clamping circuits were designed and set up. The input and output waveforms were
observed on the CRO.
Fig. 3
INTRODUCTION TO OPERATIONAL AMPLIFIERS
An Operational Amplifier, commonly called opamp is a three stage circuit namely, the input
stage, gain stage and the output stage, which is fabricated as an integrated circuit. The input stage is
a differential amplifier, the gain stage provides the additional voltage gain with necessary DC level
shifting and the output stage provides current gain compensation. The opamp is a multiple terminal
and internally compensated device. The opamp amplifies the difference between the two input signals
and generate a single output.
The opamps are used extensively in electronic systems such as radio communication, medical
electronics instrumentation and in mathematical computations such as addition, subtraction,
multiplication, integration, differentiation, logarithmic and anti-logarithmic operations and in many
signal processing applications.
The IC 741 is a widely used all- bipolar general purpose opamp.
Circuit symbol of an Operational amplifier

The circuit schematic of an opamp is in the form of a triangle, as shown in Fig. 1. The device
has two input terminals and one output terminal. The terminal marked (-) is called the inverting input
terminal and the terminal marked (+) is called the non- inverting input terminal. Fig. 2 shows the
opamp with positive voltage supply V+ and a negative voltage supply V- terminals.
BLOCK DIAGRAM
An operational amplifier generally consists of three stages, namely, i) a differential amplifier
ii) additional amplifier stages to provide the required voltage gain and DC level shifting and an iii)
emitter-follower or source- follower output stage to provide current gain and low output resistance.
The input stage is the dual input balanced output differential amplifier. This stage generally
provides most of the voltage gain of the amplifier and establishes the input resistance of the op-amp.
The intermediate stage is dual input unbalance output. The final stage is a push pull complimentary
amplifier output stage. The output stage increases the output voltage swing and raises the current
supplying capability of the opamp.
Ideal opamps exhibits electrical characteristics:

infinite voltage gain, infinite input resistance, zero output resistance, infinite bandwidth, infinite
CMRR and infinite slew rate.
a) Voltage Follower Waveforms
Design:
The circuit is in non-inverting mode

𝑅
Gain , A = 1 + 𝑅𝑓 Gain is unity for a buffer
𝑖
So, Rf / Ri = 0 ; Rf = 0
b) Non-inverting Amplifier
Design:
𝑅
Gain of the inverting amplifier, A = 1 + 𝑅𝑓
𝑖
For a gain of 11, Rf / Ri = 10
Take Ri = 1k. Then, Rf = 10 x 1k = 10k
Experiment No. 5
OPERATIONAL AMPLIFIER CIRCUITS 1
Aim
To design and setup the following operational amplifier circuits

a) Voltage follower
b) Non- inverting amplifier
c) Inverting amplifier
d) Adder
Opamp IC 741 - 1
Resistors - 1k
10k (3 nos.)
Function generator
CRO
Principle
a) Voltage Follower
The voltage follower is a special case of the non- inverting amplifier. The output voltage is
equal to the input voltage both in magnitude and phase. Since the output voltage follows the input
voltage, this circuit is called a voltage follower, source follower, unity gain amplifier, buffer amplifier
or an isolation amplifier. It offers very high input impedance of the order of MΩ and very low output
impedance. Therefore, this circuit draws very small current from the input. Thus, the voltage follower
can be used as a buffer between a high impedance source and a low impedance load for impedance
matching applications.
b) Non- inverting amplifier

This circuit provides a gain to the input signal without any change in the polarity. The gain
of the non- inverting amplifier is given by the expression
𝑅
A = 1 + 𝑅𝑓
𝑖
where Rf is the feedback resistance and Ri is the input resistance.
c) Inverting Amplifier
This is one of the most popular opamp circuits. The polarity of the input voltage gets
inverted at the output. If a sine wave is fed to the input of this amplifier, the output will be an
amplified sine wave with 180o phase shift. The gain of the inverting amplifier is given by the
expression,
−𝑅
A= 𝑅𝑓
𝑖
where Rf is the feedback resistance and Ri is the input resistance. Inverting amplifier can be used as
a scale changer because by varying either Rf or Ri , the amplitude of the output can be varied.
c) Inverting Amplifier
Design:
Gain of the inverting amplifier, A = -Rf / Ri

For a gain of -10, Rf / Ri = 10
Take Ri = 1k. Then, Rf = 10 x 1k = 10k
d) Adder
Design:
The circuit is in inverting mode

Gain , A = - Rf / Ri
For unity gain , Rf = Ri = 10k
d) Adder
The adder is also called a summing amplifier. The output of this circuit is the linear addition
of a number of input signals. It is proportional to the sum of the input signals. In other words, the
output signal is the sum of all the inputs multiplied by their associated gains. It can be expressed as
VO = V1Av1 + V2Av2 + … + VnAvn
where Av1, Av2, … , Avn are the individual gains. The summing amplifier may have equal gain for all
the inputs, and then it i8s referred to as an equal- weighted configuration. It may also be inverting or
non- inverting.
The advantage of this method of summation of signals is that a very large number of inputs
can be added together, thus requiring only one additional resistor for each additional input with
individual gain controls.
Procedure
With the help of the bread board, setup the voltage follower circuit first.. Feed a 2 V (peak to
peak), 1kHz sine wave and observe the input and output simultaneously on the CRO. Verify the
output. Repeat the above procedure for inverting amplifier, non- inverting amplifier and adder
configurations.
Take care to switch off the input signal sources before switching off the power supply to the
IC 741.
d) Adder
Result
The given Opamp circuits were designed and setup and output waveforms were verified.
Circuit Diagram
Specifications of BFW 10/ BFW 11
VDSmax : 30V
VGSmax : 30V
Pmax : 300mW
IDmax : 20mA / 10mA
Thevenin equivalent of the amplifier

Experiment No. 6
FET SOURCE FOLLOWER AMPLIFIER
Aim
To design and setup a source follower amplifier and to measure it's voltage gain, current gain,
input impedance and output impedance.
BFW 10 - 1
Resistors - 1.5k
10k (2 Nos.)
47k
1.5M
5M
Capacitors - 0.1 μF (2 Nos.)
Function Generator,
CRO
DMM
Principle
The source follower amplifier has a voltage gain almost equal to (slightly less than) unity.
Output voltage is in phase with the input voltage. Any change in the input voltage produces an almost
equal and in phase change at the source. It seems that the source follows the input. Hence the name
source follower. It has very high input impedance and low output impedance. This amplifier is
analogous to BJT emitter follower.
From equivalent circuit it can be seen that,
𝐴𝑣 𝑉2 𝑅02
𝑉01 =
𝑅01 + 𝑅0
𝐴𝑣 𝑉2 𝑅02
𝑉02 =
𝑅02 + 𝑅0
𝑉01 − 𝑉02
𝑅0 =
𝑉 𝑉
(𝑅02 − 𝑅01 )
02 01
Design
Let the DC conditions assumed be

VDD = 6V ; ID = 2mA
VDS = 50% of VDD
VRS = 50% of VDD
VRS = 0.5 x 6 = 3V
ID x RS = 3
3
RS = 2𝑥10−3 = 1.5kΩ
Assume VGS = -1.5V and current through R1 and R2 as 1μA.

VR2 = VRS + VGS = 3 – 1.5 = 1.5V
𝑉𝑅2 1.5
R2 = = 1𝑥10−6 = 1.5MΩ
𝐼𝑅2
VR1 = VDD – VR2 = 6 – 1.5 = 4.5V

𝑉𝑅1 4.5
R1 = = 1𝑥10−6 = 4.5MΩ ≈ 5MΩ
𝐼𝑅1
Observations
DC Conditions:
Parameter VDD (V) VGS (V) VDS (V) VRS (V) VR1 (V) VR2 (V)
Designed values
Observed values
Source Follower:
V1 (V) V2 (V) VNL (V) V01 (V) V02 (V)

Procedure
Checking the DC conditions

Connect the FET, resistors R1, R2, RS and the DC source as in figure. Adjust the DC voltage
to 6V (VCC). Measure the voltages VDS, VGS, VR1, VR2, and VRS . See that they agree with the designed
values.
After checking the DC conditions, assemble the rest of the circuit. Apply the AC signal as
specified in the figure. Measure the voltages V1 and V2. Measure the output voltage without
connecting any resistance across the output. This is VNL. Connect R01 and R02 alternately and measure
V01 and V02 respectively.
Observe the input and output voltage signals on a CRO and observe the phase difference.
Calculate voltage gain, current gain, input impedance and output impedance.
Calculations
V1 = ; V2 = ; R = 10kΩ
𝑉1 −𝑉2
I1 = ( )
𝑅
𝑉
Input Impedance = 𝐼2 =
1
No load output voltage, VNL = ;

𝑉𝑁𝐿
Voltage gain = =
𝑉2
𝑉
Output current, Io = 𝑅01 ;
01
𝐼
Current gain = 𝐼0
1
(𝑉01 −𝑉02 )
Output Impedance, R = 𝑉02 𝑉01
−
𝑅02 𝑅01
Result
Designed and setup a source follower amplifier circuit and the following parameters were
obtained.
Voltage gain =
Current gain =
Input impedance =
Output impedance =
Circuit Diagram
Design
Output requirements
VO = 5.6V , IL = 10mA When input is in the range 103V
Select 5.6V Zener
PO = 0.25W , VZ = 5.6V , IZmax = 45mA , IZmin = 5mA
Design of load resistor, RL

𝑉
RL = 𝐼 𝑂
𝐿𝑚𝑖𝑛
VO = VZ. For a load regulation from 5mA to 15mA, ILmin = 5mA.
5.6
RL =5𝑥10−3 = 1.12k
Design of RS
𝑉 −𝑉𝑍 7−5.6
Rsmin = 𝐼 𝑖𝑛𝑚𝑖𝑛 = (15+5)𝑥10−3 = 70Ω
𝐿𝑚𝑎𝑥+𝐼 𝑍𝑚𝑖𝑛
𝑉𝑖𝑛𝑚𝑎𝑥 −𝑉𝑍 13−5.6

Rsmax = 𝐼 = (5+45)𝑥10−3 = 148Ω
𝐿𝑚𝑖𝑛 +𝐼𝑍𝑚𝑎𝑥
Take Rsmin < Rs < Rsmax
Rs = 120Ω
Power dissipation by Rs = Ismax2 x Rs = (ILmin + IZmax)2 x Rs = ((5 + 45)x10-3)2 x 120 = 0.3W
Take Rs = 120Ω, 0.5W
Experiment No. 7 A
ZENER VOLTAGE REGULATOR
Aim
To design and test a Zener diode shunt regulator and to plot its line and load regulation
characteristics
Zener Diode - 5.6 V

Resistor - 1200.5 W
Rheostat - 500, 1.2A (2 Nos.)
Voltmeter - 0 – 10V
Ammeter - 0 – 25mA
Principle
A zener diode is an ordinary diode when forward biased and it is specially designed diode
when reverse biased. It’s reverse break down zener voltage VZ remain constant irrespective of current.
Resistor limits zener current below it’s maximum current.
IS = IZ + IL
where IL is the current through load resistor RL. Values of Rs must be properly selected to fulfill
coarse distribution required. When input voltage increases, IL remains the same and IS and IZ
decreases. But if IZ falls below a minimum zener current (IZmin ), regulation will be lost and output
voltage decreases.
Procedure
Circuit is assembled in the bread board. Keep line current constant at 10mA and vary the input
voltage from 7V to 13V. Note the output voltage. Plot line regulation graph with Vin along X- axis
and VO along Y- axis. Keep input voltage constant at 10V. Note down output voltage for various
values of line current from 5mA to 15mA by varying the load rheostat. Plot load regulation graph
with IZ along X- axis and VO along Y- axis.
Observations
(a) Line regulation IL = 10mA
Vin (V) VO (V)
(b) Load regulation Vin = 10V
IL (mA) VO (V)
Result
The zener voltage regulator was designed and tested and plotted the line and load regulation
characteristics.
Circuit Diagram
Design
Output requirements
VO = VZ – VBE
Take VZ = 5.6V
Take VBE = 0.7V
VO = 5.6 – 0.7 = 4.9V
IL = 100 mA
Design of load resistor, RL

𝑉
RL = 𝐼 𝑂
𝐿𝑚𝑖𝑛
VO = 4.9V. For a load regulation from 50 mA to 100 mA, ILmin = 50mA.
4.9
RL =50𝑥10−3 = 98 (Use 100 rheostat)
Design of RS
𝑉 −𝑉𝑍 13−5.6
RS = 𝑖𝑛𝑚𝑎𝑥 = 5𝑥10−3= 1480Ω
𝐼 𝑍𝑚𝑖𝑛
RS = 1.5kΩ (std)
Power dissipation by Rs = IZmin2 x RS
= (5 x10-3)2 x 1500 = 0.0375W
Take RS = 1.5kΩ, 250 mW
Experiment No. 7 B
SERIES VOLTAGE REGULATOR
Aim
To design and test a transistor series regulator and to plot its line and load regulation
characteristics
Transistor - SL100
Zener Diode - 5.6 V
Resistor - 1.5k250 mW
Rheostat - 100, 1A
Voltmeter - 0 – 10V
Ammeter - 0 – 250mA
Principle
A series voltage regulator works on the principle of a variable resistance in series with the
unregulated supply source and the load. The series pass element must change its resistance according
to the load current and line voltage variations to maintain a constant load voltage. A BJT working in
linear or ohmic region can act as the series element.
The base-emitter voltage of a transistor is typically 0.7V. The base voltage is kept constant by
means of a zener diode. As the output voltage tend to drop due to increased load current, the emitter
voltage of the transistor decreases, and the base-emitter voltage increases. This leads to increased
collector current, that flows to the load, bringing back the output voltage to normal. With a decrease
in load current, the output voltage tends to increase. This reduces the base-emitter voltage and biasing
of the transistor, thereby reducing the collector current and hence the output voltage returns to the set
value.
Procedure
Circuit is assembled in the bread board. Keep line current constant at 50 mA and vary the
input voltage from 6V to 10V. Note the output voltage. Plot line regulation graph with V in along X-
axis and VO along Y- axis. Keep input voltage constant at 8V. Note down output voltage for various
values of line current from 50 mA to 100 mA by varying the load rheostat. Plot load regulation graph
with IZ along X- axis and VO along Y- axis.
Observations
(a) Line regulation IL = 50 mA
Vin (V) VO (V)
(b) Load regulation Vin = 8V
IL (mA) VO (V)
Result
The series voltage regulator using transistor was designed and tested and plotted the line and
load regulation characteristics.
a) Differentiator
Design
1
Let T = 1ms. fa = = 1kHz.
2𝜋𝑅𝑓 𝐶1
1
Assuming C1 = 0.1μF, Rf = 2𝜋1000𝑥0.1x10−6 = 1.59k ≈ 1.5k
For effective differentiation, the time period of the input signal, T >> RfC1
i.e, fb = 10fa = 10kHz
1 1
fb = 2𝜋𝑅 𝐶 . Then, R1 = 2𝜋10x103 𝑥0.1x10−6= 159Ω ≈ 150Ω
1 1
R1C1 = RfCf. Then, Cf = 0.01μF
Rcomp = R1||Rf = R1 (since Rf >> R1); Rcomp = 150Ω
Experiment No. 8
OPERATIONAL AMPLIFIER CIRCUITS 2
Aim
To design and setup the following operational amplifier circuits

a) Differentiator
b) Integrator
c) Comparator
d) Schmitt Trigger
Opamp IC 741 - 1
Resistors - 150 Ω (2 nos.)
1k
1.5k
3.9k
10k (2 nos.)
15k (2 nos.)
150k
Capacitors - 0.1 μF
0.01 μF
Pot - 4.7k
Function generator
CRO
Principle
a) Differentiator
The differentiator circuit can perform the mathematical operation of differentiation, i.e, the
output voltage is the differentiation of the input voltage. This operation is very useful to find the rate
at which a signal varies with time. The ideal differentiator may be constructed from a basic inverting
amplifier, if the resistor R1 is replaced by a capacitor C1. When compared to integrator circuits, the
differentiator circuits are more susceptible to noise. The input noise fluctuations of small amplitudes
will have large derivatives. When differentiated these noise fluctuations will generate large noise
signals at the output, which will introduce a poor signal- to- noise ratio. This problem may be
minimized by placing resistor in series with the input capacitor this modified circuit differentiates
only low frequency signals with a constant high frequency gain.
b) Integrator
Design
If input frequency is 10 times fa, then it results in 99% accuracy.

Let f = 1kHz. So, fa = f /10 = 100Hz
1
fa = 2𝜋𝑅 𝐶 = 100
𝑓 𝑓
Let Cf = 0.01μF. Then,
1
Rf = 2𝜋100𝑥0.01x10−6= 159k ≈ 150k
𝑅
At fa, gain ≈ 𝑅𝑓
1
𝑅𝑓
≈ 10; R1 = 15k
𝑅1
In a differentiator circuit, the limitations due to noise stability and input impedance can pose
problems. In order to minimize noise and aid in stability, a small capacitor may be place in parallel
with Rf, which reduces the high frequency gain. In order to place a lower limit on the input impedance,
a resistor may be placed in series with the differentiation capacitor. The addition of either component
will limit the upper range of differentiation.
b) Integrator
A circuit in which the output voltage waveform is the time integral of the input voltage
waveform is called the integrator or integrating amplifier. In order to achieve integration, the basic
inverting amplifier configuration can be used with the feedback element Rf replaced by an capacitors
Cf..
In the ideal integrator circuit, a small DC offset at the input can force the output into saturation.
To avoid this, a resistor is placed in parallel with the integrator capacitor to limit the low frequency
gain. However, this has the undesirable side effect of limiting the useful integration range at high
frequencies.
c) Comparator
A circuit in which the output voltage waveform switches between positive and negative
saturation values according to an input and a reference is called a comparator. The comparator is an
open loop opamp circuit. In open loop condition, when the non-inverting terminal has more potential
compared to the inverting terminal, the output saturates to +Vsat , due to high open loop gain, and
when the non-inverting terminal has less potential compared to the inverting terminal, the output
saturates to -Vsat .
A voltage value approximately in the ±3V range is taken as the reference. A voltage divider
circuit using resistors generate the reference. A pot is provided in the middle of the voltage divider
arrangement to vary the reference. When the input is below the reference, the output saturates to -
Vsat . When input is above it, the output saturates to +Vsat .
d) Schmitt Trigger
A Schmitt trigger is a comparator with hysteresis. It is a bistable multivibrator with dual

threshold. This circuit uses series positive feedback to create hysteresis. In the inverting
configuration, when the inverting terminal (input signal) potential is below that of non-inverting
terminal, the output switches to +Vsat . Due to the positive feedback, the input signal must rise above
the high threshold, (+Vsat / 5) for the output to switch to -Vsat value. Again, due to the positive
feedback, the output remains in that state till the input has less potential than low threshold, ( -Vsat /
5) whereupon the output switches to +Vsat .
(c) Comparator
(d) Schmitt Trigger
Design
Let Vsat = 13V

Let Vhigh = 2.5V and Vlow = – 2.5V be the high and low threshold voltages.
𝑅1
𝑉𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 = ±( .𝑉 )
𝑅1 + 𝑅2 𝑠𝑎𝑡
𝑅1 2.5
Hence, 𝑅 +𝑅 = 13 = 0.192
1 2
Assume R1 = 1kΩ
Thus, R2 = 4.2kΩ Take 3.9kΩ (std)
Procedure
Setup the integrator circuit. Feed a 2V (p-p) square wave of 1 kHz frequency and observe the
output simultaneously. Apply sine wave and triangular wave forms of same frequency and observe
output and input. Repeat the above procedure for differentiator circuit.
Setup the comparator circuit. Apply a 2V (p-p) sine wave of 100 Hz frequency at the inverting
terminal. Observe the output and input simultaneously. Adjust the pot and note the variation in the
duty cycle of the output square wave.
Setup the Schmitt trigger circuit. Apply an 8V (p-p) sine wave of 100 Hz frequency and
observe the output simultaneously.
Take care to switch off the input signal sources before switching off the power supply to the
IC 741.
Result
The given Opamp circuits were designed and setup and output waveforms were verified.
Circuit Diagram
Design
For a frequency of 1kHz,

1
𝑓𝑜 =
2𝛱√6𝑅𝐶
Let C= 0.1F.
1
Then, 𝑅 = 2𝛱√6𝑥1x103 𝑥0.1x10−6= 650
𝑅𝑓
Gain = 29
𝑅𝑖
Let Ri = 1.2k,
Then Rf = 29 Ri = 29 x 1.2k = 33k
Experiment No. 9 A
RC PHASE SHIFT OSCILLATOR
Aim
To design and set up an RC phase shift oscillator using opamp for a frequency of 1 kHz.
Opamp - LM 741 (1 No.)

Resistors - 650 (2 Nos.)
1.2k
33k
Pot - 10k
Capacitor - 0.1F (3 Nos.)
CRO
Principle
The RC phase shift oscillator consists of an opamp as the amplifying stage, three RC cascading
networks as the feedback network. The feedback network provides a fraction of the output voltage
back to the input of the amplifier. The opamp is in the inverting mode. Therefore, any signal which
appears at the inverting terminal is shifted 180o at the output. An additional 180o phase shift is
required for the oscillations as per the Barkhausen criterion is provided by the cascaded RC network.
Thus the total phase around the loop becomes 360o.
The frequency of oscillation is given by
1
𝑓𝑜 =
2𝛱√6𝑅𝐶
The gain of the inverting opamp should be atleast 29 at this frequency. The gain is kept slightly
higher than 29 to ensure that the variation in circuit parameters will not make the loop gain less than
unity and thus the oscillations die out.
For lower frequencies, opamp IC 741 may be used. However, for higher frequencies, CH3187
or ZF351 should be used.
Procedure
Check whether the opamp is in good condition. Set up the circuit on the bread board. Adjust
the pot to get a sine wave of appreciable amplitude. Note down the frequency and amplitude of the
output waveform.
Waveform
Result
An RC phase shift oscillator was designed and set up using opamp and the following results
were obtained:
Time period of waveform =
Peak voltage =
Circuit Diagram
Design
For a frequency of 1kHz

1
𝑓𝑜 =
2π𝑅𝐶
Assuming C= 0.1μF,
R = 1.59kΩ
For sustained amplification,

AV ≥ 3
Thus,
𝑅
1 + 𝑅𝑓≥ 3
𝑖
Rf ≥ 2Ri
Assuming Ri = 10k
Rf ≥ 20k (Use 22k pot)
Experiment No. 9B
WIEN BRIDGE OSCILLATOR
Aim
To design and set up a Wien bridge oscillator using OPAMP for a frequency of 1 kHz.
OPAMP - LM 741 (1 No.)

Resistors - 1.5k (2 Nos.)
10k (1 No.)
Pot - 22k (1 No.)
Capacitor - 0.1F (2 Nos.)
CRO
Principle
The series RC circuit acts as a high pass filter and parallel RC circuit acts as a low pass filter.
Connecting the two, the network forms a very selective frequency dependent band pass filter, with a
very narrow selected frequency, fO . At resonant frequency, the capacitive reactance equals resistance
R. Hence the phase shift between input and output becomes zero.
The frequency of oscillation is given by
1
𝑓𝑜 =
2π𝑅𝐶
The magnitude of output equals one third of the input. For sustained oscillations, the output
must be amplified by a factor of at least 3. Using an OPAMP in non-inverting mode, amplification
can be achieved without any additional phase shift. Gain of a non-inverting amplifier is
𝑅𝑓
𝐴𝑉 = 1 +
𝑅𝑖
Procedure
Check whether the opamp is in good condition. Set up the circuit on the bread board. Adjust
the pot to get a sine wave of appreciable amplitude. Note down the frequency and amplitude of the
output waveform.
Waveform
Result
A Wien Bridge oscillator was designed and set up using opamp and the following results
were obtained:
Time period of waveform =
Peak voltage =
Circuit Diagram
Design
Time period of oscillation, T = 1ms

1+𝛽
𝑇 = 2RCln( )
1−𝛽
𝑅2
where, 𝑅 +𝑅
1 2
Let 0.5 and R2 = 10k. Then, R1 = 10k
Take C = 0.1F
T = 2.2 RC
1𝑥10−3
R = 2.2𝑥0.1𝑥10−6 = 4.7k
Experiment No. 10A
WAVEFORM GENERATION USING OPAMP – SQUARE WAVE
Aim
To design and setup an square wave generator using OPAMP, for a frequency of 1kHz
Opamp - LM 741
Resistor - 4.7k
10k (2 Nos.)
Capacitor - 0.1F
CRO
Principle
At the heart of the astable multivibrator is an inverting opamp comparator. The comparator
uses positive feedback that increases the gain of the amplifier. In a comparator circuit, this offers two
advantages. First, the high gain causes the opamp’s output to switch very quickly from one state to
another and vice-versa. Second, the use of positive feedback gives the circuit hysteresis.
Consider an instant of time when the output voltage, VO = +Vsat. The voltage at the non-
𝑅2
inverting terminal of the opamp is now +Vsat , where 𝑅 +𝑅 . The capacitor, C charges
1 2
exponentially towards +Vsat through the resistor, R. The output voltage remains constant at + Vsat
until vc equals +Vsat . When this happens, the comparator output reverses to –Vsat . Now VC charges
exponentially towards –Vsat, with the same time constant and again the output makes a transition from
– Vsat to +Vsat, when VC equals -Vsat. This repeats on its own.
This is called an astable multivibrator since it has two quasi-stable states. The output remains
in one state for time T1, and then makes an abrupt transition to the second state and remains in that
state for time T2. The cycle repeats itself after time
T = (T1 + T2), where T is the time period of the square wave.
Procedure
Check whether the opamp is in good condition. Set up the circuit on the bread board and
observe the waveforms in CRO.
Waveforms
Result
An astable multivibrator was designed and setup using Opamp. Required waveforms were
observed.
Time period of the waveform =
Amplitude =
Circuit Diagram
Design
𝑅1
Given frequency of oscillation, f = 4𝑅 = 1kHz
3 𝐶𝑅2
2𝑅2
Peak to peak output of ramp, Vo, p-p = 𝑅
1 .𝑉𝑠𝑎𝑡
Let Vo, p-p = 5V and Vsat = 13V
Let R1 = 1k, then R2 = 180
Let C = 0.1F, then R3 = 13k. (Use 12k std.)
Experiment No. 10B
WAVEFORM GENERATION USING OPAMP – TRIANGULAR WAVE
Aim
To set up and study a triangular waveform generator using opamp for 1 kHz frequency
Opamp - LM 741(2 Nos.)

Resistor - 180
Pot - 1k
12k
Capacitor - 0.1F
CRO
Principle
The triangular wave generator consists of two opamps and several passive components. The
opamp A1 forms the comparator with hysteresis, which is a Schmitt trigger. The opamp, A2 forms an
integrator which integrates the output obtained from the Schmitt trigger. The opamp A1 is a two level
comparator whose outputs are determined by Vsat. The square wave output from A1 is applied to the
(-) input of the comparator through a voltage divider network, formed by R1 and R2.
Suppose the output, VO of the comparator A1 is + Vsat initially. The integrator integrates this
to produce a negative going ramp at its output. Hence the voltages at the two ends of the voltage
divider formed by R1–R2 are + Vsat at the output of A1 and – Vsat at the output of A2. At the instant
T1, the negative going ramp reaches a value, -Vramp, the effective value at point P becomes slightly
less than 0V. This switches the opamp A1 to its negative saturation level, -Vsat . With the output of A1
at –Vsat, the opamp A2 starts integrating and increases its output in the positive direction. At the
instant T2, the voltage at P becomes slightly greater than 0V. this switches the output of A1 from –
Vsat to +Vsat. This cycle repeats itself and generates a triangular waveform.
The frequency of the waveform is determined by the RC value of the integrator formed by the
opamp A2 and the saturation voltage levels Vsat of the comparator opamp, A1 and it is found to be
𝑅1
equal to 4𝑅 𝐶𝑅
3 2
Observations
Vsat VO Time Period

(V) (V) (ms)
Designed value 13 5 1
Observed value
Waveforms
Procedure
Check whether the opamps are in good condition. Setup the circuit on bread board. Observe
the output waveform on CRO. Adjust the 12k pot to get an output of appreciable amplitude
Result
A triangular wave generator circuit was setup using opamp and the expected waveform was
obtained from CRO.
Vpeak =
Vsat =
Time period of oscillations =

Circuit Diagram
Design
𝑅1
Given frequency of oscillation, f = 4𝑅 = 1kHz
3 𝐶𝑅2
2R2
Peak to peak output of ramp, Vo, p-p = 𝑅
1 .𝑉𝑠𝑎𝑡
Let Vo, p-p = 5V and Vsat = 13V
Let R1 = 1k, then R2 = 180
Let C = 0.1F, then R3 = 13k. (Use 12k std.)
Use 22k std. pot for variable voltage at pin 3 of integrator
Experiment No. 10C
WAVEFORM GENERATION USING OPAMP – SAWTOOTH WAVE
Aim
To set up and study a sawtooth waveform generator using opamps for 1 kHz frequency
Opamp - LM 741 (2 Nos.)

Resistor - 180
Pot - 1k
12k
22k
Capacitor - 0.1F
CRO
Principle
The sawtooth wave refers to a waveform with its rise time many times longer than
corresponding fall time or vice versa. The triangular wave generator can be modifiedd to produce a
sawtooth waveform.
The triangular wave generator can be converted to a sawtooth wave generator by integrating
a variable dc voltage into the non-inverting terminal of the integrator. This can be done by using a
potentiometer. When the wiper of the pot is at the center, the output will be triangular wave since the
duty cycle is 50%. If the wiper moves towards -V, rise time becomes longer than fall time. If it moves
towards +V, fall time becomes more than rise time.
Procedure
Check whether the opamps are in good condition. Setup the circuit on bread board. Observe
the output waveform on CRO. Adjust the pots to get an output of required frequency and very low
fall time (10% of time period)
Observations
Vsat Vpeak Time Period Rise Time Fall Time

(V) (V) (ms) (ms) (ms)
Designed
13 3 1 0.9 0.1
value
Observed
value
Waveforms
Result
A triangular wave generator circuit was setup using opamp and the expected waveform was
obtained from CRO.
Vpeak =
Vsat =
Time period of oscillations =
Rise time =
Fall time =
Pin Diagram of 555 Timer
Functional Diagram of 555 IC

555 Timer
The 555 timer is one of the most versatile linear ICs. It is a monolithic timing circuit that can
produce accurate and highly stable time delays or oscillation. Like general purpose opamps, it is very
reliable, easy to use and cheaper in cost. It has a variety of applications including monostable and
astable multivibrators, DC - DC converters, digital logic probes, waveform generators, analog
frequency meters and tachometers, temperature measurement and control devices, voltage regulators
etc. the timer basically operates either as a monostable or as an astable multivibrator.
The 555 timer operates from a wide range of power supplies (+5 V to +18 V), sinking or
sourcing 200 mA current. Proper selection of only a few external components allows timing intervals
of several minutes or frequencies as high as several kilohertz. It also has a high current output, which
can drive TTL ICs. It has an adjustable duty cycle.
555 Timer PIN Configuration
The 555 IC is available as an 8 pin PDIP as shown in fig.1. The IC consists of 23 transistors,
2 diodes and 16 resistors. The terminals of the IC can be explained as:
Pin 1: Grounded Terminal: All voltages are measured with respect to this terminal.
Pin 2: Trigger Terminal: This pin is an inverting input to a comparator that is responsible for the
transition of the flip- flop from set to reset. The output of the timer depends on the amplitude of the
external trigger pulse applied to this pin.
Pin 3: Output Terminal: Output of the timer is available at this pin. There are two ways in which a
load can be connected to the output terminal: either between pin 3 and ground pin or between pin 3
and supply pin the load connected between pin 3 and ground supply pin is called normally on load
and that connected between pin 3 and ground pin is called normally off load.
Pin 4: Reset Terminal: To disable or reset the timer, a negative pulse is applied to this pin due to
which it is referred to as reset terminal. When this pin is not to be used for reset purpose, it should be
connected to +VCC to avoid any possibility of false triggering.
Pin 5: Control Voltage Terminal: The function of this terminal is to control the threshold and trigger
levels. Thus, either the external voltage or a pot connected to this pin determines the pulse width of
the output waveform. The external voltage applied to this pin can also be used to modulate the output
voltage waveform. When this pin is not used it should be connected to ground through a 0.01μF
capacitor, to avoid any noise problem.
Pin 6: Threshold Terminal: This is the non- inverting input terminal of comparator 1, which
compares the voltage applied to this terminal, with a reference voltage, +2/3 VCC. The amplitude of
the voltage applied to this terminal is responsible for the set state of the flip- flop.
Pin 7: Discharge Terminal: This pin is connected internally to the collector of the transistor and
mostly a capacitor is connected between this terminal and the ground. This pin is called the discharge
terminal because, when the transistor saturates, the capacitor discharges through the transistor. When
the transistor is cut- off the capacitor charges at a rate determined by the external resistance and
capacitor.
Pin 8: Supply Terminal: A supply voltage of +5V to +18V is applied to this terminal with respect to
the ground.
FUNCTIONAL DIAGRAM OF THE 555 TIMER
Block diagram of the 555 timer is shown in fig.2. As shown in the diagram, It consists of two
comparators, an RS flip flop, two transistor and a resistive network.
The resistive network consists of three equal resistors and acts as a voltage divider.
Comparator 1 compares the threshold voltage with a reference voltage of +2/3 VCC, while Comparator
2 compares the trigger voltage with a reference of voltage of +1/3 V CC.. Output of both the
comparators is supplied to the flip- flop. The flip- flop assumes its state according t the output of the
two comparators.
One of the two transistors is a discharge transistor of which the collector is connected to pin
7. This transistor saturates or cuts off according to the output state of the flip- flop. The saturated
transistor provides a discharge path to a capacitor connected externally. Base of another transistor is
connected to the Reset terminal. A pulse applied to this terminal resets the whole timer irrespective
of any input.
Working:
Comparator 1 has a threshold input and a control input. In most applications, the control input
is not used, so that the control voltage equals +2/3 VCC. Output of this comparator is applied to Set
(S) input of the flip- flop. Whenever the threshold voltage exceeds the control voltage, comparator1
will set the flip-flop and its output is high. A high output from the flip- flop saturates the discharge
transistor and discharges the capacitor connected externally to pin 7. The complementary signal out
of the flip- flop goes to pin 3, the output. The output available at pin 3 is low. These conditions will
prevail until comparator 2 triggers the flip- flop, even if the voltage at the threshold input falls below
+2/3 VCC, i.e, Comparator 1 cannot cause the flip- flop to change again. It means that the comparator
1 can only force the flip- flop's output high.
To change the output of the flip- flop to low, the voltage at the trigger input must fall below
+1/3 VCC. When this occurs, comparator 2 triggers the flip- flop, forcing its output low. The low
output from the flip0 flop turns the discharge transistor off and forces the power amplifier to output
a high. These conditions will continue independent of the voltage on the trigger input. Comparator 2
can only cause the flip- flop to output low.
A voltage may be applied to the control input to change the levels at which the switching
occurs. When not in use, a 0.01μF capacitor may be connected between pin 5 and ground to avoid
noise coupled onto this pin from causing false triggering.
Circuit Diagram
Design
Let VCC = 10V

Frequency of oscillation = 1kHz
Time period of oscillation = 1ms
For a duty cycle of 60%, charging time tc = 0.6ms and discharging time td = 0.4ms.
tc = 0.693(RA + RB) C
td = 0.693 RB C
Assuming C = 0.1μF,
0.4𝑥10−3
RB = 0.693𝑥0.1𝑥10−6 = 5.772k (Use 5.6k std.)
0.6𝑥10−3
RA + RB = 0.693𝑥0.1𝑥10−6= 8.658k
RA = 8.658 – 5.772 = 2.886k (Use 3k std.)

Choose C1 = 0.01μF
Experiment No. 11 A
ASTABLE MULTIVIBRATOR USING 555 IC
Aim
To design and setup an astable multivibrator using 555 timer IC for a frequency of 1 kHz
and 60% duty cycle
IC 555 - 1
Resistors - 5.6k
3k
Capacitors - 0.01μF
0.1μF
CRO
Principle
In the block diagram of 555 IC, when Q is low, or output Vout is high, the discharging transistor
is cut off and the capacitor, C begins charging towards VCC through the resistors, RA and RB. Hence,
the charging time constant is (RA + RB) C. Eventually, the threshold voltage exceeds +2/3 VCC, the
comparator 1 has high output and triggers the flip- flop so that its Q is high and the timer output is
low. With Q high, the discharge transistor saturates and pin 7 grounds so that the capacitor discharges
through resistance RB with a discharging time constant, RBC. With the discharging of the capacitor
trigger voltage at the inverting input of comparator 2 decreases. When it drops below 1/3 V CC, the
output of comparator 2 goes high and this resets the flip- flop so that Q is low and timer output is high
this proves the auto- transition from low to high and then from high to low. Thus the cycle repeats.
The charging period of the capacitor, tc is 0.693(RA +RB) C and the discharging period of the
capacitor, td is 0.693 RBC. The overall period of oscillations, T is 0.693(RA + RB) C.
Procedure
Setup the circuit on bread board. Switch on the supply. Observe the waveforms at pin numbers
3 and 6 of the IC.
Waveforms
Observations
Charging Time Discharging Time VCC 2 1

VCC VCC
3 3
tc (ms) td (ms) (V)
(V) (V)
Theoretical value 0.6 0.4 10 6.6 3.3
Observed value
Result
An astable multivibrator was designed and setup using the 555 timer IC and the following
observations were made:
Output Waveform:
Maximum value =
Time period for which the output is maximum =
Time period for which the output is minimum =
Capacitor Waveform
Maximum value =
Minimum value =
Charging time, tc =
Discharging time, td =
Circuit Diagram
Design
Let VCC = 10V .

Pulse width = 1ms (given)
Pulse width, T = 1.1 RAC. Let C = 0.1μF
RA = 10k
Design of the triggering circuit:
We have R1C1 ≤ 0.0016Tt , where Tt is the time period of the trigger.

Let Tt = 3ms and C1 = 0.01μF.
Then R1 = 480Ω
Experiment No. 11 B
MONOSTABLE MULTIVIBRATOR USING 555 IC
Aim
To design a monostable multivibrator using 555 timer, for a pulse width of 1 ms
IC 555 - 1
Diode (1N4007) - 1
Resistors - 480Ω
10 k
Capacitors - 0.01μF (2 Nos.)
0.1μF
Function Generator
CRO
Principle
Initially, when the output at pin 3 is low, i.e., the circuit is in a stable state, the transistor is ON
and capacitors C is shorted to the ground. When a negative pulse is applied to pin 2, the trigger input
falls below +1/3 VCC, the output of the comparator goes high, which resets the flip-flop and
consequently the transistor turns off and the output pin 3 goes high. This is the transition of the output
from stable to quasi-stable state. As the discharge transistor is cut off, the capacitor, C begins charging
towards + VCC, through resistance RA, with a time constant equal to RAC. When the increasing
capacitor voltage becomes slightly higher than +2/3 VCC, the output of comparator 1 goes high, which
sets the flip-flop. The transistor goes to saturation, thereby discharging the capacitors, C and the
output of the timer goes low.
Thus the output returns back to stable state from quasi-stable state. The output of the
multivibrator remains low until a trigger pulse is again applied. Then the cycle repeats.
The capacitors, C has to charge through the resistance RA. The larger the time constant, RAC,
the longer it takes for the capacitor to reach +2/3 VCC. In other words, the RC time constant controls
the width of the output pulse. The pulse width can be shown to be approximately equal to 1.1 RAC.
Procedure
Setup the circuit. Switch on the power supply. Use positive square pulses of amplitude VCC
and frequency 300 Hz or lower as the trigger. Observe the waveforms at pin numbers 3 and 6 of the
IC.
Waveforms
Observations
VCC 2 T
VCC
3
(V) (ms)
(V)
Theoretical value 10 6.6 1
Observed value
Result
A monostable multivibrator having pulse width of 1ms was designed and setup and observed
the output.
Output Waveform
Maximum voltage value =
Pulse Width =
Capacitor Waveform
Maximum voltage value =
Pulse Width =
PSPICE – CIRCUIT SIMULATION SOFTWARE
SPICE (Simulation Program for Integrated Circuits Emphasis) is a powerful general purpose
analog and mixed mode (both analog and digital) circuit simulator. This was originally developed at
the Electronics Research Laboratory of the University of California in 1975. PSpice is the PC version
of SPICE developed by Microsim Corp. currently available from OrCAD Corp.
OrCAD is a schematic editor or a program that allows you to draw circuit schematics. PSPICE
is an electrical simulator that allows you to simulate the operation of the circuits whose schematic is
prepared using OrCAD.
The following steps summarize the different steps involved in simulating a circuit with Capture and
Pspice
Step 1: Circuit Creation with Capture
Create a new Analog, mixed AD project

• Double click the OrCAD Capture schematic
• Click on File from the main menu bar and then select New → Project.
• You can then see the following dialog box
• Create a new project using Analog or Mixed Signal Circuit Wizard

• Enter name of project in the space provided. eg. rectifier
• Browse the location where this project is to be stored
Then press OK
To place different types of circuit parts like voltage source, resistance, capacitance, inductance,
diode, MOSFET, ground etc as required in the circuit.
• A schematic page will be opened in the 'Project manager', where you can draw the
circuit diagram.
• Click 'Place' menu toolbar (or Shift P)

• Desired component can be placed after invoking the respective libraries
• To rotate the component and place properly either you can select the component and
press R or right click and select the Rotate button
• Now place this part in the schematic page by clicking the left mouse button. Now
right click the mouse button and select 'End mode' or press Esc key.
• After selecting each part using left mouse button, double click the selected part or
use the right mouse button to edit properties of that part. For eg. To change the
capacitance value
• Similarly you can choose different components needed for your design including
sources and ground. A ground with value 0 (means node 0) is needed in all
designs.
Connect the parts using 'place wire' (shift + W)
Specify values and names of these circuit parts

Step 2: Specify type of simulation
Create a simulation profile. Click on PSpice → New Simulation Profile
Give a name to the simulation.
Select the type of analysis (Transient, AC sweep, DC sweep etc), Run time, step time etc
Run Pspice
Step 3: View the results
1. Add traces to the probe window

2. Use cursors to analyze waveforms
3. Check the output file, if needed
4. Save or print the results
Opamp Inverting Amplifier Circuit
Half Wave Rectifier with filter

Experiment No. 12
SIMULATION OF ANALOG CIRCUITS
Aim
To simulate the following ciruits using Pspice

(i) Opamp Inverting Amplifier
(ii) Half wave rectifier with filter
Principle
The polarity of the input voltage gets inverted at the output. If a sine wave is fed to the input
of this amplifier, the output will be an amplified sine wave with 180o phase shift. The gain of the
inverting amplifier is given by the expression,
−𝑅
A= 𝑅𝑓
𝑖
where Rf is the feedback resistance and Ri is the input resistance. Inverting amplifier can be used as
a scale changer because by varying either Rf or Ri
A half wave rectifier circuit consists of a single diode connected in series with an AC voltage
source and a resistive load. Only during positive half cycle of the input AC, the diode will conduct.
The capacitor connected across the load will smoothen the ripple in the load voltage.
Procedure
1. Draw the circuit as such and give the project name

2. Connect the components using place wire command from the menu
3. Give Amplitude as 1 and Frequency as 1000 for the sine input. Rf = 5k and Ri = 1k for an
gain of 5.
4. Take Pspice toolbar button again. Select New simulation profile. Give a name, and press
'Create' button
5. Select the analysis type as Time domain (Transient) for this case
6. As the input frequency is 1 kHz (T=1ms), it is set to run the simulation at least up to 5ms to
get a good look on the waveform (5 cycles). So choose 'Run to time' as 5ms
7. Also we have to choose a maximum step size. As a thumb rule, select it as 1/1000 of the
'Run to time' seconds
8. Now press OK.
9. Place Differential voltage markers at the required positions.
10. Now select 'Pspice' → 'Run' to run the simulation (or press run button)
11. The waveforms at markers are displayed.
If resolution is poor, take 'Edit simulation profile' and reduce step size. If it takes a long
time to simulate, increase step size
Waveform of Opamp Integrator Circuit
Waveform of Half wave rectifier with filter

Result
The following circuits were simulated using PSPICE and output waveforms obtained
(i) Opamp Inverting amplifiers
(ii) Half wave rectifier with filter

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Dept.

Of Electrical & Electronics Engineering

GOVERNMENT ENGINEERING COLLEGE PALAKKAD

DEPARTMENT OF ELECTRICAL AND ELECTRONICS

ANALOG ELECTRONIC CIRCUITS LAB

S3 Electronic Circuits Lab Manual i

I. Vision, Mission, PEO and PSO ........................................................................... v

S3 Electronic Circuits Lab Manual ii

Department of Electrical & Electronics Engineering

Program Educational Objectives (PEOs)

Program Specific Outcomes (PSOs)

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

S3 Electronic Circuits Lab Manual v

EE 221 ELECTRONIC CIRCUITS LAB

List of Experiments : ( Out of 18 experiments listed, 12 experiments are mandatory)

S3 Electronic Circuits Lab Manual vii

S3 Electronic Circuits Lab Manual viii

EE 221 ELECTRONIC CIRCUITS LAB

1. Use an oscilloscope (CRO or DSO) to view and measure signals

2. Design and develop regulated DC power supplies

3. Analyze amplifier circuits using BJT and JFET

5. Create wave shaping circuits using diodes

6. Prepare simulation models of analog circuits

MAPPING OF COURSE OUTCOME WITH PO

S3 Electronic Circuits Lab Manual ix

GENERAL LABORATORY INSTRUCTIONS

PRECAUTIONS FOR ELECTRICAL SAFETY

01. Wear shoes compulsorily

S3 Electronic Circuits Lab Manual x

1. Write Name of the experiment with number & date.

S3 Electronic Circuits Lab Manual xi

S3 Electronic Circuits Lab Manual xii

EE 221 ELECTRONIC CIRCUITS LAB

1. Study of CRO ……………………………………………………...……….. 1

4. A) Diode clipping circuits ……………………………………..…………… 21

7. A) Zener voltage regulator ……………………...…………….………….… 49

10. A) Waveform generation using OPAMP – Square wave……….…..……..… 71

S3 Electronic Circuits Lab Manual xiii

Block Diagram of Cathode Ray Oscilloscope

Block Diagram of Digital Storage Oscilloscope

S3 Electronic Circuits Lab Manual 1

Components and Equipments Required

S3 Electronic Circuits Lab Manual 2

Phase difference between X plate and Y plate signals,

S3 Electronic Circuits Lab Manual 3

To view and measure signals

To view Lissajous pattern and measure phase difference

S3 Electronic Circuits Lab Manual 4

Fig. 1: Half wave rectifier without filter

Fig. 2: Half wave rectifier with Capacitor filter

Fig. 3: Full wave rectifier without filter

S3 Electronic Circuits Lab Manual 5

RECTIFIERS AND FILTERS

Components and Equipments Required

Diode - BY 127 / 1N4007 (4 Nos.)

Rectifier is a device capable of converting a bidirectional input wave into a unidirectional

S3 Electronic Circuits Lab Manual 6

Fig. 5: Full wave Bridge rectifier with Capacitor filter

Tabulations and Sample Calculations

Half Wave Rectifier without Filter

Sl. Idc Vdc Vm Vrms Ripple Voltage Rectification