EE370A: DIGITAL ELECTRONICS

MODULE-2, LECTURE-3
Dr. Shubham Sahay,
Assistant Professor,
Department of Electrical Engineering,
IIT Kanpur
 STATIC CHARACTERISTICS
➢ Boolean variable: mathematical abstraction.
➢ Represented by electrical quantity i.e. voltage or current.
➢ Voltage/current levels are discretized: 2 nominal voltage levels.
➢ Nominal logic high voltage: VOH, Nominal logic low voltage: VOL
➢ Voltage swing = VOH - VOL
INVERTER
➢ Similar stature as that of amplifiers in analog circuits.
➢ Inverts the logic at the input: logic 0 to 1 and vice versa.
➢ In terms of logic levels: Apply VOH at input, VOL at output and vice versa.
➢ Electrical function: Voltage-transfer characteristics (VTC).
➢ Sweep input voltage and plot output voltage.
➢ Multiple variables: sweep one input and plot output, several possible combinations.
➢ Inverter VTC: VOH = f(VOL), VOL = f(VOH).
➢ Vin = Vout = VM, inverter (gate) switching threshold.
➢ Mid-point of switching characteristics: i/p shorted with o/p, obtained via loadline.
 LOGIC LEVELS
➢ VTC deviates from ideal nominal values.
➢ Noise and o/p not isolated (several devices connected: loading effect).
➢ Regions of acceptable voltage separated by region of uncertainty.
➢ Acceptable voltage range limited by input high VIH and input low voltage VIL
➢ Defined where gain is -1.
➢ Steep transition between VIH and VIL: undefined region.
 NOISE MARGIN
➢ Measure of sensitivity to noise.
➢ Large region of acceptable voltage for logic levels. How large?
➢ Digital circuits: not sensitive to exact value of input if within limit.
➢ VIL: maximum input voltage for which o/p can be inferred as logic high
➢ VIH: minimum input voltage for which o/p can be inferred as logic low
➢ Inherent noise suppression/robustness. VDD VDD

VOH "1"
NMH = VOH - VIH
VIH
Noise Margin High Undefined
Region
Noise Margin Low VIL
NML = VIL - VOL
𝑁𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 VOL
"0"
𝑁𝑀𝐿 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 Gnd Gnd
Gate Output Gate Input
 REGENERATIVE PROPERTY
v0 v1 v2 v3 v4 v5 v6

v1 = f(v0)  v1 = finv(v2)

➢ Function of gate is like an inverter.

➢ Converges to nominal value after few stages.
➢ If its complementary to the inverter, signal converges to intermediate level.
➢ VTC matters: noise does not propagate if regenerative.
➢ Steep transient region with large gain, sandwiched between two legal zones with gain < 1.
➢ VIH and VIL are boundaries between legal and transient zone.
 NOISE IMMUNITY
➢ Noise Margin: Robustness against noise.
➢ Noise immunity: Even with low NM, good noise immunity can be achieved
➢ Designs capable of rejecting noise.
➢ Transfer function between noise source and signal node is <<1.
➢ Only a small fraction is coupled to important nodes.
➢ Noise Sources:
oInternal (coupling): proportional to signal swing/logic swing: g x Vsw
oFixed noise (supply/gnd): f x VNf
of: Transfer function from noise source to the signal node, VNf: Noise amplitude

➢ Noise Margin: 0.5 Vsw (symmetric and largest NM)

𝑉𝑠𝑤
➢ 𝑉𝑁𝑀 = ≥ σ𝑖 𝑓𝑖 𝑉𝑁𝑓𝑖 + σ𝑗 𝑔𝑗 𝑉𝑠𝑤
2

2 σ𝑖 𝑓𝑖 𝑉𝑁𝑓𝑖
➢ 𝑉𝑠𝑤 ≥
1−2 σ𝑗 𝑔𝑗

➢ Large Signal/logic swing: minimizes impact of fixed noise. 6

➢ If g is large, increasing signal swing does not help.
 DIRECTIVITY
➢ Unidirectional gates.
➢ No coupling of output signal to any unchanging input signal.
➢ Real designs: feedback (CGD of MOSFETs)
➢ Design to minimize coupling: change in output reflects as input noise.

FAN-IN

➢ Number of inputs to any gate.

➢ Large Fan-in: complex design
➢ Bigger and slower M
➢ Typically divided into number of stages.
➢ Design of stages and allocation of inputs is tricky.
 FAN-OUT
➢ Number of load gates connected to output of a driving gate.
➢ Loading effect: capacitance increases at output node.
➢ Speed and logic levels may also change
➢ Ideally, large input resistance and small output resistance N
➢ Maximum fan-out specified in libraries to ensure correct
static and dynamic operation

IDEAL DIGITAL GATE Fan-out N

➢Infinite gain in the transition region

➢Switching threshold located in the middle of the logic swing
g=
➢High and low noise margins equal to half the swing
➢Input and output impedances of infinity and zero, respectively
➢Unlimited Fan-out
➢Static CMOS inverter: pretty close.
 PERFORMANCE: COMPUTATIONAL ABILITY
➢ FLOPS or number of instructions per second.
➢ Architecture (parallelism) and design of circuit.
➢ Duration of clock period
➢ Signal propagation time through gate, time for
data I/O in registers and clock uncertainty.
➢ Propagation delay: How quickly gate responds
to change in inputs.
➢ Related to delay experienced by a signal when it
passes through the gate.
➢ Measured between 50% transition point of
input and output. Why 50%?
➢ Different response time for rising and falling
waveforms: Two different propagation delays.
➢ tpHL: response time for high to low transition of
output.
𝒕𝒑𝑯𝑳 + 𝐭 𝐩𝐋𝐇
➢ tpLH: response time for low to high transition of 𝒕𝒑 =
output. 𝟐