DESIGN AND IMPLEMENTATION OF 8 BIT VEDIC

MULTIPLIER

BATCH-C3:
UNDER THE GUIDANCE OF:
P.NAGARJUNA
Dr.P.Suresh Kumar M.Tech..,Ph.D.
Y19EC151
Associate Professor
CONTENTS:

➢ Abstract
➢ Aim
➢ Objective
➢ Introduction
➢ Literature Survey
➢ Existing Methods
➢ Proposed Methodology
➢ Tool And It’s Features
➢ References

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 Abstract:
• This project anticipate the design of a novel Vedic multiplier using the
techniques of Ancient Indian Vedic Mathematics that have been modified
to improve performance.

• In this paper, we are proposing an 8-bit multiplier using the new

methodology of Vedic Mathematics called the Urdhva-Tiryagbhyam sutra,
which is used for generating partial products.

• From various multiplication techniques, the Urdhva-Tiryagbhyam sutra is

being implemented because this sutra is applicable to all cases of
algorithms for N x N bit numbers and the minimum delay is obtained.

• A 4 x 4 Vedic multiplier will be designed using a 9-full adders and a special

4-bit adder which has reduced delay. Then an 8-bit multiplier will be
designed using four 4-bit multipliers and a 3-ripple carry adder.

• Then the 8 x 8 Vedic Multiplier will be coded in Verilog, synthesized,

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and
simulated using Xilinx ISE8.2 Software
AIM:

➢ To design a high speed 8 bit multiplier

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OBJECTIVE:

▪ The Vedic method shows effective methods of implementation of multiplication for

higher bits for the science and engineering field.
▪ The hardware architecture of 8x8 multiplier is dependent on Urdhva Tiryagbhyam

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Introduction:

➢ The multiplication is an important process in mathematics.

➢ The multiplication process is carried out in many digital processors

like microprocessors, microcontroller and many processors.

➢ Multipliers and adders play a vital role in determining the

performance of FIR filter.

➢ Multipliers play a major role in today’s digital signal processing

and various other applications. Both signed and unsigned
multiplications are required in many computing applications

➢ The regular methods for multiplication may require more area or

delay.
➢ The ancient vedic mathematical formulas can be used in order
to achieve less area and delay .

➢ The methodology for vedic multiplication using Urdhva

Tiryagbhyam sutra, based on ancient vedic mathematics.

➢ The architectures are based on different implementation

methods such as full adders,special adder,carry look a head .

➢ This work proposes the design of efficient signed multiplier

using vedic mathematics

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➢ The process of multiplication by using Urdhva Tiryagbhyam
sutra is as follows, First step is to multiply the first digit that
is left hand most digit of multiplicand with first digit of
multiplier. The product is written as first digit in the answer.
➢ In second step multiply second digit of multiplicand with first
digit of the multiplier and first digit of the multiplicand with
second digit of multiplier, add the product.
➢ The result is written as second digit in the answer.
➢ Third step is to multiply second digit of multiplicand with
second digit of multiplier, write the product as third digit in
the answer 8
EXAMPLE:

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LITERATURE SURVEY:

1) Raj Kumari, Rajesh Mehra, “Power and Delay Analysis of CMOS Multipliers Using
Vedic Algorithm”, 1st IEEE ICPEICES-2016.

• A Vedic multiplication algorithm is designed by using Vedic mathematics formula

Urdhava Tiryakbhya method means vertically and cross wise, which gets less time
delay compared to other algorithms

2)Dravik Kishor Bhai Kahar, Harsha Mehta, “High-Speed Vedic Multiplier using Vedic
Mathematics”, ICICCS, 2017

•An efficient high performance 64-bit MAC unit (Multiplier-and-Accumulator) is

presented which is designed using Vedic multiplier using URDHVA-TIRYAKBHYAM
sutra.

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EXISTING METHOD:

➢ The block diagrams of Vedic Multiplier proposed previously and

that proposed in this paper are shown in figures.

➢ In previously proposed multiplier of figure , to implement the three

4-bit adders, ripple carries adders were used.

➢ But the limitation associated with ripple carry adder is that, the
sum and carry outputs of a stage will depend on the carry output
from the previous stage.

➢ This delay adds up for three stages greatly increasing the

propagation delay.
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Fig. 2: Block diagram of previously proposed 8 bit
multiplier using ripple carry adders:

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PROPOSED METHODOLOGY:

➢ In the proposed multiplier of figure 3, ripple carry adders are

replaced by carrying look-ahead adders.

➢ In the latter adder, the output from a stage depends only on the
input carry, Cin and not on the carry outputs from the previous
stages.

➢ Thus, the propagation delay is reduced in comparison with the

ripple carry adders.

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Fig. 3: Block diagram of proposed 8x8 Vedic Multiplier

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Block diagram of 4 bit Vedic multiplier:

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Special adder:

➢ In the figure A,B,C,D are four inputs.C0 and C1 are LSB and MSB of
carry outputs respectively and Sum is the sum of four inputs.
➢ The Boolean expressions for the same are given below.
➢ Sum= A XOR B XOR C XOR D
➢ C0= ((NOT B) AND D)OR (C AND (NOT D))OR (B AND (NOT C))
➢ C1= A AND B AND C AND D.
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Tool Used:

➢ We are using xillinx 12.7 in this project

➢ Xilinx is an American technology

and semiconductor company that primarily
supplied programmable logic devices. The
company was known for inventing the first
commercially viable field-programmable gate
array (FPGA) and creating the first fabless
manufacturing mode

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Features of Xilinx:

❖ A free, downloadable PLD design environment for both

Microsoft Windows and Linux!

❖ The industry's fastest timing closure with Xilinx Smart Compile

technology

❖ Integrated Verilog verification with the Lite version of the ISE

Simulator (ISim)

❖ The easiest, lowest cost way to get started with the industry
leader for productivity, performance, and power

❖ Easily upgrade able to any of the ISE Design Suite Editions

from the Xilinx Online Store.
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REFERENCES:

1) Raj Kumari, Rajesh Mehra, “Power and Delay Analysis

of CMOS Multipliers Using Vedic Algorithm”, 1st IEEE
ICPEICES-2016.

2) C. Selvakumari, M. Jeyaprakash, A. Kavitha,

“Transistor Level Implementation of an 8-bit Multiplier
Using Vedic Mathematics in 180nm Technology”, 2016
IEEE.

3) Dravik Kishor Bhai Kahar, Harsha Mehta, “High-Speed

Vedic Multiplier using Vedic Mathematics”, ICICCS,
2017.
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THANK YOU

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