STR Y6735 STR 6753 STR Y6754 STR Y6763 STR Y6765 STR Y6766 Application Note

Application Information
STR-Y6700 Series Quasi-Resonant Off-Line Switching Regulators
General Description
The STR-Y6700 series products comprise a power MOSFET

and a multifunctional monolithic integrated circuit (MIC)
controller designed for controlling switch mode power supplies.
The quasi-resonant mode of operation, coupled with the
bottom-skip function, allows high efficiency and low noise at
low to high operational levels, while burst oscillation mode
ensures minimum power consumption at standby. In order to
sustain low power consumption under low load and in standby
mode, the controller has built-in startup and standby circuits.
The compact 7-pin full mold package (TO-220F-7L) reduces
board space by requiring a minimum of external components,
thus simplifying circuit design. This IC, including various Figure 1. STR-Y6700 series packages are fully molded SIPs, A
protection functions, is an excellent choice for standardized, copper heat dissipation heatsink can be mounted at the rear surface
compact power supplies. of the case.
Features and Benefits • Protection functions

• TO–220F–7L package ▫ Overcurrent protection (OCP): pulse by pulse basis, low
• Lead (Pb) free compliance dependence on input voltage
• The built-in startup circuit reduces the number of external ▫ Overload protection (OLP): latched shutoff*
components and lowers standby power consumption ▫ Overvoltage protection (OVP): latched shutoff*
• Multi-mode control allows high efficiency operation ▫ Maximum on-time limitation
across the full range of loads ▫ Thermal shutdown protection (TSD): latched shutoff*
• Auto burst oscillation mode for standby mode, for
improving low standby power at no load: input power *Latched shutoff means the output is kept in a shutoff mode
< 30 mW at 100 VAC and < 50 mW at 230 VAC for protection, until reset.
• Bottom-skip mode minimizes switching loss at medium to
low loads The product lineup for the STR-Y6700 series provides the
following options:
• Built-in soft start function reduces stress applied to the
incorporated power MOSFET and peripheral components MOSFET
Part POUT
• Step-on burst oscillation minimizes transformer Number VDSS(min) RDS(on)(max) (W)*
audible noise (V) (Ω)
• Built-in leading edge blanking (LEB) function eliminates VIN = 100 VAC
STR–Y6735 500 0.8
external filter components 120
• Built-in Bias Assist function enables stable startup VIN = VIN =
operation 380 VDC Universal
• VCC operational range expanded STR–Y6753 1.9 100 60
650
• Internal power MOSFET is avalanche energy guaranteed; STR–Y6754 1.4 120 67
two-chip structure STR–Y6763 3.5 80 50
STR–Y6765 800 2.2 120 70
STR–Y6766 1.7 140 80
*Based on the thermal rating; the allowable maximum output
power can be up to 120% to 140% of this value. However, maxi-
mum output power may be limited in such an application with low
output voltage or short duty cycle.
STR-Y6700-AN Rev. 2.0

Functional Block Diagram
STR-Y6700 Pin List Table

MIC D/ST Name Number Function
3 Startup 1
VCC 1 D/ST MOSFET drain and Startup circuit input
DRV MOSFET source and overcurrent detection signal

UVLO
2 S/OCP
input
Reg/Iconst 3 VCC Control circuit power supply input
OCP/BS 2
S/OCP 4 GND Ground
Latch
Logic
NF Constant Voltage Control signal input, Standby
7 5 FB/OLP
FB/STB control, and overload detection signal input
OLP 5
Bottom Detection signal input, Input Compensation
OSC FB/OLP 6 BD
detection signal input
BD 6 For stable operation, connect to GND pin, using
BD 7 NF
4 the shortest possible path
GND
Table of Contents
Package Diagram 3 BD Pin Blanking Time 14
Bottom Skip Quasi-Resonant Operation 15
Electrical Characteristics 4
Auto Standby with Burst Oscillation Function 17
Absolute Maximum Ratings 4
Protection Functions 18
MOSFET Electrical Characteristics 4
Undervoltage Lockout Function (UVLO) 18
MIC Electrical Characteristics 5
Overvoltage Protection Function (OVP) 18
Typical Application Circuit 6 Overload Protection Function (OLP) 18
Functional Description 7 Thermal Shutdown (TSD) 19
Startup Operation 7 Overcurrent Protection Function (OCP) 19
Startup Period 7 Overcurrent Input Compensation Function 19
Bias Assist Function 8 BD Pin Peripheral Components Value Selection
Auxiliary Winding 8 Reference Example 22
Soft Start Function 10 When Overcurrent Input Compensation is
Operational Mode at Startup 10 Not Required 22
Constant Voltage Control Operation 11 Overcurrent Detection Threshold Voltage 22
Quasi-Resonant Operation and Bottom-On Timing 12 Maximum On-Time Limitation Function 23
Quasi-Resonant Operation 12 Design Notes 24
Bottom-On Timing 12 External Components 24
RBD1 and RBD2 Setup 13 Transformer Design 24
CBD Setup 13 Phase Compensation 26
Circuit Trace Layout 26
Allegro MicroSystems, Inc.

115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A. STRY6700-AN
1.508.853.5000; www.allegromicro.com
Package Diagram
TO-220F-7L package, Leadform No. LF 3051
10 ±0.2 4.2 ±0.2
2.8 +0.2
Gate Burr 2.6 ±0.2
（5.6）
3.2 ±0.2
15 ±0.3
STR （1.1）
a
2.6±0.1
b (Measured at
pin base)
5±0.5
5±0.5
7-0.62 ±0.15
10.4 ±0.5
R-end R-end
+0.2
7-0.55 -0.1
+0.2
5×P1.17±0.15 0.45 -0.1 2.54±0.6
2 ±0.15
＝5.85±0.15 (Measured at (Measured at
(Measured at (Measured at 5.08±0.6
pin base) pin tip) pin tip)
pin base)
(Measured at
pin tip)
0.5 0.5 0.5 0.5

(max) (max) (max) (max)
(Front view) (Side view)

1 2 3 4 5 6 7
Pin material: Cu a. Product name label: Y67××

Pin treatment: Solder dip b. Lot #:
Product weight: Approximately1.45 g First letter, year manufactured: last number of year
Unit: Millimeters (mm) Second letter, Month manufactured:
Note: "Gate Burr" shows area where 0.3 mm (max.) Jan. to Sep.: 0 to 9
gate burr may be present October: O
November: N
December: D
Third and fourth letters: Date manufactured: 01 to 31
Fifth letter: Sanken control number
Pin treatment Pb-free. Device composition

compliant with the RoHS directive.

3
Electrical Characteristics
• These data are from the STR-Y6763 which is representative of the series, except as noted.
• The polarity value for current specifies a sink as "+ ," and a source as “−,” referencing the IC.
• Please refer to the datasheet of each product for additional details.
Absolute Maximum Ratings Unless specifically noted, TA = 25°C and VCC = 20 V

Characteristic Symbol Notes Pins Rating Unit
Drain Current1 IDPEAK Single pulse 1–2 6.7 A
Maximum Switching Current1 IDMAX TA = −20°C to 125°C 1–2 6.7 A
Single pulse, VDD = 99 V, L= 20 mH,
Single Pulse Avalanche Energy1 EAS 1–2 60 mJ
ILPEAK= 2.3 A
Input Voltage in Control Part (MIC) VCC 3–4 35 V
Startup (D/ST) Pin Voltage VSTARTUP 1–4 −1.0 to VDSS V
OCP Pin Voltage VOCP 2–4 −2.0 to 6.0 V
FB Pin Voltage VFB 5–4 −0.3 to 7.0 V
FB Pin Sink Current IFB 5–4 10.0 mA
BD Pin Voltage VBD 6–4 −6.0 to 6.0 V
With an infinite heatsink 1–2 19.9 W
Power Dissipation in MOSFET1 PD1
Without heatsink 1–2 1.8 W
Power Dissipation in Control Part (MIC) PD2 – 0.8 W
Internal Frame Temperature in Operation2 TF – −20 to 115 °C
Operating Ambient Temperature TOP – −20 to 115 °C
Storage Temperature Tstg – −40 to 125 °C
Channel Temperature Tch – 150 °C
1Please
refer to each individual product datasheet for details.
2Recommended internal frame temperature is T = 105°C (max).
F
Electrical Characteristics of MOSFET Unless specifically noted, TA = 25°C and VCC = 20 V

Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit
Voltage Between Drain and Source1 VDSS 1–2 800 – – V
Drain Leakage Current IDSS 1–2 – – 300 μA
On-Resistance1 RDS(on) 1–2 – – 3.5 Ω
Switching Time1 tf 1–2 – – 250 ns
Thermal Resistance1,2 Rθch-F – – 2.8 3.2 °C/W
1Please refer to each individual product datasheet for details.
2Thermal resistance between a channel of the MOSFET and the internal leadframe.

4
Electrical Characteristics of Control Part (MIC) Unless specifically noted, TA = 25°C and VCC = 20 V
Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit
Power Supply Startup Operation
Operation Start Voltage VCC(ON) 3–4 13.8 15.1 17.3 V
Operation Stop Voltage1 VCC(OFF) 3–4 8.4 9.4 10.7 V
Circuit Current in Operation ICC(ON) 3–4 – 1.3 3.7 mA
Circuit Current in Non-Operation ICC(OFF) VCC = 13 V 3–4 – 4.5 50 μA
Startup Circuit Operation Voltage VSTART(ON) 1–4 42 57 72 V
Startup Current ICC(STARTUP) VCC = 13 V 3–4 −4.5 −3.1 −1.0 mA
Startup Current Supply Threshold
VCC(BIAS) 3–4 9.5 11.0 12.5 V
Voltage1
Operation Frequency fOSC 1–4 18.4 21.0 24.4 kHz
Soft Start Operation Duration tSS 1–4 – 6.05 – ms
Normal Operation
Bottom-Skip Operation Threshold
VOCP(BS1) 2–4 0.487 0.572 0.665 V
Voltage 1
Bottom-Skip Operation Threshold
VOCP(BS2) 2–4 0.200 0.289 0.380 V
Voltage 2
Quasi-Resonant Operation Threshold
VBD(TH1) 6–4 0.14 0.24 0.34 V
Voltage 12
Quasi-Resonant Operation Threshold
VBD(TH2) 6–4 – 0.17 – V
Voltage 22
Maximum Feedback Current IFB(MAX) 5–4 −320 −205 −120 μA
Standby Operation
Standby Operation Threshold Voltage VFB(STBOP) 5–4 0.45 0.80 1.15 V
Protected Operation
Maximum On-Time tON(MAX) 1–4 30.0 40.0 50.0 μs
Leading Edge Blanking Time tON(LEB) 1–4 – 470 – ns
Overcurrent Detection Threshold
VOCP(H) VBD = 0 V 2–4 0.820 0.910 1.000 V
Voltage (Normal Operation)
Voltage (Input Compensation in VOCP(L) VBD = –3 V 2–4 0.560 0.660 0.760 V
Operation)
VOCP(La.OFF) 2–4 1.65 1.83 2.01 V
Voltage (Latched shutoff)
BD Pin Source Current IBD(O) VBD = –3 V 6–4 −250 −83 −30 μA
OLP Bias Current IFB(OLP) 5–4 −15 −10 −5 μA
OLP Threshold Voltage VFB(OLP) 5–4 5.50 5.96 6.40 V
OVP Threshold Voltage VCC(OVP) 3–4 28.5 31.5 34.0 V
FB Pin Maximum Voltage in Feedback
VFB(MAX) 5–4 3.70 4.05 4.40 V
Operation
Thermal Shut Down Temperature TJ(TSD) – 135 – – °C
1The relation of VCC(BIAS) > VCC(OFF) is maintained in each product.
2The relation of V
BD(TH1) > VBD(TH2) is maintained in each product.

5
Typical Application Circuit
L1
D1 T1 D3 VOUT
VAC
P
C1 R6
PC1 R3
R7
C6
S R4 C8
U1
C7 R5
D2 R2 U2
STR-Y6700 R8
C2 D
FB/OLP
S/OCP
GND
D/ST
GND
VCC
BD
NF
2
DZBD
1 2 3 4 5 6 7
RBD1
CV
R1
RBD2
ROCP CBD
C4 C3 PC1
C5
The NF pin (No. 7) should be connected to the GND pin (No. 4), which
should be at a stable ground potential, to ensure stability of operation.

6
Functional Description
All of the parameter values used in these descriptions are typical
values, unless they are specified as minimum or maximum.
With regard to current direction, "+" indicates sink current
(toward the IC) and "–" indicates source current (from the IC).
Startup Operation
Startup Period
Typical D/ST and VCC pin peripheral circuits are shown in fig-
ure 2. This IC has a built-in Startup circuit which is connected to
the D/ST pin.
VCC
The Startup Current, ICC(STARTUP) = –3.1 mA, is constant-current
controlled inside the IC. When the electrolytic capacitor C2, con-
nected to the VCC pin, is fully charged and the VCC pin voltage
rises to the Operation Start Voltage, VCC(ON) = 15.1 V, the IC
Control Part (MIC) starts operation.
After switching operation begins, the startup circuit automatically
turns off (shuts off) to zero its current consumption.
The startup time is determined by the rating of C2, which is usu- Figure 2. D/ST and VCC pin peripheral circuits
ally in the range of 10 to 47 μF.
The approximate value of the startup time is calculated by the
following formula:
VCC(ON) – VCC(INT)
tSTART = C2 × (1)
|ICC(STARTUP)| ICC
where:
I CC(ON) = 3.7mA
tSTART is the startup time in s, and (max)
VCC(INT) is the initial voltage of the VCC pin in V. Start

Stop
Figure 3 shows the relation of the VCC pin voltage versus the
circuit current, ICC . When the VCC pin voltage reaches the
Operation Start Voltage, VCC(ON) = 15.1 V, the Control Part (MIC)
starts operation and the circuit current increases. The voltage from
the auxiliary winding (D in figure 2) becomes a power source to 9.4 V 15.1 V VCC pin voltage
the Control Part after operation start. The turns ratio of auxiliary VCC(OFF) VCC(ON)
winding D must be adjusted so that the VCC pin voltage becomes
the following range in the power supply specification for input
and output deviation: Figure 3. VCC versus ICC
VCC(BIAS)(max) < VCC < VCC(OVP)(min) (2)
12.5 (V) < VCC < 28.5 (V)

An auxiliary winding voltage of approximately 20 V is recom-
mended.

7
Bias Assist Function VCC
Figure 4 shows the VCC voltage behavior during the startup pin voltage
period. When VCC pin voltage reaches VCC (ON) = 15.1 V, the IC IC startup Startup success
Control Part (MIC) starts operation. Because of the relationship Target
VCC(ON) = Operating
of the turns ratios of the auxiliary winding D and of the primary 15.1 V Voltage
winding, the voltage through D does not rise to the target operat-
ing voltage immediately. After the IC starts, the VCC voltage VCC(BIAS) =
11.0 V
starts dropping. If it reaches VCC (OFF) = 9.4 V, the IC Control Part VCC(OFF) = Bias Assist period
(MIC) would be stopped by the UVLO (Undervoltage Lockout) 9.4 V
circuit, a startup failure would be caused, and the IC would revert Startup failure
to the state before startup.
In order to prevent this, during a state of operating feedback con-
trol (the FB/OLP pin voltage is the Standby Operation Threshold
Voltage, VFB(STBOP) = 0.80 V or less), when the VCC pin voltage Time (t)
falls to the Startup Current Supply Threshold Voltage, VCC(BIAS) =
11.0 V, the Bias Assist function is activated. While the Bias Assist Figure 4. VCC during startup period
function is operating, the decrease of the VCC voltage is sup-
pressed by a supplementary current from the Startup circuit.
By the Bias Assist function, the use of a small value C2 capacitor
is allowed, resulting in improved response for OVP (Overvolt- VCC Without R2
pin voltage
age Protection). Also, because the increase of VCC pin voltage
becomes faster when the output runs with excess voltage, the
response time of the OVP function can also be shortened. It is
necessary to check and adjust the process so that poor starting
conditions may be avoided.
With R2
Auxiliary Winding
In actual power supply circuits, there are cases in which the VCC IOUT
pin voltage fluctuates in proportion to the output of the SMPS
Figure 5. VCC versus IOUT with and without resistor R2
(see figure 5). This happens because C2 is charged to a peak volt-
age on the auxiliary winding D, which is caused by the transient
surge voltage coupled from the primary winding when the power
MOSFET turns off.
D2 R2
For alleviating C2 peak charging, it is effective to add some value
R2, of several tenths of ohms to several ohms, in series with D2 3
(see figure 6). The optimal value of R2 should be determined VCC Added D
using a transformer matching what will be used in the actual STR-Y6700
application, because the proportion of the VCC pin voltage versus C2
the transformer output voltage differs according to transformer GND
structural design. 4
Figure 6. VCC pin peripheral circuit with R2

8
Bobbin
Barrier
P1 S1 P2 S2 D
The variation of VCC pin voltage becomes worse if:
• The coupling between the primary and secondary windings of Barrier
the transformer gets worse and the surge voltage increases (low
Pin Side
output voltage, large current load specification, for example).
• The coupling of the auxiliary winding, D, and the secondary Winding structural example (a)
side stabilization output winding (winding of the output line
P1, P2 Primary side winding
which is controlling constant voltage) gets worse and it is sub-
S1 Secondary side winding from
ject to surge voltage. which the output voltage is
In order to reduce the influence of surge voltages on the VCC pin, controlled constant
alternative structures of the auxiliary winding, D, can be used. S2 Secondary side winding
Two alternatives are shown in figure 7. D Auxiliary winding for VCC
• Winding structural example (a): Separating the auxiliary wind-

ing D from the primary side windings P1 and P2. Bobbin
P1 and P2 are the windings which divide the primary side wind- Barrier
ing into two.
• Winding structural example (b): Structure which improves cou- P1 S1 D S2 S1 P2
pling of the secondary side stabilization output winding S1 and
the auxiliary winding, D.
Barrier
Of two output windings S1 and S2, the output winding S1 is a
stabilized output winding, controlled to constant voltage. Pin Side
Winding structural example (b)
Figure 7. Winding structural examples

9
Soft Start Function Operational Mode at Startup
Figure 8 shows the waveforms of operation at startup. The soft As shown in figure 8, because the auxiliary winding voltage is
start operation period, tSS , is internally set to 6.05 ms, and the low at startup, there is a certain period when the quasi-resonant
overcurrent protection (OCP) threshold voltage steps up in four signal has not yet reached regulation level (Quasi-Resonant
steps during this period. This reduces the voltage and current Operation Threshold Voltage 1, VBD(TH1) , is 0.24 V or more, and
stress on the incorporated MOSFET and on the secondary-side the effective pulse width for the quasi-resonant signal is 1.0 μs
rectifier. or more). During this period, the operation is in PWM operation
at an operation frequency of fOSC = 21.0 kHz. Then, when output
During the soft start operation period, the operation is in
voltage rises, the auxiliary winding voltage will rise, and when
PWM operation, at an internally set operation frequency,
a quasi-resonant signal reaches a regulated level, quasi-resonant
fOSC = 21.0 kHz. In addition, because the soft start operation
operation will begin.
period is fixed internally, it is necessary to confirm and adjust the
VCC pin voltage and the OCP delay time during startup.
Startup Target Operating Voltage

VCC pin voltage
VCC(ON)
VCC(OFF)
Quasi-resonant
Time PWM operation operation
BD pin voltage A
VBD(TH1)
Time Pulse width1.0 μs (min)

BD pin waveform
MOSFET Expanded at point A
Drain current
ID
Time
Soft-Start tSS=6.05 ms
Operation mode
Quasi-resonant operation
PWM operation
㧔fOSC= 21.0 kHz㧕
Figure 8. Operational mode at startup

10
Constant Voltage Control Operation
For enhanced response speed and stability, current mode control
(peak current mode control) is used for constant voltage control of
STR-Y6700
the output voltage. S/OCP GND FB/OLP
Referring to figure 9, this IC compares the voltage, VR1 , of a cur- 2 4 5
rent detection resistor and target voltage, VSC , with the internal
PC1
FB comparator, and controls them so that the peak value of VR1
VR1 ROCP IFB
gets close to VSC . C3
VSC is determined by the voltage of the FB/OLP pin (refer to

figures 9 and 10).
• In the case of light load. If the load becomes light, the feedback Figure 9. FB/OLP pin feedback circuit
current (IFB) of the secondary side error amplifier will increase
along with the rise of output voltage. FB/OLP pin voltage falls
by detecting this current through a photocoupler. For the above
reason, because the target voltage VSC falls, it causes the value Target voltage
of VR1 to fall. As a result, the peak value of the drain current
decreases and suppresses the rise of output voltage. + VSC
• In the case of heavy load. When the load becomes heavy, the - VR1
converse occurs with respect to light load operation: the target
voltage VSC of the FB comparator will become high, and the FB comparator S/OCP voltage
㧔R OCP voltage㧕
peak value of the drain current increases and suppresses the
decrease of the output voltage. Drain Current,
Also, generally, because of the steep surge current which occurs ID
when the power MOSFET turns on, the FB comparator and
overcurrent protection circuit (OCP) may respond, and the power
Figure 10. ID and FB comparator operation during
MOSFET may turn off. normal operation
In order to prevent this phenomenon, the IC has a leading edge
blanking time, tON(LEB) = 470 ns, from the moment of the power
MOSFET turn on, which keeps it from responding to the drain tON(LEB)
current surge. Please refer to each individual product datasheet
about tON(LEB) . V 'OCP(H)
As shown in figure 11, when the power MOSFET turns on, if the
drain current surge pulse width is large, the following adjustments
are required so that the surge pulse width falls within tON(LEB) .
• Match the turn-on timing to a VDS bottom point.
• Lower the rating of the voltage resonant capacitor, CV , and the Surge at MOSFET turn on
rating of the capacitor in the secondary side snubber circuit.
V'OCP(H) of figure 11 is the overcurrent detection threshold voltage Figure 11. S/OCP pin voltage
after input compensation.

11
Quasi-Resonant Operation and Bottom-On are reduced and it is possible to obtain converters with high
Timing efficiency and low noise. This IC performs bottom-on operation
not only during normal quasi-resonant operation, but also during
bottom-skip quasi-resonant operation. This allows reduction of
Quasi-Resonant Operation
the operation frequency during light-load conditions, to improve
Figure 12 shows the circuit of a flyback converter. A flyback
efficiency across the full range of loads.
converter is a system which transfers the energy stored in the
transformer to the secondary side when the primary side power Bottom-On Timing
MOSFET is turned off. After the energy is completely trans- Figure 14 shows the voltage waveform of the BD pin peripheral
ferred to the secondary, when the MOSFET keeps turning off, the circuit and auxiliary winding, D. The following setup is required
MOSFET drain node begins free oscillation based on the LP of with the BD pin:
the transformer and CV across the drain and source pins.
1. Bottom-on timing setup (described here, below).
The quasi-resonant operation is the VDS bottom-on operation that
turns-on the MOSFET at the bottom point of VDS free oscillation. 2. OCP input compensation value setup (refer to OCP section for
description).
Figure 13 shows an ideal VDS waveform during bottom-on
The components DZBD, RBD1, RBD2, and CBD, are connected to
operation.
the BD pin peripheral circuit as shown in figure 14, with values
Using bottom-on operation, switching loss and switching noise that are determined with above-mentioned steps 1 and 2.
Vf
NP T1 NS D3 t ONDLY (half cycle of free oscillation)
VOUT LP  CV
E FLY
LP tONDLY zP
EIN P S IOFF C6
ID
E FLY
C1
VDS
CV
E IN
0
Bottom
Point
Figure 12. Basic flyback converter circuit IOFF
EIN Input voltage 0
EFLY Flyback voltage (EFLY = (NP / NS) × (VO + Vf)
NP Primary side number of turns
NS Secondary side number of turns
ID
VOUT Output voltage
Vf Forward voltage drop of the secondary side rectifier 0
ID Drain current of power MOSFET
IOFF Current which flows through the secondary side rectifier tON
when power MOSFET is off
CV Voltage resonant capacitor Figure 13. Ideal bottom-on operation waveform (MOSFET turn-on at a
LP Primary side inductance bottom point of a VDS waveform)

12
This delay time for bottom-on, from the start of VDS free oscilla- RBD1 and RBD2 Setup
tion to the timing of turning-on the power MOSFET, is created by
RBD1 and RBD2 must set the range for the quasi-resonant signal:
exploiting the auxiliary winding voltage, which synchronizes to
VBD(TH1) = 0.34 V (max) or more under input and output con-
the drain voltage VDS waveform.
ditions where VCC becomes lowest, but less than the absolute
Referring to figure 14, either end of RBD1 and RBD2 subtracts maximum rating of the BD pin, 6.0 V , under conditions where
the forward voltage drop, Vf , of DZBD from the flyback voltage, VCC becomes highest.
Erev1, of the auxiliary winding, D.
Figure 21 defines the pulse width of the quasi-resonant signal. For
The quasi-resonant signal, Erev2 , is the voltage of the BD pin initiating quasi-resonant operation, the quasi-resonant signal pulse
biased RBD2 by Erev1. The delay time, tONDLY , of Erev2 is required width between the two points VBD(TH1) and VBD(TH2) must be
to be adjusted by CBD after the other component values have 1.0 μs or more. The recommended value of Erev2 is about 3.0 V.
been set.
CBD Setup
After the power MOSFET turns off, the quasi-resonant signal
immediately goes up and it exceeds the Quasi-Resonant Opera- The delay time, tONDLY , after which the power MOSFET turns on,
tion Threshold Voltage 1, VBD(TH1) = 0.24 V. After this occurs, is adjusted by the value of CBD , so that the power MOSFET turns
the power MOSFET remains off until the quasi-resonant sig- on at the bottom-on of VDS.
nal comes down enough to cross the Quasi-Resonant Opera-
tion Threshold Voltage 2, VBD(TH2) = 0.17 V. Then the power To do so, observe the power MOSFET drain voltage, VDS, the
MOSFET again turns on. In addition, at this point, the threshold drain currnet, ID, and the quasi-resonant signal, under the maxi-
voltage goes up to VBD(TH1) automatically to prevent malfunction mum input voltage and the maximum output power, as shown in
of the quasi-resonant operation from noise interference. figure 13.
Clamping Snubber
T1
P
EIN C1
EIN EFLY
D2 R2
Auxiliary
Winding E rev1
CV Voltage
E rev1 Efw1
C2 VD 0
1 3
D/ST D E fw1
VCC
DZBD Forward Voltage
STR-Y6700
Flyback voltage
RBD1 3.0 V recommended,

6 㨠ON
but less than 6.0 V acceptable
BD
2 S/OCP GND Quasi-resonant
signal,
4 Erev2 V BD(TH1)
CBD RBD2 Erev2 V BD(TH2)
ROCP
0
Figure 14. BD pin peripheral circuit (left) and auxiliary winding voltage and flyback voltage timing (right)

13
The following show how to adjust the turn-on point: BD Pin Blanking Time
Figure 17 shows two different BD pin waveforms, comparing
• If the turn-on point precedes the bottom of the VDS signal (see
transformer coupling conditions between the primary and second-
figure 15), it causes higher switching losses. In that situation,
ary winding. The poor coupling tends to happen in a low output
after confiming the initial turn-on point, delay the turn-on point
voltage transformer design with high NP/ NS turns ratio (NP
by increasing the CBD value gradually, so that the turn-on will
and NS indicate the number of turns of the primary winding and
match the bottom point of VDS.
secondary winding, respectively), and it results in high leakage
• In the converse situation, if the turn-on point lags behind the inductance. The poor coupling causes high surge voltage ring-
VDS bottom point (see figure 16): it causes higher switching ing at the power MOSFET drain pin when it turns off. That high
losses also. After confirming the initial turn-on point, advance surge voltage ringing is coupled to the auxiliary winding and then
the turn-on point by decreasing the CBD value gradually, so that the inappropriate quasi-resonant signal occurs.
the turn-on will match the bottom point of VDS .
An initial reference value for CBD is about 1000 pF.
Free oscillation, fR
1
fR ≈
2P LP  CV
Early turn-on point Delayed turn-on point
V DS 0 V DS 0
Bottom Bottom
point point
IOFF 0 I OFF 0
ID 0 ID 0
ｔON ｔON
V BD(TH1) V BD(TH1)
V BD(TH2) V BD 0 VBD(TH2)
VBD 0
Auxiliary Auxiliary
Winding Winding
Voltage Voltage
VD 0 VD 0
Figure 15. When the turn-on of a VDS waveform Figure 16. When the turn-on of a VDS waveform
occurs before a bottom point occurs after a bottom point

14
The BD pin has a blanking period of 250 ns (max) to avoid the In addition, the BD pin waveform during operation should be
IC reacting to it, but if the surge voltage continues longer than measured by connecting test probes as short to the BD pin and
that period, the IC responds to it and repeatedly turns the power the GND pin as possible, in order to measure any surge voltage
MOSFET on and off at high frequency. This results in an increase correctly.
of the MOSFET power dissipation and temperature, and it can be
damaged.
The following adjustments are required when such high fre- Bottom Skip Quasi-Resonant Operation
quency operation occurs:
In order to reduce switching losses during light to medium load
• CBD must be connected near the BD pin and the GND pin
conditions, in addition to quasi-resonant operation, the bottom
• The circuit trace loop between the BD pin and the GND pin skip function is built in, to limit the rise of the power MOSFET
must be separated from any traces carrying high current operation frequency. This function monitors the power MOSFET
• The coupling of the primary winding and the auxiliary winding drain current (in fact, the S/OCP pin voltage), and during heavy
must be good load conditions it automatically changes to normal quasi-resonant
• The clamping snubber circuit (refer to figure 14) must be ad- operation, and during light to medium loads, it changes to bottom
justed properly. skip quasi-resonant operation.
Normal Waveform
(Good coupling)
VBD(TH1)= 0.24V
VBD(TH2)= 0.17V
Erev2
Inappropriate Waveform
(Poor coupling)
V BD(TH1)= 0.24V
VBD(TH2)= 0.17V
Erev2
BD pin blanking time

250ns（max）
Figure 17. The difference of BD pin voltage waveform by the coupling condition of
the transformer; good coupling (top) versus inappropriate coupling (bottom)

15
Figure 18 shows the operation state transition diagram of the width (see figure 21) will narrow. Also, the peak value of the S/
output load from light load to heavy load. Figure 19 shows the OCP pin voltage decreases. When load is reduced further and
state transition diagram from heavy load to light load. (In these the S/OCP pin voltage falls to VOCP(BS2) , the mode is changed to
diagrams, the amplitude of the S/OCP pin is shown without input one bottom-skip quasi-resonant operation. This suppresses the
current compensation, and thus the OCP threshold voltage is rise of the MOSFET operation frequency.
VOCP(H) = 0.910 V.) As shown in figure 20, in the process of the increase and decrease
This IC has a built-in automatic multi-mode control which of load current, hysteresis is imposed at the time of each opera-
changes among the following three operational modes according tional mode change. For this reason, the switching waveform
to the output loading state: auto standby mode, one bottom-skip does not become unstable near the threshold voltage of a change,
quasi-resonant operation, and normal quasi-resonant operation. and this enables the IC to switch in a stable operation.
• The mode is changed from one bottom-skip quasi-resonant

operation to normal quasi-resonant operation (figure 18), when
load is increased from one bottom-skip operation, the MOSFET
peak drain current value will increase, and the positive pulse Bottom-Skip Quasi-resonsant
width (see figure 21) will widen. Also, the peak value of the V OCP(H)
VOCP(BS1)
S/OCP pin voltage increases. When the load is increased further
and the S/OCP pin voltage rises to VOCP(BS1) , the mode is
changed to normal quasi-resonant operation. Normal Quasi-Resonant
• The mode is changed from normal quasi-resonant operation to VOCP(BS2)
Load
one bottom-skip quasi-resonant operation (figure 19), when load Current
is reduced from normal quasi-resonant operation, the MOSFET
peak drain current value will decrease, and the positive pulse Figure 20. Hysteresis at the time of an operational mode change
(Light Load) One Bottom-Skip Quasi-Resonant Normal Quasi-Resonant (Heavy Load)
VDS
S/OCP VOCP(H)= 0.910V

pin voltage V OCP(BS1)= 0.572V
Figure 18. Operation state transition diagram from light load to heavy load conditions
(Heavy Load) Normal Quasi-Resonant One Bottom-Skip Quasi-Resonant (Light Load)
V DS
S/OCP V OCP(H)= 0.910V

pin voltage
V OCP(BS2)= 0.289V
Figure 19. Operation state transition diagram from heavy load to light load conditions

16
In order to perform stable normal quasi-resonant operation and efficiency is improved under light load conditions.
one bottom-skip operation, it is necessary to ensure that the pulse
width of the quasi-resonant signal is 1 μs or more under the con- Generally, a burst interval is set to several kilohertz or less, in
ditions of minimum input voltage and minimum output power. order to improve the efficiency during light loads. When the burst
The pulse width of the quasi-resonant signal, Erev2 , is defined oscillation frequency is in the human audible range (20 Hz to
as the interval between VBD(TH1) = 0.34 V (max) on the rising 20 kHz), audible noise may occur from the transformer.
edge, and VBD(TH2) = 0.27 V (max) on the falling edge of the
This IC keeps the peak drain current low during burst oscillation
pulse. Figure 21 shows the quasi-resonant signal waveform pulse
width definitions. mode, and suppresses the audible noise of the transformer further
by enabling the step-on burst oscillation function, which expands
the pulse width gradually.
Auto Standby with Burst Oscillation Function
During the transition stage to burst oscillation mode, if the VCC
The auto standby function automatically changes the IC operation
pin voltage falls to the Start-up Current Supply Threshold Volt-
mode to standby mode, with burst oscillation, when the MOSFET
age, VCC (BIAS) = 11.0 V, the Bias Assist function will operate and
drain current, ID, decreases during light loads.
supply the starting current ICC(STARTUP) . This stops the fall of the
The S/OCP pin circuit monitors ID . When the S/OCP pin voltage VCC pin voltage and enables stable standby operation.
falls to the standby state threshold voltage (about 9% compared
to VOCP(H) = 0.910 V) , the auto standby function changes the IC In addition, because the power consumption of the IC will
to standby mode (figure 22). Also, during standby mode, when increase when the Bias Assist function operates during normal
the FB/OLP pin voltage falls below VFB(STBOP) , the IC stops operation (which includes burst oscillation mode periods), an
switching operation, and the burst oscillation mode will begin. adjustment of the peripheral circuit is required to make the VCC
During burst oscillation mode, because switching operation has pin voltage higher than VCC (BIAS) , by adjusting the turns ratio of
a certain interval of off-time, switching losses are reduced and the transformer, and minimizing R2, as shown in figure 6.
Erev2 E rev2
VBD(TH1)= 0.34V(MAX) VBD(TH1)= 0.34V(MAX)
VBD(TH2)= 0.27V(MAX) VBD(TH2)= 0.27V(MAX)
Pulse Width Pulse Width

S/OCP pin voltage 1.0μs or more
S/OCP pin voltage 1.0μs or more
Figure 21. The pulse width of a quasi-resonant signal; normal operation (left) and one bottom-skip operation (right)
SMPS Output Burst Oscillation

Current, IOUT
VOCP(H) approximately 9%
S/OCP pin voltage related to
the drain current, ID
Below several kHz
Normal Operation Standby Operation Normal Operation
Figure 22. Auto Standby mode timing

17
Protection Functions tion stops, the VCC pin voltage will begin to fall, and when it
reaches VCC(BIAS) = 11.0 V, the Bias Assist function will oper-
Undervoltage Lockout Function (UVLO) ate. When the Bias Assist function operates, the Startup Current,
In operation, when the VCC pin voltage decreases to VCC(OFF) = ICC(STARTUP) , will be supplied to the VCC pin, and prevent VCC
9.4 V (typ), the Control Part (MIC) stops operation, by activat- pin voltage from falling to the Operation Stop power-supply volt-
ing the UVLO (Undervoltage Lockout) circuit, and reverts to the age, VCC(OFF) = 9.4 V, and the latched state is maintained. Releas-
state before startup (see figure 23). ing the latched state is done by turning off the input voltage and
by dropping the VCC pin voltage below VCC(OFF).
Overvoltage Protection Function (OVP) Because the VCC pin voltage is proportional to the output volt-
When the voltage between the VCC pin and GND pin exceeds age, when supplying VCC pin voltage from the auxiliary wind-
the OVP Operation power-supply voltage, VCC(OVP) = 31.5 V, ing of the transformer, excess voltage on the secondary side is
the overvoltage protection function (OVP) operates and stops detectable (such that the output voltage detection circuit is open).
switching operation in latch mode. When the switching opera- In this case, the approximate value of the secondary side output
voltage at the time of overvoltage protection operation can be
calculated by the following formula:
ICC
ICC(ON) (max)
VOUT(normal operation)
= 3.7mA VOUT(OVP) = × 31.5 (V) (3)
VCC(normal operation)
Overload Protection Function (OLP)
Figure 24 shows the waveform of the IC when the overload pro-
Startup
Stop
tection function is active.

When an overload state (the state where overcurrent protection,
OCP, operation has limited the peak drain current value) occurs,
the output voltage will decline and the error amplifier on the
9.4 V 15.1 V VCC pin voltage secondary side cuts off. When the error amplifier cuts off, the
VCC(OFF) VCC(ON)
capacitor C4 connected to the FB/OLP pin will be charged, and
go up to the maximum voltage during feedback control, VFB(MAX)
Figure 23. ICC versus VCC at start and stop
VCC pin voltage Bias assist

Latch release
VCC(BIAS)
VCC(OFF)
FB/OLP pin voltage Charge by IFB(OLP)

VFB(OLP)= 5.96V STR-Y6700
VFB(MAX)= 4.05V
GND FB/OLP
tDLY
4 5
IFB PC1
ID R1
C3
C4
Figure 24. Operation waveform at the time of OLP operation (left) and peripheral circuit (right)

18
= 4.05 V. Then, C4 is charged by feedback current IFB(OLP) = nected to the VCC pin. In this case, the charge time is determined
–10 μA. When the FB/OLP pin voltage reaches the OLP Thresh- by the startup current from the startup circuit, while the discharge
old Voltage, VFB(OLP) = 5.96 V, the overload protection circuit will time is determined by the current supply to the internal circuits of
operate and stop switching operation. Switching operation will be the IC.
stopped in latch mode at the time of overload protection opera-
tion. Releasing the latched state is done by turning off the input Thermal Shutdown (TSD)
voltage and by dropping the VCC pin voltage below VCC(OFF). When the temperature of the Control Part (MIC) reaches the
Thermal Protection Threshold Temperature, TJ(TSD) = 135°C
The time of the FB/OLP pin voltage from VFB(max) = 4.05 V
(min), the thermal protection function (TSD) operates and switch-
to VFB(OLP) = 5.96 V is defined as the OLP Delay Time, tDLY.
ing operation is stopped in latch mode. Releasing the latched state
Because the capacitor C3 for phase compensation is small com-
is done by turning off the input voltage and by dropping the VCC
pared to C4, in the case of IFB(OLP) = –10 μA, the approximate
pin voltage below VCC(OFF).
value of tDLY is determined by the following formula:
(VFB(OLP) – VFB(MAX) ) × C4 Overcurrent Protection Function (OCP)
tDLY ≈ | IFB(OLP) |
(4)
The overcurrent protection function (OCP) detects the peak drain
(5.96 (V) – 4.05 (V) ) × C4 current value of the incorporated power MOSFET by means of
≈ | –10 μA |
the current detection resistor ROCP , between the S/OCP pin and
ground (see figure 27). When the voltage drop of ROCP reaches
In the case of C4 = 4.7 μF, the value of tDLY would be approxi-
the Overcurrent Detection Threshold Voltage (Normal Opera-
mately 0.9 s. The recommended value of R1 is 47 kΩ.
tion), VOCP(H) = 0.910 V, the power MOSFET turns off and the
To enable the overload protection function to initiate an auto- output power is limited (pulse by pulse basis).
matic restart, 220 kΩ is connected between the FB/OLP pin and
Overcurrent Input Compensation Function
ground, as a bypass path for IFB(OLP) , as shown in figure 25.
When using a quasi-resonant converter with universal input
In the case where automatic restart is used, the IC function is (85 to 265 VAC), if the output power is set constant, then because
an intermittent oscillation mode, determined by the cycle of the higher input voltages have higher frequency, the MOSFET peak
charge and discharge of the capacitor C2 (refer to figure 6) con- drain current becomes low.
VCC pin voltage
VCC(ON)
VCC(OFF)
FB/OLP pin voltage

VFB(OLP)= 5.96V
STR-Y6700
GND FB/OLP
4 5
ID IFB PC1
220kΩ
C3
Figure 25. Individual operation waveforms (left) and peripheral circuit configured for OLP with
automatic restart (right)

19
Because ROCP is fixed, the OCP point in the higher input volt- to ensure that IOUT(OCP) remains more than IOUT across the input
age will shift further into the overload area. And thus, the output voltage range.
current at OCP point in the maximum input voltage, IOUT(OCP) ,
Figure 27 shows an overcurrent input compensation circuit, and
doubles relative to that in the minimum input voltage.
figure 28 shows Efw1 and Efw2 relative to the input voltage. Also,
In order to suppress this phenomenon, this IC has the overcurrent figure 29 shows the relationship between the overcurrent thresh-
input compensation function. old voltage after input compensation, V'OCP(H) , and the BD pin
voltage, Efw2.
As for determining an input compensation value, it is necessary
to avoid excessive input compensation for the output current The overcurrent input compensation function compensates the
specification, IOUT , as shown in figure 26. When excessive input overcurrent detection threshold voltage (normal operation),
compensation is applied, IOUT(OCP) may be below IOUT in the situ- VOCP(H) , according to the input voltage. As shown in figure 27,
ation where the input voltage is high. Therefore, it is necessary the forward voltage, Efw1, is proportional to the input voltage,
Flyback voltage, Erev1

D2 R2 T1
IOUT without input

Output Current at OCP, IOUT(OCP) 㧔A㧕
compensation C2
3 D
VCC
IOUT with appropriate Forward voltage, Efw1
input compensation DZBD VDZBD
STR-Y6700
IOUT
IOUT target output level RBD1
6
IOUT with excessive BD
input compensation S/OCP GND Efw2
2 4 RBD2
ROCP CBD
85V AC Input Voltage (V㧕 265V
Figure 26. OCP circuit input compensation Figure 27. Overcurrent input compensation circuit
100 V 230 V
0 AC 1
VZ VOCP(H)= 0.910
0.8
Efw1
(V)
0.6
MAX
VOCP(H)
0 AC
0.4 TYP
'
MIN
0.2
Efw2
OCP input compensation 0
0 –1 –2 –3 –4 –5 –6
starting point: BD pin voltage, Efw2 (V)
the point matching Efw1– VZ = 0
Recommended use range
Figure 28. Efw1 and Efw2 voltage relative to AC input voltage Figure 29. Overcurrent threshold voltage after input compensation, V'OCP(H)
(reference for design target values)

20
the voltage passed through DZBD from Efw1 is biased by either temperature of the power MOSFET should be checked in normal
end of RBD1 and RBD2 , and thus the BD pin voltage is provided quasi-resonant operation switched from bottom-skip operation,
the voltage on RDB2 divided by the divider of RBD1 and RBD2. by changing load condition. Efw2 , which includes surge voltage,
Referring to figure 29, the overcurrent detection threshold voltage must be within the absolute maximum rating of the BD pin volt-
after input voltage compensation, V'OCP(H) , relative to Efw2 can be age (–6.0 to 6.0 V) at the maximum input voltage.
calculated, and this voltage becomes the OCP threshold voltage
after input compensation. Figure 30 shows each voltage waveform for the input voltage in
normal quasi-resonant operation:
• DZBD setting: The starting voltage for input compensation is
set by the Zener voltage, VZ , of DZBD . According to the input • When VDZBD ≥ Efw1 (Point A). No input compensation required,
voltage specification or transformer specification, it is required Efw2 remains zero, and the detection voltage for an overcurrent
to be VZ = 6.8 to 30 V. event is the Overcurrent Detection Threshold Voltage (normal
• RBD1 setting: Please refer to Bottom-On Timing section, p. 12. operation), VOCP(H).
• The recommended value of RBD2: 1.0 kΩ • When VDZBD < Efw1 (Point B through Point D). When the input
Overcurrent input compensation should be adjusted so that the voltage is increased and Efw1 exceeds the Zener voltage, VZ,
variance of the output current, IOUT(OCP) , at an OCP point, is of DZBD, Efw2 will be produced as a negative voltage to com-
minimized at the high and low input voltage. In addition, as pensate the Overcurrent Detection Threshold Voltage (normal
shown in figure 26, the input compensation must be adjusted so operation), VOCP(H) .
that IOUT(OCP) remains more than the output current specification,
Efw2 is generally adjusted to the BD pin voltage of Efw2 = –3.0 V
IOUT , across the input voltage range.
at the maximum input voltage. Adjustment of Efw2 will change
If V'OCP(H) is compensated to the Bottom-Skip Operation Thresh- the overcurrent detection threshold voltage by an overcurrent
old Voltage, VOCP(BS1), or less, the IC will change from one bot- input compensation function. Therefore, Efw2 must be adjusted
tom-skip operation to normal quasi-resonant operation, and thus while checking the input compensation starting point and the
will raise the operation frequency and will provide output power. amount of input compensation. Also, the variations of the over-
Therefore, switching losses in normal quasi-resonant operation current detection threshold voltage after input compensation,
is higher than that in bottom-skip operation. In this case, when V'OCP(H) , can be calculated by the MIN and MAX values shown
the input compensation is compensated to VOCP(BS1) or less, the in figure 29.
Auxiliary winding voltage

E rev1
0
E fw1 tON
tON
tON
tON
0 Input voltage
VDZBD A B C D DZ BD Zener voltage, Vz
100V 230V
0 Input voltage
Efw2
At the input voltage where Efw1 reaches

VZ or more, Efw2 goes negative.
Figure 30. Each voltage waveform for the input voltage in normal quasi-resonant operation

21
BD Pin Peripheral Components Value Selection Reference When setting RBD2 = 1 kΩ, RBD1 = 7.5 kΩ, Vf = 0.7 V, and Erev1 =
Example 20 V, Erev2 of figure 14 can be calculated as follows:
This example demonstrates the determination of external compo-
RBD2
nent values for the BD pin peripheral circuit. It assumes universal Erev 2 = × (Erev1 − Vf ) (8)
input (85 to 265 VAC) is being used, and input compensation RBD1 + RBD2
begins from the input voltage of 120 VAC. The transformer is
1 (kΩ)
assumed to have primary winding with NP = 40 T, and an auxil- = × (20 (V) − 0.7 (V))
iary winding with ND = 5 T. 1 (kΩ) + 7.5 (kΩ)
= 2.27 (V)
To determine the Zener voltage, VZ , of DZBD , Efw1 at 120 VAC is
calculated by the following formula: In this case, the quasi-resonant voltage Erev2 meets the design
guidelines: it is Quasi-Resonant Operation Threshold Voltage
ND 1, VBD(TH1) = 0.24V or more, and Efw2 and Erev2 are kept within
Efw1 = × VIN(AC) × (5)
NP the limits of the Absolute Maximum Rating (–6.0 to 6.0 V) of
5 the BD pin.
= 40 × 120 (V) × = 21.2 (V)
When Overcurrent Input Compensation is Not Required
The Zener diode rating, VZ , is chosen to be 22 V, a standard When the input voltage is narrow range, or provided from PFC
value. circuit, the variation of the input voltage is small. And thus, the
variation of OCP point may become less than that of the universal
RBD1 results in Efw2 = –3.0 V at the maximum input voltage of
input voltage specification.
265 VAC, as follows:
RBD2 ND When overcurrent input compensation is not required, the input
RBD1 = × × VIN ( AC ) × 2 Z BD E fw2 (6) compensation function can be disabled by substituting a high-
Efw2 NP
speed diode for the Zener DZBD diode, and by keeping BD pin
1 (kΩ) 5 voltage from being minus voltage.
= × × 265(V) 2 22 (V) 3 (V) = 7.28 (kΩ)
3(V) 40
In addition, the following formula shows the reverse voltage of a
The RBD1 rating is chosen to be 7.5 kΩ of the E series. high-speed diode. The high-speed selection should take account
Choosing RBD2 = 1.0 kΩ, the | Efw2 | value at 265 VAC can be of its derating.
calculated as follows: ND
E fw1   Maximum Input Voltage (9)
RBD2 NP
E fw2 = × E fw1 − Z BD (7)
RBD1 + RBD2 Overcurrent Detection Threshold Voltage
1(kΩ) 5 The overcurrent detection threshold voltage has two modes of
= × × 265(V) 2 − 22 (V) operation.
7.5 (kΩ) + 1 (kΩ) 40
• Overcurrent protection (OCP) on a pulse by pulse basis
= 2.92 (V)
2.92 V is an acceptable approximation of |–3.0 V|. Referring to When the S/OCP pin voltage reaches the Overcurrent Detection
figure 29, when compensated by Efw2 = –2.92 V, the overcurrent Threshold Voltage (normal operation), VOCP(H), or the threshold
threshold voltage after input compensation, V'OCP(H), is set to voltage after overcurrent input compensation, V'OCP(H) (refer
about 0.66 V (typ). to figure 29), the OCP function is activated on a pulse by pulse
basis.

22
• Overcurrent protection in latch mode 40.0 μs (refer to figure 31). And thus, the peak drain current is
As the protection for an abnormal state, such as an output wind- limited, and the audible noise of the transformer is suppressed.
ing being shorted or the withstand voltage of secondary rectifier In designing a power supply, the on-time must be less than
being out of specification, when the S/OCP pin voltage reaches tON(MAX) .
VOCP(La.OFF) = 1.83 V, the IC stops switching operation immedi-
ately, in latch mode. Releasing the latched state is done by turn- If such a transformer is used that the on-time is tON(MAX) or more,
ing off the input voltage and by dropping the VCC pin voltage under the condition with the minimum input voltage and the
below VCC(OFF). maximum output power, the output power would become low.
This overcurrent protection also operates during the leading edge In that case, the transformer should be redesigned taking into
blanking. consideration the following:
Maximum On-Time Limitation Function • Inductance, LP , of the transformer should be lowered in order to
When the input voltage is low or in a transient state such that raise the operation frequency.
the input voltage turns on or off, the on-time of the incorporated • Lower the primary and the secondary turns ratio, NP / NS , to
power MOSFET is limited to the maximum on-time, tON(MAX) = lower the duty cycle.
ID Maximum
On-Time
Time
VDS
Time
Figure 31. Confirmation of maximum on-time

23
Design Notes
External Components the duty cycle will change due to the quasi-resonant operations
delaying the turn-on, the duty cycle needs to be compensated.
Take care to use properly rated and proper type of components.
When the on-duty, DON, is calculated by the ratio of the primary
• Output smoothing capacitor. Consider design margins for rat-
turns, NP , and the secondary turns, NS , the inductance, L'P on the
ings of ripple current, voltage, and temperature in selecting the
primary side, taking into consideration the delay time, can be
output capacitor. A low impedance capacitor, designed to be
calculated by the following formula:
tolerant against high ripple current, is recommended.
• Transformer. Consider design margins for temperature rise, (E IN( MIN )× DON ) 2
resulting from copper losses and core losses, in designing or L P' = 2
2PO × f 0 (10)
selecting a transformer. Switching current contains a high + E IN( MIN ) × DON × f 0 × π CV
frequency component that causes the skin effect; therefore, η1
consider a current density of 3 to 4 A/mm2 and select a wire
where
gauge based on RMS current. In the event further temperature
measurement is necessary and it is necessary to increase surface PO: the maximum output power,
area of the wire, try the following measures:
f0: the minimum operation frequency,
▫ Increase the quantity of parallel wires
CV: the voltage resonance capacitor connected between the
▫ Use litz wire
drain and source of the power MOSFET,
▫ Increase the diameter of the wires
η1: the transformer efficiency,
• Current detection resistor, ROCP . Choose a low equivalent series
inductance and high surge tolerant type for the current detection DON : the on-duty at the minimum input voltage,
resistor. If a high inductance type is used, it may cause malfunc- E FLY
DON = ,
tioning because of the high frequency current running through E IN ( MIN ) + E FLY
it. EIN(MIN): the C1 voltage of figure 32 at the minimum input
voltage,
Transformer Design EFLY : the flyback voltage ⇒
The design of the transformer is fundamentally the same as the NP
E FLY = × (VO + Vf ) , and
power transformer of a Ringing Choke Converter (RCC) sys- NS
tem: a self-excitation type flyback converter. However, because Vf : the forward voltage drop of D3.
VF
NP T1 NS D3 VO
LP
EFLY
EIN P S IOFF C6
ID
C1
CV
Figure 32. Quasi-resonant circuit

24
Each parameter, such as the peak drain current, IDP , is calculated The minimum operation frequency, f0 , can be calculated by the
by the following formulas: following formula:
tONDLY = π L'P  CV (11) 2
−
2PO
+ +
(
2PO 4π E IN ( MIN )× DON )×
2
CV
' = DON (1 − f 0 × t ONDLY )
DON (12) η1 η1 L'P (17)
f0 =
PO 1 2π CV × E IN ( MIN ) × DON
I IN   (13)
ǯ2 E IN(MIN)
In transformer design, AL-value and NP must be set in a way that
2  I IN (14) the ferrite core does not saturate. Here, use ampere turn value
I DP =
'
DON (AT), the result of IDP × NP and the graph of NI-Limit (AT) versus
AL-value (figure 33 is an example of it). NI-Limit is the limit
L'P
NP  (15) that the ampere turn value should not exceed; otherwise the core
AL-value
saturates.
NP  VO  Vf  When choosing a ferrite core to match the relationship of
NS  (16)
E FLY NI-Limit (AT) versus AL-value, it is recommended to set the cal-
culated NI-Limit value below about 30% from the NI-Limit curve
where of ferrite core data, as shown in the hatched area containing the
tONDLY : the delay time of quasi-resonant operation, design point in figure 33, to provide a design margin in consider-
ation of temperature effects and other variations.
IIN : the average input current,
η2 : the conversion efficiency of the power supply,
IDP : the peak drain current,
D'ON : the on-duty after compensation, and
VO : the secondary side output voltage.
Saturation
region lower
boundary
N I-Limit (AT)
Margin = 30% less
Design point
(example)
AL-Value (nH/T 2 )
Figure 33. Example of NI-Limit versus AL-Value characteristics

25
Phase Compensation significant noise, and large power dissipation may occur.
Figure 34 shows a typical secondary side error amplifier circuit. Circuit loop traces flowing high frequency current, as shown in
The C7 value for phase compensation is recommended to be figure 36, should be designed as wide and short as possible to
0.047 to 0.47 μF, and should be confirmed in actual operation. reduce trace impedance.
Figure 35 shows a circuit around the FB/OLP pin. The C3 value, In addition, earth ground traces affect radiation noise, and thus
for high frequency noise rejection and phase compensation, is should be designed as wide and short as possible.
recommended to be approximately 470 pF to 0.01 μF. It should
be connected close between the FB/OLP pin and the GND pin, Switching mode power supplies consist of current traces with
and should be confirmed in actual operation. high frequency and high voltage, and thus trace design and
component layout should be done in compliance with all safety
guidelines.
Circuit Trace Layout
Furthermore, because an integrated power MOSFET is being
PCB circuit trace design and component layout affect IC func- used as the switching device, take account of the positive thermal
tioning during operation. Unless they are proper, malfunction, coefficient of RDS(on) for thermal design.
D3 L1
T1 VOUT
R6
PC1 R3
R7
S R4 C8
C6
C7 R5
U2
R8
GND
Figure 34. Peripheral circuit around a secondary-side
shunt regulator (U2)
STR-Y6700
S/OCP GND FB/OLP
2 4 5
PC1
ROCP IFB
C3
Figure 35. FB/OLP pin peripheral circuit Figure 36. High-frequency current loops

26
Figure 37 shows practical trace design examples and consider- (3) Current Detection Resistor, ROCP:
ations. In addition, observe the following:
• IC peripheral circuit Place ROCP as close to the S/OCP pin as possible. In addition,
in order to avoid interference of the switching current with the
(1) Traces among S/OCP pin, ROCP , C1, T1(primary winding), control circuit, connect the ground of the control circuit to the
and D/ST pin point A in figure 37 as close as possible, with a dedicated trace to
The traces carry the switching current; therefore, widen and ROCP .
shorten them as much as possible.
• Secondary side, traces among T1(secondary winding), D3,
If the IC and the electrolytic capacitor C1 are apart, place a film
and C6
capacitor (0.1 μF with appropriate voltage rating) close to the IC
or the transformer in order to reduce series inductances of the
traces against high frequency current. The secondary-side switching current runs through this trace.
Widen and shorten the traces as much as possible.
(2) Traces among GND pin, C2(–), T1(auxiliary winding D), R2,
D2, C2(+), and VCC pin
Thin and long traces cause the series inductance to be high and it
This trace is for supplying voltage to the IC. Widen and shorten results in high surge voltage on the power MOSFET when it turns
the traces as much as possible. If the IC and the electrolytic off. Therefore, proper layout pattern design helps to increase the
capacitor C2 are apart, place a film or ceramic capacitor voltage margin of the power MOSFET to its breakdown voltage
(0.1 to 1.0 μF) as close to the VCC pin and the GND pin and to reduce power stress and losses in the clamping snubber
as possible. circuit.
D3
T1
Clamping Snubber Circuit P

C1
C6
S
U1
D2 R2
STR-Y6700 VCC C2
D
Main circuit
FB/OLP
S/OCP
VCC
D/ST
GND
BD
NF
DZBD Control circuit GND circuit

2
1 2 3 4 5 6 7
RBD1
Secondary rectification and
CV smoothing circuit
ROCP R1 CBD RBD2

C3
C4 PC 1
A
C5
Figure 37. An example schematic of a typical application circuit

27
Because reliability can be affected adversely by improper storage Heatsink Mounting Method
environments and handling methods, please observe the following
cautions. • Torque When Tightening Mounting Screws. Thermal resistance
Cautions for Storage increases when tightening torque is low, and radiation effects are
• Ensure that storage conditions comply with the standard decreased. When the torque is too high, the screw can strip, the
temperature (5 to 35°C) and the standard relative humidity heatsink can be deformed, and distortion can arise in the product
(around 40 to 75%); avoid storage locations that experience frame. To avoid these problems, observe the recommended tightening
extreme changes in temperature or humidity. torques for this product package type, 0.588 to 0.785 N•m
• Avoid locations where dust or harmful gases are present and (6 to 8 kgf•cm).
avoid direct sunlight.
• Reinspect for rust on leads and solderability of products that have Soldering
been stored for a long time.
• When soldering the products, please be sure to minimize the
Cautions for Testing and Handling
working time, within the following limits:
When tests are carried out during inspection testing and other
standard test periods, protect the products from power surges 260±5°C 10 s
from the testing device, shorts between adjacent products, and
shorts to the heatsink. 350±5°C 3 s (solder iron)
Remarks About Using Silicone Grease with a Heatsink • Soldering iron should be at a distance of at least 2.0 mm from the
• When silicone grease is used in mounting this product on a body of the products
heatsink, it shall be applied evenly and thinly. If more silicone
grease than required is applied, it may produce stress. Electrostatic Discharge
• Coat the back surface of the product and both surfaces of the • When handling the products, operator must be grounded.
insulating plate to improve heat transfer between the product and
Grounded wrist straps worn should have at least 1 MΩ of
the heatsink.
resistance to ground to prevent shock hazard.
• Volatile-type silicone greases may permeate the product and
produce cracks after long periods of time, resulting in reduced • Workbenches where the products are handled should be
heat radiation effect, and possibly shortening the lifetime of the grounded and be provided with conductive table and floor mats.
product.
• When using measuring equipment such as a curve tracer, the
• Our recommended silicone greases for heat radiation purposes,
which will not cause any adverse effect on the product life, are equipment should be grounded.
indicated below: • When soldering the products, the head of soldering irons or the
Type Suppliers solder bath must be grounded in other to prevent leak voltages
generated by them from being applied to the products.
G746 Shin-Etsu Chemical Co., Ltd.
YG6260 MOMENTIVE Performance Materials, Inc. • The products should always be stored and transported in our
shipping containers or conductive containers, or be wrapped in
SC102 Dow Corning Toray Co., Ltd. aluminum foil.

28
The products described herein are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit im-
provements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this
publication is current before placing any order.
When using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at the users
responsibility.
Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at
a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to device failure or malfunction.
Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus
(home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation
hardness assurance (e.g., aerospace equipment) is not supported.
When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems
or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written con-
firmation of your specifications.
The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equip-
ment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited.
The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are given
for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual property rights, or
any other rights of Sanken or Allegro or any third party that may result from its use.
Anti radioactive ray design is not considered for the products listed herein.
Sanken assumes no responsibility for any troubles, such as dropping products, caused during transportation out of Sanken’s distribution network.
The contents in this document must not be transcribed or copied without Sanken’s written consent.
Copyright © 2011-2012 Allegro MicroSystems, Inc.

29

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Application Information

STR-Y6700 Series Quasi-Resonant Off-Line Switching Regulators

The STR-Y6700 series products comprise a power MOSFET

Features and Benefits • Protection functions

STR-Y6700-AN Rev. 2.0

STR-Y6700 Pin List Table

DRV MOSFET source and overcurrent detection signal

Allegro MicroSystems, Inc.

10 ±0.2 4.2 ±0.2

0.5 0.5 0.5 0.5

(Front view) (Side view)

Pin material: Cu a. Product name label: Y67××

Pin treatment Pb-free. Device composition

Allegro MicroSystems, Inc.

Absolute Maximum Ratings Unless specifically noted, TA = 25°C and VCC = 20 V

Electrical Characteristics of MOSFET Unless specifically noted, TA = 25°C and VCC = 20 V

Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc.

VCC(INT) is the initial voltage of the VCC pin in V. Start

VCC(BIAS)(max) < VCC < VCC(OVP)(min) (2)

12.5 (V) < VCC < 28.5 (V)

Allegro MicroSystems, Inc.

Figure 6. VCC pin peripheral circuit with R2

Allegro MicroSystems, Inc.

• Winding structural example (a): Separating the auxiliary wind-

Winding structural example (b)

Figure 7. Winding structural examples

Allegro MicroSystems, Inc.

Startup Target Operating Voltage

Time Pulse width1.0 μs (min)

Figure 8. Operational mode at startup

Allegro MicroSystems, Inc.

VSC is determined by the voltage of the FB/OLP pin (refer to

Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc.

RBD1 3.0 V recommended,

Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc.

BD pin blanking time

Allegro MicroSystems, Inc.

• The mode is changed from one bottom-skip quasi-resonant

(Light Load) One Bottom-Skip Quasi-Resonant Normal Quasi-Resonant (Heavy Load)

S/OCP VOCP(H)= 0.910V

(Heavy Load) Normal Quasi-Resonant One Bottom-Skip Quasi-Resonant (Light Load)

S/OCP V OCP(H)= 0.910V

Allegro MicroSystems, Inc.

VBD(TH1)= 0.34V(MAX) VBD(TH1)= 0.34V(MAX)

VBD(TH2)= 0.27V(MAX) VBD(TH2)= 0.27V(MAX)

Pulse Width Pulse Width

SMPS Output Burst Oscillation

Below several kHz

Normal Operation Standby Operation Normal Operation

Figure 22. Auto Standby mode timing

Allegro MicroSystems, Inc.

tection function is active.

VCC pin voltage Bias assist

FB/OLP pin voltage Charge by IFB(OLP)