Scribd Logo
Upload

Welcome to Scribd!

  • Code

    Uploaded by

    NINAD ANIL PARKAR
    4 views4 pages
    The document contains code for a Verilog module that implements a 2048x8-bit synchronous memory. It contains registers to store the input data, write enable signal, and address. On each clock cycle, it either writes the input data to the addressed memory location if write enable is high, or outputs the data from the addressed location if write enable is low. A testbench is provided that writes then reads from all memory locations.

    Original Description:

    Original Title

    New Microsoft Word Document

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document contains code for a Verilog module that implements a 2048x8-bit synchronous memory. It contains registers to store the input data, write enable signal, and address. On each clock cycle, it either writes the input data to the addressed memory location if write enable is high, or outputs the data from the addressed location if write enable is low. A testbench is provided that writes then reads from all memory locations.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    4 views4 pages

    Code

    Uploaded by

    NINAD ANIL PARKAR
    The document contains code for a Verilog module that implements a 2048x8-bit synchronous memory. It contains registers to store the input data, write enable signal, and address. On each clock cycle, it either writes the input data to the addressed memory location if write enable is high, or outputs the data from the addressed location if write enable is low. A testbench is provided that writes then reads from all memory locations.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 4

    Code:

    module main(data_in,data_out,addr,clk,we);

    input clk,we;

    input [7:0] data_in;

    output reg [7:0] data_out;

    input [10:0] addr;

    reg [7:0] memory [2047:0];

    reg [7:0] data_in_reg;

    reg we_reg;

    reg[10:0] addr_reg;

    always @(posedge clk)

    begin

    we_reg<=we;

    data_in_reg<=data_in;

    addr_reg<=addr;

    end

    always @(posedge clk)

    begin

    if(we_reg)

    memory[addr_reg]<=data_in_reg;

    else

    data_out<=memory[addr_reg];

    end

    endmodule
    TB:

    module TB();

    reg [7:0] data_in;

    wire [7:0] data_out;

    reg [10:0] addr;

    reg clk,we;

    integer i;

    main uut(data_in,data_out,addr,clk,we);

    initial

    begin

    clk=0;

    forever #5 clk=~clk;

    end

    initial begin

    we=1;

    for(i=0;i<2047;i=i+1)

    begin

    addr=2047-i;

    data_in=i; #10;

    end

    #20470

    we=0;

    for(i=0;i<2047;i=i+1)

    begin

    addr=2047-i; #10;
    end

    $finish;

    end

    endmodule

    Timing Constraint:

    Period=2.6ns

    Max Frequency=384Mhz

    WNS=0.258ns

    Enable Rate of the design before Optimization: 100%


    Writing to the memory(we=1)

    Reading from Memory(we=0):

    You might also like