ELT3047 Computer Architecture

Lecture 7: Single Cycle Processor Design

Hoang Gia Hung

Faculty of Electronics and Telecommunications
University of Engineering and Technology, VNU Hanoi
 Last lecture review
❑ ISAs support arithmetic
➢ Signed and unsigned integers
➢ Floating-point approximation to reals

❑ Arithmetic operations have finite range and precision

➢ Operations can overflow and underflow
➢ Need to account for this in programs

❑ MIPS ALU ISA

➢ Core instructions: 54 most frequently used
▪ 100% of SPECINT, 97% of SPECFP
➢ Other instructions: less frequent

❑ Today’s lecture: Building a single-cycle processor

➢ Additional logic for datapath & control
Building a Processor: Datapath &
Control
❑ Components of a processor
Datapath
• Collection of components that process data
• Performs the arithmetic, logical and memory
operations

Control
• Tells the datapath, memory and I/O devices what
to do according to program instructions

❑ Two MIPS implementations …

➢ A simplified version (today)
➢ A more realistic pipelined version (later)

❑ … based on a simple MIPS ISA subset

➢ Memory reference: lw, sw
➢ Arithmetic/logical: add, sub, and, or, slt
➢ Control transfer: beq, j
 Instruction Execution

1. Fetch:
Instruction ▪ Get instruction from memory
Fetch ▪ Address is in Program Counter (PC) Register
Instruction 2. Decode:
Next Instruction

Decode ▪ Find out the operation required

Operand 3. Operand Fetch:
Fetch ▪ Get operand(s) needed for operation
Execute 4. Execute:
▪ Perform the required operation
Result
Write 5. Result Write (Store):
▪ Store the result of the operation
 MIPS Instruction Execution
❑ Show the actual steps for 3 representative MIPS instructions
➢ Fetch and Decode stages not shown, the standard steps are performed

add $3, $1, $2 lw $3, 20($1) beq $1, $2, ofst

Fetch
standard standard standard
Decode

Operand o Read [$1] as opr1 o Read [$1] as opr1 o Read [$1] as opr1
Fetch o Read [$2] as opr2 o Use 20 as opr2 o Read [$2] as opr2

o MemAddr = opr1 + opr2

Taken = (opr1 == opr2 )?
Execute Result = opr1 + opr2 o Use MemAddr to read
Target = (PC+4) + ofst4
from memory

Result if (Taken)
Result stored in $3 Memory data stored in $3
Write PC = Target

◼ opr = operand ◼ ofst = offset

◼ MemAddr = Memory Address
 Refined MIPS Instruction Execution
❑ Refined design
➢ Merge Decode and Operand Fetch – Decode is simple for MIPS
➢ Split Execute into ALU (Calculation) and Memory Access

add $3, $1, $2 lw $3, 20( $1 ) beq $1, $2, ofst

Fetch Read inst. at [PC] Read inst. at [PC] Read inst. at [PC]

Decode &
o Read [$1] as opr1 o Read [$1] as opr1 o Read [$1] as opr1
Operand
o Read [$2] as opr2 o Use 20 as opr2 o Read [$2] as opr2
Fetch
Taken = (opr1 == opr2 )?
ALU Result = opr1 + opr2 MemAddr = opr1 + opr2
Target = (PC+4) + ofst4

Memory Use MemAddr to read

Access from memory

Result if (Taken)
Result stored in $3 Memory data stored in $3
Write PC = Target
 Building MIPS datapath
❑ We will build a MIPS datapath
incrementally: Fetch
➢ Refining the overview design

❑ What we are going to do: Decode

Next Instruction
➢ Look at each stage closely, figure out the
requirements and processes
ALU
➢ Sketch a high level block diagram, then zoom in
for each elements
➢ With the simple starting design, check whether Memory
different type of instructions can be handled: Access
▪ Add modifications when needed

❑ Study the design from the viewpoint of a Result

designer, instead of a "tourist" Write
 Fetch Stage: Requirements
❑ Instruction Fetch Stage:
1. Use the Program Counter (PC) to fetch the instruction from memory
▪ PC is implemented as a special register in the processor
2. Increment the PC by 4 to get the address of the next instruction:
▪ How do we know the next instruction is at PC+4?
▪ Note the exception when branch/jump instruction is executed

❑ Output to the next stage (Decode):

➢ The instruction to be executed

1. Fetch
2. Decode
3. ALU
4. Memory
5. RegWrite
 Fetch Stage: Block diagram

Increment by
4 for next
instruction

Decode Stage
32-bit
register
 Element: Instruction Memory
❑ Storage element for the instructions
Instruction
➢ It is a sequential circuit Address

▪ Uses a Clk signal to determine when to

Instruction
update the stored value
▪ Edge-triggered: update when Clk Instruction
changes (edges of the Clk pulses) Memory

➢ Has an internal state that stores information

➢ Clock signal is assumed and not shown

❑ Supply instruction given the address Memory

➢ Given instruction address 𝑀 as input, the ………..

memory outputs the content at address 𝑀 2048 add $3, $1, $2
➢ Conceptual diagram of the memory layout is 2052 sll $4, $3, 2
given on the right 2056 andi $1, $4, 0xF

…… ………..
 The Idea of Clocking
❑ It seems that we are reading and updating the PC at the same
time:
➢ How can it works properly?

❑ Magic of clock
➢ PC is read during the first half of the clock period and it is updated with PC+4
at the next rising clock edge

Add Time
4

PC Read Clk
In address

Instruction PC 100 104 108 112

Instruction In 104 108 112 116
memory
 Decode Stage: Requirements
❑ Instruction Decode Stage:
➢ Gather data from the instruction fields:
1. Read the opcode to determine instruction type and field lengths
2. Read data from all necessary registers
▪ Can be two (e.g. add), one (e.g. addi) or zero (e.g. j)

❑ Input from previous stage (Fetch):

➢ The instruction to be executed

❑ Output to the next stage (ALU):

➢ Operation and the necessary operands
1. Fetch
2. Decode
3. ALU
4. Memory
5. RegWrite
 Decode Stage: Block Diagram
Register
numbers
Fetch Stage

5 Read Data

ALU Stage
Read 32
register 1 data 1
5 Read
Inst. Register
register 2 Operands
5 Write
File
register Read 32
data 2
Operation

Collection of
registers, known
as register file
 Element: Register File
5 Read Read 32
register 1 data 1
Register 5 Read
numbers Register
register 2
File Data
5 Write
register
Read 32
32 data 2
Write
Data
data

RegWrite

❑ A collection of 32 registers:
➢ Each 32-bit wide; can be read/written by specifying register number
➢ Read at most two registers per instruction
➢ Write at most one register per instruction

❑ RegWrite is a control signal to indicate:

➢ Writing of register
➢ 1(True) = Write, 0 (False) = No Write
 Decode Stage: R-Format Instruction
add $8, $9, $10
Notation:
opcode
000000
31:26

Inst [Y:X]
= bits X to Y in Instruction
25:21

01001

Inst [25:21]
5 Read 32 content of
rs

Read
register 1 data 1 register $9
5 Read
20:16

01010

register 2 Register
rt

File
5 Write
register
Read 32 content of
15:11

01000

data 2
32 register $10
rd

Write
data
shamt
00000
10:6

RegWrite
Result to be stored
into register $8
100000
funct

(produced by later
5:0

stage)
 Decode Stage: I-Format Instruction
addi $21, $22, -50
opcode
001000
31:26
25:21

10110

Inst [25:21]
5 Read content of
rs

Read 32
register 1 data 1
register $22
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
Read 32
1111 1111 1100 1110

data 2
Write
data
Immediate
15:0

RegWrite

Problems:
- Destination $21 is in the "wrong position"
- Read Data 2 is an immediate value, not from register
 Decode Stage: Choice in Destination

addi $21, $22, -50

opcode
001000
31:26
25:21

10110

Inst [25:21]
5 Read content of
rs

Read 32
register 1 data 1
register $22
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read 32
1111 1111 1100 1110

data 2
U Write
data
X
Immediate

Inst [15:11]
15:0

RegWrite
RegDst
Solution (Write Reg. No.):
RegDst:
Use a multiplexer to choose the
A control signal to choose
either Inst[20:16] or Inst[15:11] correct write register number
as the write register number based on instruction type
 Element: Multiplexer

❑ Function: control
m
➢ Selects one input from multiple input lines

❑ Inputs: in0
➢ 𝑛 lines of same width .
.
M
U out
.
❑ Control: X
inn-1
➢ 𝑚 bits where 𝑛 = 2𝑚

❑ Output:
Control=0 → select in0 to out
➢ Select 𝑖𝑡ℎ input line if control = 𝑖 Control=3 → select in3 to out
 Decode Stage: Choice in Data 2
addi $21, $22, -50
opcode
001000
31:26
25:21

10110

Inst [25:21]
5 Read content of
rs

Read 32
register 1 data 1 register $22
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read 32
M
1111 1111 1100 1110

data 2
U Write
data U
Inst [15:11] X
X
Immediate
15:0

RegWrite
RegDst
Inst [15:0] 16 Sign 32 ALUSrc
Extend
A control signal to
choose either
Solution (Rd. Data 2): "Read data 2" or
the sign extended
Use a multiplexer to choose the correct operand 2. Inst[15:0] as the
Sign extend the 16-bit immediate value to 32-bit second operand
 Decode Stage: Load Word Instruction

lw $21, -50($22)
opcode
100011
31:26

Do we need any modification?

25:21

10110

Inst [25:21]
5 Read content of
rs

Read 32
register 1 data 1
register $22
5 Read
20:16

10101

register 2 Register
rt

5 Write File
register
M Read 32
M
1111 1111 1100 1110

data 2
U Write
data U
Inst [15:11] X
X
Immediate
15:0

RegWrite
RegDst
Inst [15:0] 16 Sign 32 ALUSrc
Extend
 Decode Stage: Branch Instruction
beq $9, $0, 3
opcode
000100
31:26
25:21

01001

Inst [25:21]
5 Read content of
rs

Read 32
register 1 data 1 register $9
5 Read
20:16

00000

register 2 Register
rt

5 Write File
register
M Read 32
M
0000 0000 0000 0011

data 2
U Write
data U
Inst [15:11] X
X
Immediate
15:0

RegWrite
RegDst
Inst [15:0] 16 Sign 32 ALUSrc
Extend

▪ Need to calculate branch outcome and target at the same time!

▪ We will tackle this problem at the ALU stage
 Decode Stage: Summary

Inst [25:21]
5 Read Read 32
register 1 data 1
Operand 1
5 Read
register 2
Register
5 Write
File
Inst[31:0] M register
Read 32

U Write
data 2 M
Inst [15:11]
X
data U Operand 2
X
RegWrite
RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
 ALU Stage: Requirements
❑ Instruction ALU Stage:
➢ ALU = Arithmetic-Logic Unit
➢ Also called the Execution stage
➢ Perform the real work for most instructions here
▪ Arithmetic (e.g. add, sub), Shifting (e.g. sll), Logical (e.g. and, or)
▪ Memory operation (e.g. lw, sw): Address calculation
▪ Branch operation (e.g. bne, beq): Perform register comparison and
target address calculation

❑ Input from previous stage (Decode):

➢ Operation and Operand(s)
1. Fetch
❑ Output to the next stage (Memory): 2. Decode
➢ Calculation result 3. ALU
4. Memory
5. RegWrite
 ALU Stage: Block Diagram

Memory Stage
Decode Stage

ALU result
Operands ALU

Operation

Logic to perform
arithmetic and
logical operations
 Element: Arithmetic Logic Unit
ALUcontrol
❑ ALU (Arithmetic Logic Unit) A
4

➢ Combinational logic to implement 32 (A op B) == 0?

isZero?
arithmetic and logical operations
ALU 32
❑ Inputs: B
result
A op B
➢ Two 32-bit numbers 32

❑ Control:
➢ 4-bit to decide the particular operation ALUcontrol Function
0000 AND
❑ Output: OR
0001
➢ Result of arithmetic/logical operation
0010 add
➢ A 1-bit signal to indicate whether result
0110 subtract
is zero
0111 slt
1100 NOR
 ALU Stage: Non-Branch Instructions
❑ We can handle non-branch instructions easily:

add $8, $9, $10

opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21]
5 Read 4
rs

Read 32
register 1 data 1
5 Read
20:16

01010

register 2 isZero?
rt

Register ALU
5 Write File 32
register
result
M Read 32
15:11

01000

U
data 2 M
rd

Write
Inst [15:11]
X
data U
X
shamt
00000
10:6

RegWrite
RegDst
ALUSrc
Inst [15:0] 16 Sign 32 ALUcontrol:
100000
funct

Extend
5:0

Set using opcode + funct

field (more in next lecture)
 ALU Stage: Branch Instructions
❑ Branch instruction is harder as we need to perform two
calculations
❑ Example: "beq $9, $0, 3"
1. Branch Outcome:
▪ Use ALU to compare the register
▪ The 1-bit "isZero?" signal is enough to handle equal/not equal check
(how?)
2. Branch Target Address:
▪ Introduce additional logic to calculate the address
▪ Need PC (from Fetch Stage)
▪ Need Offset (from Decode Stage)
 Complete ALU Stage

PC Add
M
4
U
Add X PCSrc:
Left Shift Control Signal
opcode
000100

2-bit
31:26

to select
PCSrc between
(PC+4) or
ALUcontrol Branch Target
25:21

01001

Inst [25:21]
5 Read 4
rs

Read 32
register 1 data 1
5 Read
20:16

00000

register 2 Register isZero?

rt

File
5 Write
ALU 32
register
result
M Read 32
0000 0000 0000 0011

U Write
data 2 M
Inst [15:11]
X
data U
Immediate

X
15:0

RegWrite
RegDst
Inst [15:0] Sign 32
ALUSrc
16
Extend
beq $9, $0, 3
 Memory Stage: Requirements
❑ Instruction Memory Access Stage:
➢ Only the load and store instructions need to perform operation in this stage
▪ Use memory address calculated by ALU Stage
▪ Read from or write to data memory
➢ All other instructions remain idle
▪ Result from ALU Stage will pass through to be used in Register Write
stage (later in this lecture) if applicable

❑ Input from previous stage (ALU):

➢ Computation result to be used as memory address (if applicable)

❑ Output to the next stage (Register Write):

➢ Result to be stored (if applicable) 1. Fetch
2. Decode
3. ALU
4. Memory
5. RegWrite
 Memory Stage: Block Diagram

MemWrite

Register Write
ALU Stage

32 Address

Stage
Read 32
Result Data
32 Write
Data
Data
Memory

MemRead

Memory which
stores data values
 Element: Data Memory

❑ Function:
➢ Storage element for the data of a program

❑ Inputs: MemWrite
➢ Memory Address
➢ Data to be written (Write Data) for store Address
instructions
Read

❑ Control: Write
Data
Data

Data
➢ Read and Write controls; only one can be Memory
asserted at any point of time

❑ Output: MemRead
➢ Data read from memory (Read Data) for load
instructions
 Memory Stage: Load Instruction
❑ Only relevant parts of Decode and ALU Stages are shown

lw $21, -50($22)
opcode
000100
100011
31:26

ALUcontrol
25:21

01001
10110

Inst [25:21] 4
5
rs

RR1 RD1 32

5 MemWrite
20:16

00000
10101

RR2
rt

Register ALU
5 WR File
ALU 32
Address
M 32 result
1111 0000
0000

U
RD2 M Data
WD
Inst [15:11]
X U Memory
1111 0000
Immediate

X Read
RegWrite 32
15:0

Data
Write
1100 0011

RegDst Data
ALUSrc
Inst [15:0] 16 Sign 32
1110

Extend MemRead
 Memory Stage: Store Instruction
❑ Need Read Data 2 (from Decode stage) as the Write Data

sw $21, -50($22)
opcode
000100
101011
31:26

ALUcontrol
25:21

01001
10110

Inst [25:21] 4
5
rs

RR1 RD1 32

5 MemWrite
20:16

00000
10101

RR2
rt

Register ALU
5 WR File ALU 32
M 32 result Address
1111 0000
0000

U
RD2 M Data
WD
Inst [15:11]
X U Memory
1111 0000
Immediate

X Read 32
RegWrite
15:0

Data
Write
1100 0011

RegDst Data
Inst [15:0] 16 Sign 32
1110

Extend MemRead
 Memory Stage: Non-Memory Inst.
❑ Add a multiplexer to choose the result to be stored
add $8, $9, $10
opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 32 4
5
rs

RR1 RD1
5 MemWrite
20:16

01010

RR2
rt

Register ALU
5 WR File 32 ALU
M result
Address
15:11

01000

U
RD2 M
rd

Data
WD
X U Memory
Inst [15:11]
X
shamt
00000

Read
10:6

RegWrite Data M
Write
RegDst Data U
Inst [15:0] 16 Sign 32 X
100000
funct

Extend
5:0

MemToReg:
A control signal to indicate MemToReg
whether result came from
memory or ALU unit
 Register Write Stage: Requirements
❑ Instruction Register Write Stage:
➢ Most instructions write the result of some computation into a register
▪ Examples: arithmetic, logical, shifts, loads, set-less-than
▪ Need destination register number and computation result
➢ Exceptions are stores, branches, jumps
▪ There are no results to be written
▪ These instructions remain idle in this stage

❑ Input from previous stage (Memory):

➢ Computation result either from memory or ALU
1. Fetch
2. Decode
3. ALU
4. Memory
5. RegWrite
 Register Write Stage: Block Diagram
Memory Stage
5 Read Read
register 1 data 1
5 Read
register 2
5 Write Register
register File Read
data 2
Result Write
data

❑ Result Write stage has no additional element:

➢ Basically just route the correct result into register file
➢ The Write Register number is generated way back in the Decode Stage
 Register Write Stage: Routing

add $8, $9, $10

opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 4
5
rs

RR1 RD1
5 MemWrite
20:16

01010

RR2
rt

Register ALU
5 WR File ALU
M result
Address
15:11

01000

U
RD2 M
rd

Data MemToReg
WD
X U Memory
Inst [15:11]
X
shamt
00000

Read
10:6

RegWrite Data M
Write
Data U
Inst [15:0] Sign X
100000
funct

Extend
5:0
 The Complete Datapath!
Instruction
Memory
PC Add M
4
Instruction
U
Add X
Address
Left Shift
2-bit
PCSrc
opcode
000000
31:26

ALUcontrol
25:21

01001

Inst [25:21] 4
5
rs

RR1 RD1
5 is0? MemWrite
20:16

01010

RR2
rt

Register ALU
5 ALUSrc
WR File
ALU
M result
Address
15:11

01000

RD2 M
U
rd

WD Data MemToReg
Inst [15:11] U Memory
X
X
shamt
00000

Read
10:6

RegDst
RegWrite
Data M
Write
Data U
Inst [15:0] Sign X
100000
funct

Extend
5:0

MemRead
 Summary
❑ We have just finished “designing” the datapath for a subset of
MIPS instructions:
➢ Shifting and Jump are not covered

❑ Check your understanding: take the complete datapath and

play the role of controller
➢ See how supported instructions are executed
➢ Figure out the correct control signals for the datapath elements

❑ Next lecture: Control