Proceedings of the 15th
IEEE International Conference on Nanotechnology
July 27-30, 2015, Rome, Italy
Characterization of effective mobility by split C-V
technique in MoS2 MOSFETs with high-k/metal gate
Takahiro Mori, Toshitaka Kubo,
Noriyuki Uchida, and Atsushi Ando
National Institute of Advanced Industrial Science and
Technology (AIST)
Tsukuba, Japan
mori-takahiro@aist.go.jp
Eiichiro Watanabe, Daiju Tsuya, and Satoshi Moriyama
National Institute for Materials Science (NIMS)
Tsukuba, Japan
Abstract—Effective mobility in top-gated MoS2 metal–oxide–
semiconductor field-effect transistors (MOSFETs) with
HfO2/TaN gate was investigated. We realized C–V measurements
of MoS2 MOSFETs with a small gate area. The resultant surface
carrier concentration dependence of the effective mobility
suggested that surface roughness scattering was responsible for
the accumulated electron mobility in the fabricated MoS2
MOSFET. The scanning tunneling microscope image exhibited
atomic scale roughness on the cleaved MoS2 surface. This
suggested that the surface roughness should be reduced to
improve the performance of MoS2 MOSFETs.
Keywords—Metal–oxide–semiconductor field-effect transistors
(MOSFETs); MoS2; high-k/metal gate; mobility
I. INTRODUCTION
The driving force of progressive very-large-scale
integration (VLSI) technology has been dimensional scaling of
metal–oxide–semiconductor field-effect transistors
(MOSFETs). The short-channel effects, which are the
threshold voltage (VT) roll-off or degradation of subthreshold
swing (SS) accompanied by gate length reduction, is crucial in
device design for scaled MOSFETs [1]. Scaling of the channel
body thickness has been required to suppress the short-channel
effects on account of the enhancement of gate electrostatic
control. Therefore, the state-of-the-art VLSI utilizes 3D-
structure finFETs or thin-body silicon–on–insulator (SOI)-
MOSFETs as its building blocks. Currently, the channel body
thickness is lower than 10 nm [2]. Nevertheless, the recent
explosion of information requires a much higher computing
performance. To this end, a greater number of transistors
should be integrated in VLSI chips with further dimensional
device scaling. Therefore, further body thickness scaling is
continuously required to overcome the short channel effects.
In terms of MOSFETs with conventional 3D materials,
aggressive body thickness scaling causes mobility reduction
because of the scattering provided by surface roughness
978-1-4673-8156-7/15/$31.00 © 2015 IEEE
Naruki Ninomiya, and Masatoshi Tanaka
Department of Physics
Yokohama National University (YNU)
Yokohama, Japan
induced in the thinning process [3]. Recently, native 2D
semiconductor materials have been attractive for the channels
of further-scaled MOSFETs. This is because they can avoid
surface roughness on account of no thinning process being
required to provide a thin-body channel. Therefore, they can
outperform silicon transistors at a considerably smaller
technology node [4]. Most of these 2D semiconductor
materials belong to transition metal dichalcogenides (TMDCs);
molybdenum disulfide (MoS2) represents these 2D materials.
Monolayer MoS2 has unique electronic and optical properties
that fundamentally differ from its bulk materials because of
quantum-mechanical confinement. For example, bulk MoS2 is
an indirect gap semiconductor, whereas monolayer MoS2 is a
direct gap semiconductor [5]. These notable properties of
atomically thin materials are also very attractive for potential
applications.
TMDC MOSFETs, especially MoS2 MOSFETs, have been
recently studied by many research groups. Nevertheless,
mobility remains low. The scattering mechanism for reducing
mobility has been under investigation. For example, Ma and
Jena have theoretically examined ionized impurity scattering
and remote optical phonon scattering in MoS2 with
consideration of surrounding dielectrics [6]. Furthermore, Kim
et al. have reported the importance of phonon scattering with
experiment and calculation [7].
On the other hand, few reports exist on an effective
mobility characterization that enables detailed discussion of the
scattering in transistors. In future technological advancement of
TMDC MOSFETs, the effective mobility characterization by
each research group plays an important role. In this
presentation, we report our experimental examination of the
effective mobility of high-k/metal-gate MoS2 MOSFETs in
order to specify the scattering mechanism using a capacitance–
voltage (C–V) measurement. In addition, we discuss the
challenges with the measurement and mobility extraction.
762

Fig. 1. (a) Fabrication process flow. (b) Optical microscope image of
the MoS2 MOSFET. (c) Configuration of the split C–V measurements.
II. EXPERIMENT
We fabricated top-gated MoS2 MOSFETs by processing
atomically thin MoS2 flakes transferred onto a SiO2 (285
nm)/Si template utilizing a Scotch tape method. In this
fabrication process, we utilized an electron beam lithography
technique to pattern the devices. The device fabrication process
flow is shown in Fig. 1(a). First, the rectangle device active
area was isolated by Ar plasma etching. The active area was
successfully protected by resist in the isolation process, which
was confirmed by Raman spectroscopy. Then, Ni/Au source
and drain contacts were formed by an electron beam
evaporation and lift-off technique. Finally, HfO2/TaN high-
k/metal gate was formed on the channel. HfO2 was deposited
by atomic layer deposition (ALD). The layer thickness, tox, was
16.4 nm, which was confirmed by a rotating compensator
spectroscopic ellipsometer. A detailed description of the
fabrication process is provided in [8]. The gate length and
width were 4 μm and 1 μm, respectively (Fig. 1(b)). The MoS2
thickness was confirmed by Raman spectroscopy and an
optical contrast method as 3 ML.
III. RESULTS AND DISCUSSION
We first discuss the split C–V measurements. Fig. 1(c)
shows their configuration. The high-voltage terminal was the
gate; the low-voltage terminal was the source and drain. The
gate area was 4 μm2. Using the thickness and assumed
permittivity of the HfO2 insulator, it was estimated that the
target capacitance to be measured in this experiment was as
low as approximately 40 fF. This required the elimination of
stray capacitance in the measurement system to realize reliable
capacitance measurements. Accordingly, we employed peculiar
cabling to realize the background stray capacitance within 1 fF
with open compensation. This cabling realized the stray
capacitance on the order of a few fF with no compensation. We
utilized triaxial cables and coaxial needle probes in the
measurement system. To reduce stray capacitance, the outer
763
Fig. 2. C–V curve measured by the split C–V method with an AC
frequency of 1 MHz. Estimation methods for Cox and VFB are described
in the text.
Fig. 3. 1/C versus 1/(Vg - Vfb) plot of the C-V curve shown in Fig. 2. Cox
was obtained from the intercept of the linearly fitted line drawn in red.
Estimated İox agreed with the value of HfO2, which indicates that the
HfO2 insulator was stacked on the MoS2 channel with sufficient quality.
shield of the needle probes were grounded (to the sample stage)
near the tip of the probes. This was the only way to realize such
a small stray capacitance.
Fig. 2 shows the obtained C–V curve. Considering the
electronic characterization mentioned below, the device
operated in accumulation mode. Therefore, the accumulation
capacitance was measured in this experiment, which was
different from conventional split C–V measurements in
MOSFETs that obtain inversion capacitance in the channel [9].
To estimate oxide thickness from the C–V curve, the oxide
capacitance should be extracted by subtracting the quantum
capacitance. For conventional MOSFETs, the subtraction is
realized by curve fitting with a simulated or theoretical
calculation. To date, a convenient method for researchers to
utilize this type of technique for 2D material devices does not
yet exist. Therefore, to estimate oxide capacitance Cox, we
utilized a 1/C–1/(Vg - Vfb) plot [10] as shown in Fig. 3, where
Vfb is the flatband voltage. The intercept on the 1/C axis of the
linear fit yields 1/Cox in this method. This corresponds with the
assumption of the infinite applied gate voltage. In this
estimation, we utilized the Vfb determined by the method in
[11]. This was also a rapid method for determining the Vfb with
no simulation or theoretical calculation. The estimated Cox was
0.896 μF/cm2. From the Cox and tox, the relative permittivity of

Fig. 4. Id-Vg curves of the MoS2 MOSFET. The ON/OFF ratio, SS, and
field-effect mobility were 108, 136 mV/decade, and approximately 6
cm2/Vs, respectively.
Fig. 5. Surface carrier concentration dependence of the effective
mobility.
the insulator was estimated as 16.24, which corresponded to
that of HfO2 itself. Therefore, we concluded that the Cox
extraction method could be utilized for MoS2 devices and that
HfO2 film of sufficient quality was successfully stacked on
MoS2. Then, the equivalent oxide thickness (EOT) was 3.94
nm.
Fig. 4 shows the Id-Vg characteristics. The fabricated device
shows good performance with the ON/OFF ratio and
subthreshold swing (SS) of 108 and 136 mV/decade,
respectively. The interface trap density derived from SS and
Cox was 7.8×1012 eV-1cm-2, which was on the order of that of
the III-V/high-k interface [12]. This indicated that the
MoS2/HfO2 interface was successfully formed in this
experiment, wherein we provided no remarkable interface
formation process. Therefore, the low interface trap density
was expected to be on account of the advantage of the MoS2
surface with no dangling bonds. Understandably, some of the
interface improvement process likely better served the interface
properties. A considerably better interface was achieved with
the SS of 86 mV/decade in our other experiment [8].
The effective mobility, μeff, was determined by the surface
carrier concentration, Ns, and conductance gd [9]. The C–V
curve provided Ns; the Id–Vg curve provided gd. Fig. 5 shows
764
Fig. 6. STM image of the cleaved MoS2 surface.
the Ns dependence of μeff. We utilized the C–V curve taken
with 1 MHz for the μeff estimaton; however, the lower
measurement frequency was preferable for avoiding the
influence of the channel resistance [13]. In our experiment, it
was difficult to obtain a low frequency C–V curve with such a
small capacitance. We therefore only confirmed that the curved
shapes were nearly the same in the frequency range of 100 kHz
to 1 MHz, in this case. We intend to discuss the measurement
frequency dependence of the C–V curves in future work.
Because the MoS2 MOSFET is a kind of so-called
junctionless transistor, μeff exhibited accumulated electron
mobility. The maximum μeff was 11.7 cm2/Vs. On the other
hand, the maximum field-effect mobility μFE was
approximately 6 cm2/Vs. This discrepancy—the maximum μeff,,
which was larger than the maximum μFE—agreed with general
cases in conventional MOSFETs [14]. Accordingly, the
estimation result was reasonable.
Furthermore, a notable feature was the rapid reduction of
μeff with the increase in Ns. According to a discussion of the
scattering mechanism in conventional MOSFETs [9], this was
expected to be an effect of the surface roughness scattering.
The image of a cleaved MoS2 surface taken by scanning
tunneling microscope (STM) supports this discussion, in which
many atomic-size surface defects were observed (Fig. 6). The
atomically thin 2D materials, such as MoS2, were expected to
suppress mobility reduction on account of the surface
roughness induced by the thinning process. However, despite
no thinning process being performed, the experimental fact
suggests that the surface roughness scattering was responsible
for the mobility. Therefore, determining how such atomic scale
surface roughness affects mobility should be addressed to
elucidate the advantage of MoS2-channel MOSFETs. MoS2
MOSFETs generally show large variability of device
performance. The surface roughness could be a factor in
causing large variability, such as with contact resistance. To
clarify the major components causing large variability in MoS2
MOSFETs, more systematic device characterization with many
devices is required. In addition, to detail the experimental
results in this paper, the surface roughness scattering
mechanism in 2D materials should be discussed. In terms of
graphene nanoribbons, it is well known that line-edge
roughness scattering causes notable mobility reduction [15].
The atomic size surface defects can cause a similar “defect
edge” structure as in the “line edge.” Therefore, it is speculated
that the mobility reduction shown in this presentation could be
explained by a similar analogy. We aim to continue research on
these problems and on the improvement of the MoS2 surface to
reduce the effect of surface roughness scattering to the μeff.
IV. SUMMARY
We fabricated MoS2 MOSFETs with HfO2/TaN gate and
characterized their capacitance characteristics utilizing the split
C–V method. The successful gate stack and HfO2/MoS2
interface formation were realized, as confirmed by the C–V
and Id-Vg measurements. We examined the effective mobility,
which suggested that the mobility reduction was caused by the
surface roughness scattering. The cleaved MoS2 surface had
many atomic-scale defects, as observed by STM, which may
have been responsible for the scattering. We believe that a
roughness improvement technique should be developed to
enhance mobility in MoS2 MOSFETs.
ACKNOWLEDGMENT
The device fabrication in this work was supported by NIMS
Nanofabrication Platform in the “Nanotechnology Platform
Project” sponsored by the Ministry of Education, Culture,
Sports, Science and Technology (MEXT), Japan. This study
was financially supported in part by JSPS KAKENHI Grant
Number 26600081.
REFERENCES
[1] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. New
York, NY: Cambridge University Press, 2009.
[2] C.-H. Jan, U. Bhattacharya, R. Brain, S.- J. Choi, G. Curello, et al., “A
22nm SoC platform technology featuring 3-D tri-gate and high-k/metal
gate, optimized for ultra low power, high Performance and high density
SoC applications,” in IEDM Tech Dig., 2012, p. 44.
[3] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S.
Takagi, “Experimental study on carrier transport mechanism in ultrathin-
765
body SOI nand p-MOSFETs with SOI thickness less than 5 nm,” in
IEDM Tech. Dig., 2002, p. 47.
[4] Q. H. Wang, K. Kalantar-Zadeh, A. Kis, J. N. Coleman, and M. S.
Strano, “Electronics and optoelectronics of two-dimensional transition
metal dichalcogenides,” Nat. Nanotechnol., vol. 7, pp. 699-712,
November 2012.
[5] K. F. Mak, C. Lee, J. Home, J. Shan, and T. F. Heinz, “Atomically thin
MoS2: a new direct-gap semiconductor,” Phys. Rev. Lett., vol. 105, p.
136805, September 2010.
[6] N. Ma and D. Jena, “Charge scattering and mobility in atomically thin
semiconductors,” Phys. Rev. X, vol. 4, p.011043, March 2014.
[7] S. Kim, A. Konar, W-. S. Hwang, J. H. Lee, J. Lee, et al., “High-
mobility and low-power thin-film transistors based on multilayer MoS2
crystals,” Nat. Commun., vol. 3, p. 1011, August 2012.
[8] N. Ninomiya, T. Mori, N. Uchida, E. Watanabe, D. Tsuya, et al.,
“Fabrication of high-k/metal-gate MoS2 field-effect transistor by device
isolation process utilizing Ar-plasma etching,” Jpn. J. Appl. Phys., vol.
54, p. 046502, March 2015.
[9] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of
inversion layer mobility in Si MOSFET's: part I-effects of substrate
impurity concentration,” IEEE Trans. Electron Devices, vol. 41, pp.
2357-2362, December 1994.
[10] E. Vincent, G. Ghibaudo, G. Morin, and C. Papadas, “On the oxide
thickness extraction in deep-submicron technologies,” in Proc. IEEE Int.
Conference on Microelectronic Test Structures, 1997, p. 105.
[11] R. J. Hillard, J. M. Heddleson, D. A. Zier, P. Rai-Choudhury, and D. K.
Schroder, “Direct and rapid method for determining flatband voltage
from non-equilibrium capacitance voltage data,” in Proc. Symp.
Diagonostic Techniques for Semicond. Mater. Devices, 1991, p. 261.
[12] W. Jevasuwan, T. Maeda, N. Miyata, M. Oda, T. Irisawa, et al., “Self-
limiting growth of ultrathin Ga2O3 for the passivation of Al2O3/InGaAs
interfaces,” Appl. Phys. Express, vol. 7, p. 011201, January 2014.
[13] P.- M. D. Chow and K.- L. Wang, “A new AC technique for accurate
determination of channel charge and mobility in very thin gate
MOSFET’s,” IEEE Trans. Electron Devices, vol. 33, pp. 1299-1304,
September 1986.
[14] D. K. Schroder, Semiconductor Material and Device Characterization.
Hoboken, NJ: John Wiley & Sons, 2006.
[15] T. Fang, A. Konar, H. Xing, and D. Jena, “Mobility in semiconducting
graphene nanoribbons: Phonon, impurity, and edge roughness
scattering,” Phys. Rev. B, vol. 78, p. 205403, November 2008.