2016 International Conference on Microelectronic Test Structures (ICMTS), 28-31 Mar.

, Yokohama, Japan 9-4

Top-Gated MOS2 Capacitors and Transistors with
High-k Dielectrics for Interface Study

Peng Zhao, Angelica Azcatl, Pavel Bolshakov- Paul K. Hurley

Barrett, Robert M. Wallace, Chadwin D. Young
Department of Materials Science and Engineering, Tyndall National Institute,
The University of Texas at Dallas, University of College Cork,
800 W Campbell Rd, Richardson, TX 75080, USA Lee Maltings, Dyke Parade
E-mail: pxzl40 130@utdallas.edu Cork, Ireland

Abstract- Top-gated MOS capacitors on bulk MOS2 and
transistors of few-layer MOS2 were designed and fabricated. They
can be potentially utilized on various TMD and high-k materials
for fast and robust electrical characterization. The 3-terminal
transistor test structure shows advantages of significant
reduction of parasitic effects. C-V and I-V measurements were
successfully conducted to characterize few-layer MoSz transistors
with sub-tO nm HfOz dielectric.
Keywords - Molybdenum disulfide (MoS2); capacitor; top-
gated transistor; high-k; interface defects.
I. INTRODUCTION
Recently, transItion metal dichalcogenides (TMDs) have
been extensively researched as a channel material for field
effect transistors (FETs), due to their two-dimensional atomic
structure, and the comparable bandgap to silicon [1]-[4].
Molybdenum disulfide (MoSz), as the most studied material
among TMDs, has been investigated with high-k materials
deposition and surface functionalization in a number of
publications [5]-[10]. However, among these publications, top-
gated structures for electrical characterization of high-klTMD
gate stacks are barely reported [7], [8]. Moreover, with
complicated e-beam lithography, the small gate areas limit the
measureable capacitance. In this work, we designed and
fabricated simple top-gated capacitors and transistors, on bulk
crystal MoSz and few-layer MoSz flakes, respectively. We
successfully applied these structures to electrically characterize
the interface of high-klMoS2 gate stacks with C-V and I-V
UV-ozone surface treatment [9] on as-exfoliated samples.
TDMA-Hf and water were used as precursors for HfOz
deposition. Finally, 100 nm TiN electrodes were sputtered on
the samples through a shadow mask. Figs. 2 shows typical C-V
and I-V results of the capacitors on bulk MOS2. The frequency
dispersion of C-V curves is large, which indicates both high
gate leakage and a large number of defects at the high-klMoS2
interfacial region. A more detailed analysis can be found in our
previous publication [II]. A TEM image (Fig. 3) indicates that
a 2 nm interfacial layer was found between MOS2 and Hf02,
resulting in large number of defects and reduced Cmax.
TiN electrode
High-k dielectrics
MoS 2 crystal
(b)
TiN electrode
__ High-kon
bulk MoS 2
Fig. 1. (a) Structure of bulk MoS, capacitors; (b) Top view under a
microscope.
400 MoS2 \ Hf0 2 \ TiN MoS2 \ Hf0 2 \ TiN

measurements. The test structures we propose in this abstract Sweep Frequency

--o- 100kHz

can be potentially utilized on various TMD and high-k LL300

.3::
~ 120kHz
""""9- 150kHz
materials for fast and robust electrical study on TMD gate Cb
o
--0- 200kHz

~200
stacks while more closely mimicking a traditional fabrication ·u
process. C1I
g.100
U
Area: 2.46E-3 em""
--I!r- 4.71E_4cm"2
II. TEST STRUCTURES 1 234 -2 -1 o 1 2
Voltage (V) Voltage (V)
A. Capacitors on Bulk MoS2 Fig. 2. Left: C-V result of frequency dependence on a bulk MoS,
The capacitor test structure on bulk MOS2 is shown in Fig.l. capacitor. The dispersion suggests leakage through dielectrics and a large
Prior to any processing steps, the bulk MoSz crystal was number of defects at interfacial region. Right: I-V result of bulk MoS,
capacitors with different areas. Large leakage is observed. [11]
exfoliated using scotch tape, thereby removing the top few
layers, to obtain a clean surface. A 30 nm HfOz thin film was
atomic layer deposited (ALD) at 200°C immediately after a
This work is partially funded by National Science Foundation (NSF)
award 1407765.

978-1-4673-8793-4/16/$31.00 ©2016 IEEE 172

 (a)

. Fig. 3. TEM picture of a bulk MoS, capacitor. An unexpected

mterfacmllayer was observed at MoS,/HfD, interface, which may cause a
large number of defects and lower emax than expected. (b)
Fig. 4. (a) A fabricated transistor for few-layer TMDs. "lOl1m" and
"5I1m" are designed dimensions on photomask; (b) A zoom-in picture on
B. Few-Layer MoS2 Transistor Test Structure an MoS, flake. The scale bar length is 511m.

To reduce the effect of leakage and to examine the interface

on few-layer MoS z, we designed and fabricated few-layer
MoSz transistors. Also, to potentially remove the interfacial Thereafter, 15 minutes of in-situ UV -ozone surface treatment
layer shown in Fig. 3, we conducted in-situ UV-ozone [9] was performed and 8 nm of HfOz was deposited at 200T
treatment [9], instead of ex-situ treatments on bulk capacitors. immediately after the treatment. The final step of fabrication
The transistor structure for few-layer MoS z is shown in Fig. 4, was patterning and deposition of Au/Cr metal gate. The high-k
and the fabrication flow is shown in Fig. 5. Before device material on source/drain pads was removed by buffered oxide
fabrication, 270nm SiOz was thermally grown on highly p-type etch to enable probing. Electrical measurements in this work
doped Si wafer as a substrate. Few-layer MoSz flakes were were performed using a Keithley 4200 Semiconductor
exfoliated by scotch tape from natural MoSz crystals and Characterization System and an Agilent E4980A LCR meter.
placed on the SiOz. Using photolithography with a lift-off
process, the source/drain were formed with Au/Ti (380/20nm).

-"",,,._.,,,,,,_.,,,,,._,,,,,," ........................................."_...",,._. .,,-""""'-""'"

Source and Drain
Few -laye r TMD

•
AU/Ti 380nm/ 20nm

r--
,
'\ 1
2Z.0JJW.Ib.e.wJ...~iO

p++Si
r p++Si [ p++Si
I
Step 1: 270nm thick therm al SiO, Growth Step 2: Mech anical exfoliation of few- Step 3: Source/drain patterning b y
layer TMDmateri al photolithography and lift-off
... __ _ _ _
.. ... _-_ ........ .. ............ ........... ........... ................ .......... ..."._-_.. .. _-_." ....
" "

Gate

1 1 1 1 1 E ,
High-k on TMD

-=
Au/er 250nm/ 50nm
I
!

I p++Si 1 1 p++Si
1 [ p++Si
I
Step 5: Atomic layer deposition of high·k
Step 4: TMD s u
rface functionalization Step 6: Topgate patterning b y
on TMD (Snm HfO, i nthis work)
photolithography and lift-off

Fig. 5. Fabrication flow offew-Iayer TMD transistors using photolithography and liftoff process.

173
 III. RESULTS AND DISCUSSION
Fig. 6 shows the [DS-VGS at VDS = 0.5 V. An excellent
on/off ratio of 10 6 was observed, with an ultra-low leakage
N
- E
o
800

u:
-
current on the gate. The dimensions of the channel were 200kHz to 2kHz
600
WXL=9.5flm x 6.5flm, with an 8 nm MoSz thickness from the s::::
AFM results. Fig. 7 shows the [DS-VDS curves with VGS Frequencies
Q)
changed from -4V to OV. A non-linear region was observed at 0400 --o- 2kHz
low drain-source voltage, likely because of Schottky barriers at s:::: --O- 5kHz
the source/drain contacts due to this unannealed device [12]. ~ ---e-- 10kHz
Fig. 8 shows higher frequency C-V measurements results. - r - 20kHz
Since this transistor operates in accumulation mode, the ~200 --¢- 50kHz
c. --<I- 100kHz
reaction of the majority carriers (electrons) to the ac signal is CO
U --i>- 200kHz
observed. In contrast to our previous study on the ex-situ UV-
ozone treatment [11], these C-V frequency dependence results O~----~~~~----~----~----~

showed a highly improved high-klMoSz interface, which has -4 -3 -2 -1 0 1 2

significantly less dispersion and lower gate leakage due to the Gate Voltage (V)
in-situ UV-ozone treatment and this few-layer TMD transistor
Fig. 8. Split C-V: frequency dependence (same device in Fig.7). The
structure. As the frequencies are swept, a "hump" in the "hump" at the depletion region indicates the existence of interface traps for
depletion region is seen. In conventional Si MOSFETs, this this unannealed sample.
"hump" is usually attributed to interface traps in the bandgap.
Another transistor (Figs. 9-11) with 2-3 layers of MoSz
-b- Drain Current (IDS) Vds=O.5V flake, however, showed similar C-V dispersion (Fig. 11)
--0- Gate Leakage (IIG Il compared to the bulk samples. [t means even with the in-situ
1 0-7~~_ _--::~~~~~
treatment, under certain circumstance (e.g. MoSz thickness,
surface roughness), the interfacial layer can still possibly exist.
; {150100c a
.s
However, since the effect of leakage is minimized compared to
bulk samples, this C-V dispersion can be potentially analyzed
J~ 50
quantitatively. In summary, the few-layer TMD transistor can
be used to extract C-V data along with [-V data fast and
o Linear
-4 -3 -2 -1 0
accurately, significantly reducing the influence from leakage
Gate Voltage (V) and series resistance. More work is needed to improve the
source/drain contacts by selection of other metals or by doping.

-4 -3 -2 -1 0
Gate Voltage (V)
Vds=O.5V
Fig. 6. IDs-V GS and gate leakage of a 12-layer MoS2 transistor. Inset:
IDS- V GS in linear scale. On/off ratio 106 was observed. Channel: WxL=
9.5J.(m x6.5J.(m. HfD2 thickness: 8nm.

-E 0.4

<c:::t 0.3
2:
:g0.2 -1 o 1
Gate Voltage (V)
0.1
Fig. 9. IDS-VGS and gate leakage of a 2-3 layer MoS2 transistor.
Channel: WxL= 17J.(mx6.5J.(m. Hf0 2 thickness: 8nm.
0.0 t>O-04oI''IP'I!!

o 1 2 3
VDS (V)
Fig. 7. IDS-VDS curves (same device in Fig.6). The non-linear region
at low drain voltage indicates non-ideal contacts due to the unannealed
device.

174
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