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Vlsi Design Unit 2
Vlsi Design Unit 2
Vlsi Design Unit 2
UNIT – II
VLSI CIRCUIT DESIGN
PROCESSES: VLSI Design Flow,
MOS Layers, Stick Diagrams, Design
Rules and Layout, 2μm CMOS
Design rules for wires, Contacts and
Transistors Layout Diagrams for
NMOS and CMOS Inverters and
Gates, Scaling of MOS circuits.
VIDYA SAGAR P
VLSI DESIGN
This Figure provides a more simplified view of the VLSI design flow, taking into account
the various representations, or abstractions of design - behavioral, logic, circuit and mask
layout. Note that the verification of design plays a very important role in every step during
this process. The failure to properly verify a design in its early phases typically causes
significant and expensive re-design at a later stage, which ultimately increases the time-to-
market.
Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighboring steps,
and occasionally even remotely separated pairs. Although top-down design flow provides
an excellent design process control, in reality, there is no truly unidirectional top-down
design flow. Both top-down and bottom-up approaches have to be combined. For instance,
if a chip designer defined an architecture without close estimation of the corresponding
chip area, then it is very likely that the resulting chip layout exceeds the area limit
of the available technology. In such a case, in order to fit the architecture into the
allowable chip area, some functions may have to be removed and the design process must
be repeated.
MOS layers :
MOS circuits are formed on four basic layers:
o N-diffusion
o P-diffusion
o Polysilicon
o Metal
These layers are isolated by one another by thick or thin silicon dioxide insulating layers.
Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.
Ox3
Via
Metal2
Ox2
Active contact
Metal1
Ox1
n+ n+ n+ n+ Poly Si
P-substrate
Stick Diagrams:
VLSI design aims to translate circuit concepts onto silicon, stick diagrams are a means of
capturing topography and layer information - simple diagrams, Stick diagrams convey
layer information through color codes .A stick diagram is like a layout Contains the basic
topology of the circuit, each wire is assigned a color (layer) Crossing wires must be on
different layers. Wires are drawn as sticks with no width. The size of the object is not to
scale.
Stick diagrams are Cartoon of a layout. Shows all components. Does not show exact
placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of
compliance with layout or design rules.
Useful for interconnect visualization, preliminary layout compaction, power/ground
routing, etc.
n-diffusion Green
p-diffusion yellow
polysilicon red
metal-1 blue
via black
demarcation line --------------------------- brown
Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.
Rule 2: When two or more ‘sticks’ of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection
explicitly).
Rule 3. When a poly crosses diffusion it represents MOSFET. If contact is shown it is not
transistor.
nMOSFET pMOSFET nMOSFET Depletion Mode
Rule 4.
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all nMOS will have to be on the other side.
When polysilicon crosses n-diffusion a transistor forms, when poly (red) crosses
diffusion (green or yellow).
nMos Invrter :
BiCmos inverter:
Figure shows the way of representing different layers in stick diagram notation and mask layout
using nmos style.Figure l shows when a n-transistor is formed: a transistor is formed when a
green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion
mode transistor is represented in the stick format.
Encodings for CMOS process:
Figure 2 shows when a n-transistor is formed: a transistor is formed when a green line
(n+ diffusion) crosses a red line (poly) completely. Figure 2 also shows when a p-
transistor is formed: a transistor is formed when a yellow line (p+ diffusion) crosses a
red line (poly) completely.
Encoding for BJT and MOSFETs:
The main objective of design rules is to achieve a high overall yield and reliability while
using the smallest possible silicon area, for any circuit to be manufactured with a
particular process.
Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n
and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ.
Similarly it shows for other layers.
Mask Summary: Metal rules may be complicated by varying spacing dependent on
width: As the width increases, the spacing increases. Metal overlap over contact might
be zero or nonzero.
Figure shows the design rule for the transistor, and it also shows that the poly should
extend for a minimum of 2λ beyond the diffusion boundaries. (gate over hang distance)
Mask Summary: The basic masks (in addition to well masks) used to define
transistors, diffusion interconnect (possibly resistors), and gate interconnect are active,
n-select, p-select, and polysilicon. These may be called different names in some
processes. Sometimes n-diffusion (ndiff) and p-diffusion (pdiff) masks are used to
alleviate designer confusion.
Via Rules: VIA is used to connect higher level metals from metal1 connection.
Processes may vary in whether they allow stackedVias to be placed over polysilicon and
diffusion regions. Some processes allow vias to be placed within these areas, but do not
allow the vias to straddle the boundary of polysilicon or diffusion.
Contact Cuts:
While making contacts between poly-silicon and diffusion in nMOS circuits it should
be remembered that there are three possible approaches—1.poly to metal then metal to
diff.
2. Buried contact poly to diff.
3. Butting contact (poly. to diff. using metal).
Among the three the latter two, the buried contact is the most widely used, because of
advantage in space and a reliable contact. At one time butting contacts were widely
used, but now a days they are superseded by buried contacts.
Other Rules: The passivation or overglass layer is a protective layer of Si02 (glass)
that covers the final chip. Appropriately sized openings are required at pads and any
internal test points. Some additional rules that might be present in some processes are
as follows:
Extension of polysilicon in the direction that metal wires exit a contact.
Extension of metal end-of-line region beyond a via.
MOSIS Scalable CMOS Design Rules: Academic designs often use the λ-based
scalable CMOS design rules from MOSIS because they are simple and freely available,
and they allow designs to easily migrate from one process to another. These advantages
come at the expense of being conservative because they must work for all
manufacturing processes.
MOSIS actually has three sets of rules: SCMOS, SUBM, and DEEP.
The SUBM rules are somewhat more conservative than SCMOS rules. DEEP rules are
even more conservative. The more conservative rules allow you to use a slightly smaller
value of λ while still satisfying all of the micron design rules for a process.
Table 2 lists some of the foundry processes MOSIS has offered and the associate value
of λ for the different rule sets. For example, the AMI 0.5 µm process can use the
SCMOS rules with λ = 0.35 µm or the SUBM rules with λ = 0.30 µm. SUBM rules are a
good choice for class projects because they are somewhat easier to use than DEEP (no
half-λ rules), while still being compatible with most processes. Some processes offer a
second polysilicon layer for floating-gate transistors and poly-insulator-poly capacitors
used in analog circuits.
For design rules where the minimum drawn gate length exceeds the feature size,
MOSIS applies a polysilicon bias to shrink the gates by a uniform amount before masks
are made.
For example, in the SUBM rules for the AMI 0.5 µm process with λ = 0.3 µm, a bias of-
0.1 µm is applied to all polysilicon. Thus, a 2 λ transistor gate is 0.5 µm rather than 0.6
µm and a 4 λ gate is 1.1 µm rather than 1.2 µm.
In the diagram above each of the arrangements can be merged into single split
contacts.
From the above diagram it is also clear that split contacts may also be made with
separate cuts.
The 3λ. metal width rule is a conservative one but is implemented to allow for the fact
that the metal layer is deposited after the others and on top of them and several layers
of silicon dioxide, so that the surface on which it sits is quite 'mountainous' . The metal
layer is also light-reflective and these factors combine to result in poor edge definition.
In double metal the second layer of metal has an even more uneven terrain on which to
be deposited and patterned. Hence metal 2 is often wider than metal 1.
Metal to metal separation is also large and is brought about mainly by difficulties in
defining metal edges accurately during masking operations on the highly reflective
metal. All diffusion processes are such that lateral diffusion occurs as well as impurity
penetration from the surface. Hence the separation rules for diffusion allow for this and
relatively large separations are specified. This is particularly the case for the p-well
diffusions which are deep diffusions and thus have considerable lateral spread.
Transitions from thin gate oxide to thick field oxide in the oxidation process also use
up space and this is another reason why the lambda-based rules require a minimum
separation between thinox regions of 3λ. In effect, this implies that the minimum
feature size for thick oxide is 3λ.The simplicity of the lambda-based rules makes this
approach to design an appropriate one for the novice chip designer and also, perhaps,
for those applications in which we are not trying to achieve the absolute minimum
area and the absolute maximum performance. Because lambda-based rules try 'to be all
things to all people', they do suffer from least common denominator effects and from
the upward rounding of all process line dimension parameters into integer values of
lambda.
.
GND In VD D
A A’
Out
(a) Layout
A A’
n
p-substrate Field
+ + Oxide
n p
(b) Cross-Section along A-A’
X n-well
X
x x
x x X
X
Gnd
Gnd
X X
x x
X X
Gnd
x Gnd
x
NAND2 Layout:
VDD VDD
X X X
a.b
Gnd a.b
a b
X X
Gnd
a b
NOR2 Layout :
VDD
VDD
X X
ab
ab
a b X X X
Gnd
a b
Gnd
TRANSMISSION GATE :
Symbol schematic
stick diagram
layout
Types of scaling:
Scaling Models
1. Full Scaling (Constant Electrical Field): Ideal model – dimensions and voltage scale
together by the same scale factor. Requires to reduce power supply voltage with the
reduction of feature size. The electric field across the gate-oxide does not change when
the technology is scaled.
2. Fixed Voltage Scaling (Constant voltage scaling): Most common model until
recently – only the dimensions scale, voltages remain constant. Increasing electric field
leads to velocity saturation, mobility degradation, and sub threshold leakage
3. General Scaling: Most realistic for today’s situation – voltages and dimensions scale
with different factors
• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product
Implications of Scaling:
Improved Performance
Improved Cost
Interconnect Woes
Power Woes
Productivity Challenges
Physical Limits
Limitations of Scaling
Effects, as a result of scaling down- which eventually become severe enough to prevent
further miniaturization.
o Substrate doping
o Depletion width
o Limits of miniaturization
o Limits of interconnect and contact resistance
o Limits due to sub threshold currents
o Limits on logic levels and supply voltage due to noise
o Limits due to current density