DRAMs
Since eDRAM memory blocks are approximately
Dynamic random access memory (DRAM) primarily
serves as the main memory for all modern computing
devices. The largest customers for DRAM are the
personal computer and server markets. However,
fueled by the popularity of hand-held computing
devices and organizers to access the Internet and the
World Wide Web, the Semiconductor Industry As-
sociation (SIA) projects the DRAM market to grow
from an estimated US$29 billion in 2000 to US$44
billion in 2002 (SIA 2000). A second independent
market research source projects the DRAM market to
reach US$76 billion in 2002 (Dataquest 2000).
Embedded DRAM (eDRAM) is a newer—and still
developing—technology that is largely based on
DRAM know-how but serves markets that are more
driven by the rate and amount of information flow to
a processor—more commonly referred to as band-
width. The presence of memory—and lots of it—close
to a processor allows information to be processed
more quickly and efficiently effectively enhancing the
performance of a system. The largest market for
eDRAMs is in graphic accelerators for personal
computers and server boxes. However, driven by the
presence of the Internet, which drives information
speed and immense storage requirements, eDRAM
technology is widely anticipated to play a major role in
four key hardware areas:
(i) wired microelectronics (e.g., network router
systems);
(ii) wireless microelectronics (e.g., hand-held tele-
phones and computers);
(iii) storage systems (as part of the read\write
electronics in hard-disk controllers); and
(iv) microprocessor unit (MPU) systems.
The worldwide revenue for eDRAM is projected to be
US$7.5 billion in 2002 (IBM press release, February
22, 1999).
One of the more intriguing areas in which eDRAM
is envisioned to make a big impact is in its use as an on-
chip memory of an MPU—typically referred to as
cache. MPUs cannot process data continuously and
must store data on a temporary basis in these cache
(memory) blocks. An MPU commonly contains three
levels of on-chip memory in which to store data
temporarily: (i) L1 (for level 1 cache), (ii) L2 (for level
2 cache), and (iii) L3 (for level 3 cache). The des-
ignation L1, L2, etc., is based on the hierarchical
methodology of data storage and data access. The first
place where a processor unit will store and look for
data is the L1 cache. If the data cannot be found in the
L1 cache, the processor will look in the L2 cache and
so on. This role is exclusively filled by static random
access memory (SRAM). However, as the MPU
requirement of on-chip memory increases from several
hundred kilobits (Kb) to several tens of megabits (Mb),
the size of SRAM memory blocks presents severe
manufacturing constraints owing to the resultant die
size.
4–8 times smaller than SRAM memory blocks, repla-
cing SRAM-based cache with eDRAM-based cache
may mitigate the problem to a large extent.
Embedded DRAM can be implemented in both a
DRAM and a logic technology. There are key
compromises that need to be made in either case.
When proceeding from a DRAM base, one retains the
advantage of a small commodity DRAM-like cell size.
However, there is a significant loss in performance for
logic devices. This performance penalty can be equiv-
alent to going back a couple of logic generations.
Additionally, the lower drive capability of the devices
in DRAM technology means that the devices need to
be made large to drive any reasonable type of load.
Ironically, while the DRAM-based technology yields
a smaller DRAM array, it actually is a generation
behind in logic density! Furthermore, DRAM-based
logic devices require custom libraries for logic im-
plementation. For these reasons, DRAM-based
eDRAM is used mainly in DRAM-intensive appl-
ications in which logic performance and large library
availability are of secondary importance. Where logic
performance is at a premium and where the appl-
ications require compatibility with a high-speed logic
library with numerous standard cell selections, it is
necessary to proceed from a logic base. Within the
context of logic-based eDRAM, a slightly larger cell
size will have to be tolerated. In both cases, however,
the overall process complexity and costs are essentially
similar.
This article describes the present and future chal-
lenges of fabricating DRAM and eDRAM based on
trench capacitor technology—or more formally
known as substrate plate trench (SPT) technology (Lu
et al. 1985). The objective of this article is twofold.
First, to have the reader appreciate the complexities in
processing DRAM, and second, to understand the
materials challenges that exist in developing present
and future DRAM and eDRAM technologies. How-
ever, before the material challenges are delved into,
some DRAM and eDRAM ‘‘basics’’ are briefly
described. Therefore, background sections are pro-
vided in this article that describe: (i) how a DRAM cell
(bit) works, (ii) the technological drivers (and dif-
ferences) between DRAM and eDRAM, and (iii) a
process flow describing the steps in the front-end-of-
line (FEOL) fabrication of trench-based DRAM and
eDRAM. Following the background information
sections three key areas of materials research in
DRAM and eDRAM are then described: (i) capacitor
dielectrics, (ii) insulator materials, and (iii) integration
of low-resistive materials such as copper for wires in
the back-end-of-line (BEOL) and metal silicides.
1. How Does DRAM Work?
All modern DRAM is based on the one transistor–one
capacitor (1T–1C) cell concept (Dennard 1968) (see
1
DRAMs
Fig. 1). Cells are arranged in arrays; array blocks of
1 Mb, 4 Mb, or larger are typical. Accessing a cell in an
array is accomplished through a set of orthogonal
wiring structures called bitlines and wordlines. Wires
and contacts that write and read charge from a
capacitor are called bitlines and bitline contacts. By
convention, bitlines take on a column address. Long
transistor gates (wires) run perpendicular to the bitline
direction and allow charge to be written into or read
out of a capacitor; these gates are known as wordlines.
By convention, wordlines take on a row address. For
the purposes of this article, the basic operation is
described of writing and reading a signal (e.g., a logical
‘‘1’’) into and out of a DRAM cell as shown in Fig. 1:
(i) A potential is applied to the bitline by a circuit
outside the array and the array transistor is turned on
to allow charge to be written into the capacitor. A
bitline contact, which lands on the active area that the
capacitor resides, holds the voltage level and transfers
the voltage onto the active area and the charge flows
into the capacitor.
(ii) After writing a charge into the capacitor, the
bitline and transistor are turned off; a junction (e.g.,
simple n+\p) that is tied to the capacitor is held in a
reverse bias condition to hold charge in the capacitor.
Figure 1
Schematic of 1 transistor—1 capacitor cell (Dennard 1968). Shown within the schematic is the current flow when ‘‘writing’’
a logical ‘‘1’’ into the capacitor.
2
(iii) However, as the word ‘‘dynamic’’ suggests,
charge does leak away from the capacitor. After
several tens or hundreds of milliseconds, the bitline
and wordline are turned on again to read and refresh
the capacitor. The bitline potential changes by only a
small fraction (" 20%) of the capacitor level, and
typically this voltage is only several tens of millivolts.
The process begins by transferring the voltage level left
in the capacitor onto the bitline. This reduced voltage
level is fed into a circuit outside of the array which can
sense this change in voltage (also known as a sense
amplifier). Once the amplifier senses the change, the
bitline voltage is amplified to its previously high level.
The capacitor is then refreshed by turning the wordline
on to allow charge to flow back into the capacitor.
2. DRAM and eDRAM Technology Drivers
Although DRAM and eDRAM share similar proces-
ses and design concepts, there are also considerable
differences. Key DRAM technology drivers are the
following:
$ Maintaining and extending deep UV (DUV)
lithography to smaller and smaller dimensions.

Figure 2
(a) SRAM cell vs. (b) eDRAM cell (offered in 0.18 µm IBM SA-27E Logic Library).
$ Reducing cell size and maximizing array ef-
ficiency. Minimizing cell area entails reducing ca-
pacitor area and incorporating borderless contacts in
the array (i.e., contacts that immediately abut the
transistor).
$ Maximizing retention time. Because charge leaks
away from the node junction that is tied to the
capacitor, the DRAM capacitor needs to be constantly
refreshed—typically in the range of tens to hundreds
of milliseconds. Refreshing often, however, means
more power consumption, and for portable devices
battery life will be compromised. In order to provide
femptoamp (10−"& A) leakage in a cell, graded junction
profiles are purposely formed in the array.
$ Minimizing cost. Devices in DRAM chips are
purposely made to be simple and cheap. Devices tend
to be single-oxide type and the number of devices
necessary to operate the chip is kept at a minimum.
Diffusions need not be silicidized, wordlines consist
of a stack of doped polysilicon with a silicide (also
known as polycide), and metal wires are composed of
aluminum.
As the motivation for making eDRAM is to have
the memory arrays as close as possible to the processor,
the thinking here is to make eDRAM a ‘‘performance-
driven’’ DRAM that is embedded next to the pro-
DRAMs
cessor. Indeed, as previously mentioned, it is widely
anticipated that eDRAM will replace some, if not
most, of the on-chip memory now in the form of
SRAM. An SRAM cell is usually configured as six
transistors (6T layout)—four n-type field effect tran-
sistors (NFETs) and two p-type FETs. A logical ‘‘1’’
state, for example, is held in a simple transistor latch
condition. Since SRAM cells are logic-based devices,
accessing the logical state is very fast (read access times
of 5 ns or less are not uncommon). In order to access
information from an eDRAM cell, a read and a
rewrite operation must be performed (the rewrite
operation is not required in SRAMs). This makes the
replacement of SRAM cache with eDRAM cache not
completely transparent.
However, it is quite clear that one can save signifi-
cant amounts of silicon real estate if cache systems
shift from SRAM based to eDRAM-based. In many
modern microprocessors, SRAM cache can take up to
50–70% of the entire real estate of the microprocessor,
depending on the amount of cache present on the chip
(Iyer and Kalter 1999). One method of compressing
the microprocessor die size is to replace SRAM cache
with eDRAM cache. Figure 2(a) shows a top-down
schematic of a 6T–SRAM cell and Fig. 2(b) shows a
top-down schematic of the 1T–1C cell that is offered in
3
DRAMs

the 0.18 µm logic family of IBM. The eDRAM cell size (a)
is " 6–8 times smaller than SRAM at the same
lithographic dimensions (Crowder et al. 1998). Thus,
Bitline
one can easily see the benefit of replacing SRAM cache
with eDRAM cache—for the same memory space on a N+ Poly Si
Contact
microprocessor chip, one can place more eDRAM Wordline
memory than SRAM memory. Since now the pro- N Junctions STI

cessor has a larger memory space to temporarily store Buried

Strap
data, the effect on the processor and system is much P-Well
Oxide Collar

improved performance. Buried N-Well

Needless to say, eDRAM technology tends to Cell Features:
accentuate performance such that assimilation into 8 lm deep trench
the logic world can be as seamless as possible. eDRAM ON node dielectric (Teq = 5.5 nm) N+ Poly Si
self-aligned (maskless) buried strap
must operate at logic voltages, which, unlike DRAMs, shallow trench isolation (STI)
tend to be unregulated and lower (e.g., power supply 8.2 nm gate oxide
polycide gate conductor
voltages for eDRAM are (will be) 1.8V (1.2V) whereas self-aligned/borderless bitline contact
metal bitline
DRAM supply voltages are (will be) 3.3V (2.5V)). To
this end, eDRAM parts use many features that logic
parts tend to possess:
$ dual work function, thin oxide surface channel
(b)
FETs to maximize transistor drive currents;
$ scaled devices that operate at reduced voltages
and shorter channel lengths; Copper m 2

$ cobalt salicide technology in the logic circuitry of

the eDRAM chip to decrease parasitic resistances; Dielectric Cu
Contact
Stud

$ bordered tungsten contacts (i.e., contacts that do Cu

Bitline
not land next to transistors and are set some distance Bordered bitline contact
BPSG
Poly AWL Poly PWL

away so as to minimize effects of the heavy dose STI

Shallow trench
Isolation
Trench
implant required for ohmic contact formation) to Buried Strap
P-Well
Oxide Poly-Si
Collar
reduce contact resistances; and Buried N
Plate N+ Poly-Si
$ copper metallurgy for metal wiring.

3. Process Flow for DRAM

The process methodology of trench-based DRAM is
to first form the capacitor in the silicon substrate as
opposed to on or above the silicon substrate (i.e.,
stacked capacitor). From a processing standpoint,
capacitor formation in the silicon creates a very planar
surface—this eases the fabrication of transistor devices
and contact levels. From an operation standpoint, the
trench capacitor provides better noise immunity and
higher soft error rate (SER) resistance than stacked
capacitors.
The FEOL process flow of creating a trench
capacitor cell in the 0.25 µm DRAM technology—
developed by IBM, TOSHIBA, and Siemens Micro-
electronics (now INFINEON)—is described below
(also refer to the cross-section of the trench capacitor
cell in Fig. 3(a) for reference) (Bronner et al. 1995).
3.1 Deep Trench Module
Trenches are lithographically defined and reactive ion
etched (RIE) into the silicon substrate. Depths of the
deep trench are typically 6–7 µm. Aspect ratios of 30: 1
(depth:width) are typical for trench capacitors. A
silicon nitride node dielectric sits along the sidewalls
and bottom surface of the deep trench. Above the
Figure 3
Cross-section schematics of trench-based capacitor cells in;
(a) DRAM, (b) eDRAM.
node dielectric is an oxide collar (30–40 nm thick) and
wraps around the upper portion of the trench. This
structure is used to prevent a vertical parasitic
leakage—a MOSFET that is gated by the trench-
fill—that can develop along the trench sidewall.
Located at the very top of the trench is a structure
called a ‘‘buried’’ strap (‘‘buried’’ because the strap sits
below the silicon surface). The strap is the conduit
allowing charge to be written into and read out of the
capacitor. This is also referred to as the node junction
as this is the junction that is held in the reverse bias
condition to minimize charge leakage. The conducting
material of the trench is an arsenic-doped silicon fill.
This fill serves as one of the two plates needed to
charge the silicon nitride dielectric. The second plate
lies outside of the trench in the silicon substrate. The
plate, formed prior to the deposition of the node
dielectric, is a heavily doped arsenic diffused layer
created by outdiffusion of arsenic from an arseno-
silicate glass (ASG).

4

3.2 Shallow Trench Isolation Module
Following capacitor formation is the shallow trench
isolation (STI) module. Here, isolation areas are
defined by a masking process and a shallow silicon
etch is conducted. The depth of the isolation is
typically 250–350 nm below the silicon surface. After
an oxidation step, the isolation trenches are filled by a
deposited oxide and planarized (via polishing) back to
the silicon surface.
3.3 DeŠice Well Module
After completion of the STI process, device wells or
tubs are formed in the chip. Wells are formed to isolate
NFETs and PFETs from one another and are created
via high-energy (" 100–600 keV) but low-dose
(" 10"$–10"%) implants. In the DRAM array, a cell sits
in a retrograde p-well. Here, implant energy and dose
conditions are chosen to minimize vertical leakage
along the trench sidewall surfaces and lateral leakage
between cells. In addition, the threshold voltage
implant for the array device is also conducted in this
process.
3.4 Gate Conductor Module
Following the well formation is the gate conductor
module. Here, transistors in the DRAM array, as well
as in the supporting logic circuitry, are defined on the
wafer. A gate oxide (6–8 nm) is grown on the surface
and a heavily (phosphorus) doped poly layer is
deposited followed by a low-resistive tungsten silicide
(WSi ) layer. A thick silicon nitride film is deposited
on top# of the poly-WSi gate stack—the nitride is used
to protect the stack #during the array (borderless)
contact etch. The entire gate conductor stack is then
defined by a mask step and reactively ion etched down
to the gate oxide.
3.5 Borderless Contact Module
A boron phosphosilicate glass (BPSG) is deposited on
the wafer to fill the spaces between the gate conductors
and is annealed to improve structural integrity. After
polishing once again, contact vias are lithographically
defined and reactively ion etched to active area
diffusions and gate conductors. To minimize cell area,
the contacts in the DRAM array are borderless.
Contact holes are filled with heavy n+ (phosphorus)
polysilicon and are planarized.
3.6 Bitline Wiring Module
After contact formation, the bitline wiring level is
defined lithographically and etched into the BPSG.
Tungsten is then deposited and planarized off the
DRAMs
BPSG. This wiring level completes the formation of
the structures that are required for basic memory
operation. Typically, two additional levels of metal
wires (aluminum-based metallurgy) are added beyond
the bitline, principally for circuits that drive signals
into the array such as wordline and bitline drivers.
The process flow for eDRAM is very similar to that
of the base DRAM process but with some exceptions
(see Fig. 3(b)):
(i) The gate conductors in the eDRAM array are
solely n+ polysilicon and do not consist of the DRAM
stack of n+ poly\WSi \Si N . The reason for this
design is in the tight #tolerances
$ % for the conductor
channel lengths necessary for consistent logic per-
formance. The presence of the thick nitride film and
WSi can bias the gate poly etch, causing variations in
#
transistor channel dimensions across the wafer.
(ii) The higher resistances in the eDRAM array are
offset by designing or ‘‘stitching’’ a metal wire onto the
gate conductor. ‘‘Stitching’’ metal wires onto the gate
conductor is present more in eDRAM than in
DRAMs.
(iii) Logic circuits use a cobalt salicide process to
lower diffusion and gate conductor resistances. The
silicide is prevented from forming in the array by
masking.
(iv) The bitline contacts in the array are formed with
tungsten and typically use a high-dose contact implant
prior to the tungsten deposition for ohmic conduction.
The presence of the high-dose implant necessitates the
bordered contact process.
(v) The bitline and metal wiring in eDRAM is
composed of copper instead of tungsten and alumi-
num, conventionally used for DRAM. The substi-
tution of copper for tungsten and aluminum helps
reduce parasitic resistances.
4. Future Trends of DRAM and eDRAM Materials
Technology
Table 1 outlines the dimensions used for the trench
capacitor cell in DRAM generations starting from the
0.25 µm node and onto the 0.14 µm node. Note the
significant size difference between the 0.25 µm cell and
0.14 µm cell (Fig. 4). From the data presented in Table
1, one can anticipate some of the material challenges
that will have an impact on DRAM and eDRAM yield
and retention. Three key areas of materials
research are highlighted below.
Node capacitors. As the cell area decreases for each
new generation, one also observes the natural re-
duction of capacitor area—this tends to drive down
capacitance. Since the charge (Q) written into a cell is
equal to CV (where V is the bitline voltage l supply
voltage, Vdd), the effective charge in the cell will be
lower if nothing is done to counteract the capacitance
decrease. Furthermore, designers of future DRAMs
are looking to lower the supply voltage, Vdd, to
5
DRAMs
Table 1
Trench cell dimensions and approximate cell areas of
0.25 µm node to 0.14 µm node.
Ground rule (i.e., minimum
feature size in and Cell area
minimum spacing between cells) (µm#)
0.25 0.605
0.20 0.380
0.18 0.260
0.14 0.160
emphasize low-power markets. Hence, providing the
necessary charge into a DRAM cell will be of
paramount concern in the near future.
Parasitic interleŠel\intraleŠel insulators. As metal
line pitch decreases, parasitic oxide capacitance be-
comes a major problem. Since charge can be ‘‘lost’’ or
shaved by oxide, a signal written into a 0.25 µm node is
more likely to be stronger than one written into a
0.14 µm node even though the applied voltage is
equivalent (i.e., 1.8 V)
Lower resistance materials. In eDRAM chips, it is
imperative that charge be written into and read out of
the capacitor quickly—even at low temperatures. A
commodity DRAM part is required to function at
0 mC; an eDRAM part is required to operate at k40 mC
as this is a requirement of logic circuit operation.
Thus, resistances in eDRAM parts should be as low as
possible.
4.1 Node Capacitance Issues
Silicon nitride (Si N ) is the most common dielectric
$ % and stacked DRAM capacitors
material used in trench
(i.e., DRAMs with capacitors defined above the silicon
substrate). Nitride replaced oxide as the dielectric
towards the end of the 1980s as its dielectric constant
is higher than that of oxide (ε of nitride " 7 vs. ε of
oxide " 4) and its leakage as a thin film is similar to
that of oxide thin films. The nitride dielectric has been,
and will most likely be, the dielectric of choice for the
0.18 µm and 0.14 µm node. Nitride is a very robust
material and, more importantly, its material properties
can withstand high-temperature processing. For
trench capacitors the quality of the node dielectric, i.e.,
maintaining its dielectric properties while providing
low leakage, is extremely important as temperatures
can approach " 1000–1100 mC. Since capacitance is
proportional to the surface area of the capacitor and
inversely proportional to the dielectric thickness,
processes to increase surface area and thin the di-
electric have been actively pursued. Two methods of
increasing surface area are etching deeper trenches or
depositing thin polysilicon islands (known as ‘‘hemi-
spherical grains’’ (HSGs)) on the trench sidewalls.
Polysilicon grains nucleate on the silicon surface
without forming a continuous layer, resulting in
increased surface area (Watanabe et al. 1995).
6
However, efforts to increase surface area can only
go so far. As the spacing between capacitors becomes
closer, increasing the lateral surface area may create
isolation problems between capacitors. Moreover,
etching deeper trenches will be more time consuming
and will increase the cost. Thinning the nitride
dielectric also has its limitations. At 3 nm or less, which
is an approximate thickness for the 0.10 µm node, the
leakage through the nitride film may be too high—even
at applied voltages of 1.0 V. At this thickness di-
mension tunneling of electrons through the film will be
a source of concern. Hence, at the 0.10 µm node,
changes in the dielectric film may be necessary to boost
capacitance.
(a) Metal oxide capacitors. Research on ‘‘higher’’
epsilon dielectrics in stacked capacitors, and their use
as a node capacitor film, has been very active since
the mid-1990s. Table 2 is a list of dielectric materials
that have been targeted for use in future DRAM
technology.
(b) PeroŠskite structures. The titanates (e.g., SrTiO )
and lead-based perovskite structures (PbZrTiO$)
$
have received the most attention as ε of these par-
ticular films lies between 400 and 1000. However,
there are serious limitations to the use of perovskite
materials in DRAM:
(i) Leakage. Perovskite structures tend to be one to
two orders of magnitude higher in leakage than oxide
and nitride dielectrics.
(ii) Reliability. With perovskite structures, a leakage
current acceleration occurs through the film after
extended operation. This degradation effect could pose
problems on perovskite-based DRAMs as DRAMs
must often meet an operating lifetime specification of
10 years or greater.
(iii) Electrode materials. In order to contact the
dielectric, one must choose materials that do not
destroy the integrity of the dielectric. Thus far,
platinum and RuO show the most promise. The main
#
issue with using platinum or RuO materials appears
#
to be in the patterning of the materials. Processing
tools in many fabricators do not have the capability
for etching these materials.
(iv) Incompatibility in trench-based DRAMs. The
perovskite structures tend to be unstable under high
temperatures that preclude their use as dielectrics in
trench capacitors.
(c) High-dielectric materials for trench capacitors.
Studies of dielectric materials that can withstand
high-temperature processing are limited and the
amount of research devoted to new trench dielectrics
is much less than research on stacked capacitor di-
electrics. There are, perhaps, three or four materials
 DRAMs

that have shown some promise as a replacement to wires becomes an increasingly difficult problem to
Si N : solve owing to the ‘‘charging’’ of the insulator.
$(i)% Ta O , HfO , ZrO . Of the three dielectrics Coupling between metal lines increases the probability
mentioned # &here, Ta
# O is# the material that is now of charge imbalances leading to subtle device failures
being or closest to being# & used in stacked capacitors. As to whole system failures. Because operating voltages
for possible use as a dielectric in trenches, early studies are decreasing as well, a higher percentage of the signal
have shown that Ta O may be unstable with respect running on a metal line may be transferred to
# &
to silicon at high temperatures, forming TaSix and the insulator material rather than to the devices
SiO . In addition, it has been observed that oxygen can themselves.
#
diffuse through the material during oxidation to In order to lower the amount of charge that is
stabilize and reduce the film leakage. Stability and absorbed by the insulator between metals, materials
leakage issues need to be addressed before implement- research has focused on developing lower dielectric
ing Ta O in trench capacitors. Studies of HfO and constant insulators for BEOL. Typical insulator ma-
ZrO are # &only now coming up to speed. Early studies
# terials are deposited oxides; for BEOL applications,
#
indicate that they may be compatible as a gate silane oxides—deposited via plasma-enhanced chemi-
dielectric as these materials have been reported to cal vapor deposition (PECVD)—are the most com-
show stability with respect to silicon surfaces; the next mon. Table 3 is a list of the dielectrics that are being
logical step is to determine whether these materials looked into as a replacement to the conventional
could be used as node dielectrics for DRAM capaci- silane oxide.
tors. Issues such as possible reaction with silicon,
leakage, and electrode material compatibility need to
be addressed.
(a) Fluorinated oxides. One method of lowering the
(ii) TiO . Unlike Ta O , TiO is very robust and,
#
more importantly, tends# to
& be stable
# with respect to
dielectric constant of deposited oxides is to in-
corporate fluorine into them. By adding fluorine to
silicon at high temperatures. This stability with silicon
deposited oxides, a decrease of 10–20% in dielectric
is its main attraction as a dielectric in trench-based
constant has been achieved (ε " 3.2–3.5). The reduc-
DRAMs. At higher temperatures, TiO can exist as
one or both of the following phases: (i)# anastase (an
tion in dielectric constant is due primarily to the re-
duction in hydroxyl content of the silane oxide.
orthorhombic structure) and (ii) rutile (a tetragonal
There are some reliability issues regarding the use of
structure). Studies indicate that TiO in the anastase
phase exhibits a dielectric constant of# " 76. If TiO is
fluorinated oxides:
formed in the rutile structure, the dielectric constant# is
(i) Moisture absorption leading to fluorine desorp-
tion and enhanced hydroxyl absorption.
" 86 (as measured parallel along the optic axis) and
(ii) Fluorine incorporation into metals. Fluorine
" 180 (as measured perpendicular to the optic axis).
interaction with metals has been commonly observed
The principal problems with TiO are leakage through
thin films and the susceptibility of#O diffusion through
and is believed to be a primary source of metal
the film. The leakage is thought to arise# from oxygen-
corrosion. Moreover, fluorine is known to be a fast
diffuser in aluminum metallurgy. A pile-up of metal at
deficient formation of TiO , as these phases are known
#
to be conductive. The best reported leakage is of the
the metal–insulator interface may weaken the ad-
hesion between thin films and lead to metal blistering.
order of 100 times greater than that of Si N or SiO at
an equivalent thickness. Oxygen penetration $ % is# a
Prevention of fluorine desorption from silane through
surface treatments or the addition of barrier materials
concern if one tries to maintain the high dielectric
has been extensively studied.
capacitance—formation of an underlying SiO , for
example, will severely affect the overall capacitance.#
(iii) Alumina (Al O ). This is perhaps the most
promising metal oxide # for
$ use as a dielectric in trench (b) Hydrogen silsequioxane (HSQ). A second oxide
capacitors. Alumina has a dielectric constant of " 10 that has been actively studied is HSQ. This oxide is
and exhibits high thermal stability. Moreover, alumina reported to have a dielectric constant of " 3.0 and is
appears to be stable with respect to silicon at high found to be less dense than the silane oxides. HSQ is
processing temperatures, which is a definite advantage deposited much like a resist; thus, it is often referred
for use in trench capacitors. Studies in the development to as a ‘‘spin-on’’ or ‘‘flowable’’ oxide. As the oxide
of Al O as a replacement for gate dielectrics show is flowable, it requires a cure at temperatures of
highly# encouraging
$ results of low dielectric leakage " 400 mC to increase its thermal and mechanical in-
without sacrificing its high dielectric constant. tegrity. The primary concern with HSQ is its propen-
sity to absorb moisture, and then release the moisture
during the metal deposition process. The primary
4.2 Interconnect Insulation
source of moisture is from the resist processing dur-
As metal wiring spacings decrease (more commonly ing lithography. Moisture absorption into metals
referred to as ‘‘pitch’’), interaction between metal inevitably causes high resistances (e.g., contact resist-

7
DRAMs

Figure 4
Top-down TEM micrographs of (A) 0.25 µm cells and (B) 0.14 µm cells taken at the same magnification.

ance) and can drastically degrade chip yield. Surface to metal deposition have been shown to be effective
treatments (e.g., using NH plasmas) of HSQ prior in eliminating moisture absorption.
$
8

Table 2
Dielectric constants of metal oxide capacitors.
Usable for trench
Capacitor ε capacitors?
Perovskite, 400–600
titanantes (e.g.,
SrTiO , BaTiO )
$ $
Lead-based 400–1000
perovskites (e.g.,
PbZrTiO ,
PbLaZrTiO$ )
$
TiO (anatase) 76
# Lee et al. 1999a
TiO (rutile) 86 (parallel to optic
# axis), 186
(perpendicular to
optic axis)
Ta O , Al O , 25 (Ta O , ZrO ),
# & , ZrO
HfO # $ 10 #(Al& O ), #
# # 30 (HfO# $)
# Kukli et al. 1997,
(c) Amorphous carbon. A newer form of insulation—
an organic polymer that is carbon based—has been
considered as a replacement for silane oxides and low
K oxides. One material that is being actively explored
by a number of semiconductor manufacturers is a
material developed by Dow Corning that has the
trade name of SiLK. The dielectric constant of these
organic materials has been reported to be approxi-
mately 2–2.5. Hence, use of SiLK represents a much
larger step in reducing parasitic insulator charging
from modern silane oxides. However, the first concern
of the semiconductor industry with implementing
SiLK lies in its mechanical stability in common BEOL
processes such as ‘‘dual damascene’’ with aluminum
and\or copper metallurgies. (Dual damascene refers
to a BEOL process whereby (i) a via and metal line
are lithographically patterned and etched into an insu-
lator, (ii) the via and line are filled in one step, and
(iii) the metal is polished by a chemical–mechanical
polishing (CMP) process.) Since the structural integ-
rity of the organic insulator is usually less than that
of the oxides, the SiLK insulator is much more prone
to surface and mechanical damage. A second concern
is the interaction of the SiLK layers after thermal cycl-
ing. Owing to its inherent softness, thermal expan-
sion of SiLK is reported to be " 5 times that of
oxides. Shear strains between SiLK and metals may
lead to contact and metal wire delamination.
4.3 Resistance Issues
Propagation delay of electrical signals is proportional
to a RC time delay constant, where R is the resistance
DRAMs
Reference
Not possible Kingon et al. 1996,
Jones et al. 1984,
Bornand et al. 2000,
Kotecki 1997
Not possible Kingon et al. 1996,
Jones et al. 1984,
Bornand et al. 2000,
Kotecki 1997
Possible Fukuda et al. 1999,
Possible Fukuda et al. 1999,
Lee et al. 1999a
Possible Oehrlein et al. 1984,
Lee et al. 1999b,
Ma et al. 1999,
Manchanda et al. 1998
of the conductor allowing signal propagation and C is
the parasitic capacitance that surrounds the conduc-
tor. As the minimum feature sizes decrease, the RC
time delay naturally increases. In the section above, we
have focused on ‘‘newer’’ insulators that will help in
reducing parasitic capacitance loss surrounding con-
ductive materials. In this section, the focus is on the
resistances of conductive materials and a glimpse is
provided into the materials that may be required in
future memory technologies.
In DRAM and eDRAM, the three main areas
where resistances can affect the performance of the
chip are (i) resistance of wordlines, (ii) resistance of
bitlines and other metal levels, and (iii) resistance of
the material used to charge the capacitors.
(a) Wordline and diffusion resistances. In a typical
DRAM or eDRAM array, wordlines can often run
to several hundreds of micrometers in length. There-
fore, significant voltage drops can occur if doped poly-
silicon is used as the principal wordline material.
(Typical sheet resistances of highly doped polysilicon
for 0.2 µm ground rules are approximately 300–400 Ω
sq−".) One can circumvent the resistance of poly-
silicon wordlines by ‘‘stitching’’ or ‘‘shunting’’ the
wordlines to low-resistance metal wires. ‘‘Stitching’’
is a design procedure whereby a metal level residing
above the wordline (usually the second level of metal)
is used to help transfer the signal along a wordline.
In order to accomplish this, one must design contacts
from the metal wire to land on the polysilicon word-
line. This procedure, however, adds length to the
9
DRAMs

Table 3 in silicon consumption with NiSi, coupled with its

Dielectric constants of BEOL insulators. ability to maintain comparable sheet resistance, will
Interconnect insulation ε allow shallower FET source and drain diffusions in
future logic generations. Shallower junctions produce
Silane oxide 4.0 lower junction capacitances of source and drain
Fluorinated oxide 3.2–3.6 diffusions, thereby increasing transistor current
(Kim et al. 1998, drive—this becomes especially important as voltage
Gomi et al. 1999) supplies are reduced.
HSQ (Gomi et al. 1999, 3.0–3.5
Meynen et al. 1998)
Amorphous carbon based 2.0–2.5 (b) Resistance of metal wiring. One of the largest re-
(e.g., SiLK) (Thiel 1999, sistance components of the total chip resistance is the
Waeterloos et al. 1999) BEOL metal wiring. In typical logic and eDRAM
offerings, it is not uncommon to have three to six
BEOL wiring levels—this can amount to several
wordline as one needs to allow for contacts to land
meters of metal wire per chip. Since the cross-
on the wordline. For applications requiring large
sectional areas are decreasing with the introduction
memory, e.g., standalone DRAM, the amount of
of every new logic generation, wiring resistance will
stitching can impose a serious area penalty. In many
only increase if there is no change in the conductor
DRAM chips, a tungsten silicide (WSi )\doped-
polysilicon structure (or polycide) is used #for array
material.
Aluminum metallurgy for BEOL metal wiring has
wordlines. The sheet resistance of WSi is " 25 Ω
sq−" or approximately 100–200 times lower # than that had a long and very successful history in semi-
conductor processing. However, as the 0.18 µm node is
of doped polysilicon.
approached, and especially for future logic genera-
The absence of a polycided wordline in eDRAM
tions, the usefulness of aluminum is being questioned.
technology requires that the wordlines in eDRAM be
A number of companies have turned to copper
stitched more frequently than standalone DRAMs (32
metallurgy as a replacement for aluminum (room
or 64 cells stitch−" for eDRAM vs. 256 cells stitch−" for
temperature resistivity of copper is 1.7 µΩ cm whereas
DRAM). The area penalty in chip size is of the order
that of aluminum is 3 µΩ cm) (Stamper et al. 1998,
of a few percent for eDRAM. For eDRAM designs in
Streetman 1980). The introduction of copper into
which larger memory blocks are present on chip,
silicon semiconductor processing is not trivial. New
wordlines may need to be composed of lower sheet
BEOL integration schemes need to be developed; one
resistance materials such as WSi or other silicides
such as CoSi . # key area is the integration of a barrier film to prevent
#
Use of CoSi has been avoided in DRAMs owing to
copper migration into the surrounding dielectrics and
#
a number of process issues such as: (i) agglomeration
into silicon. Copper is a notoriously fast diffuser
in silicon and is found to cause deep level donor
on doped polysilicon after high-temperature proces-
(0.24 eV) and acceptor traps (0.49 eV) in silicon.
ses, (ii) silicide bridging of diffusions and gate elec-
A more problematic scenario, however, is the ac-
trodes, and (iii) possible reaction of cobalt with
cumulation of copper on crystal defects that can form
dielectrics (Nguyen et al. 1993, 1996). Moreover,
during the course of processing (e.g., dislocations
previous experiences with salicide processing using
formed as a result of ion implantation for well
CoSi in DRAMs (i.e., diffusions and doped poly-
# gate electrodes silicided simultaneously) re-
silicon
isolation). If copper should accumulate on these
crystal defects, these defects become quite conductive
sulted in excessive node junction leakage (Takato et al.
(essentially resistors) causing early junction break-
1999, Xu et al. 1998).
down and destroying any well isolation between
Other studies on silicides have focused on NiSi as a
disparate circuits. A second area requiring study is in
replacement to CoSi in the near future. NiSi forms at
temperatures as low# as " 300 mC and is stable to
CMP of copper, especially for dual damascene proces-
sing. New polishing slurries and polishing pads are
temperatures as high as " 700 mC (Sarcona et al. 1999,
required. Only a handful of companies have qualified
Hu and Harper 1997). The temperature restriction of
copper for the BEOL wiring; most of the major
NiSi suggests that metal reaction with dielectrics will
semiconducting manufacturers will convert from
be limited. Benefits of integrating NiSi include (i)
aluminum to copper in the coming years.
comparable resistivity to CoSi (" 15–20 Ω sq−") and
(ii) no agglomeration behavior# on narrow lines. The
primary advantage of NiSi over CoSi is that less
silicon is consumed in making NiSi than # CoSi . For (c) Resistance of doped polysilicon. For trench-based
every angstrom of nickel deposited, 2.2 AH of NiSi # is DRAM and eDRAM, highly doped silicon (typically
produced. However, for every angstrom of cobalt n type) is used as an electrode to charge the Si N
deposited, 3.5 AH of CoSi is produced. This reduction node. As the cross-sectional area of the capacitor$ %
#
10

Table 4
Projected resistance of trench fill from 0.25 µm node to
0.14 µm node at 25 mC (depth assumed as 6 µm).
Resistance, assuming Resistance assuming
Node 2.5i10#! doping 10#! doping
(µm) concentration (kΩ) concentration (kΩ)
0.25 3.50 9.42
0.20 6.55 17.68
0.18 11.16 30.17
0.14 11.84 31.97
decreases from generation to generation, it is not too
surprising to see resistance increasing as well. If we
assume that the doping level for n-type silicon is
constant from the 0.25 µm generation to the 0.14 µm
generation, the decrease in cross-sectional area alone
will result in a 340% increase in resistance (see Table
4). Moreover, the temperature range in which the
DRAM or eDRAM must operate is extremely wide.
For eDRAM applications, the array must operate at
k40 mC. Since resistivity of n-Si is proportional to
T #/$, an additional 20–25% increase in resistance is
projected to occur from 25 mC to k40 mC.
In addition to the area problems presented by each
new and smaller generation, there are also a number of
processing-related drawbacks to using polysilicon
trench fills. First, there is always the probability that
one may inadvertently fill some trenches with poly-
silicon having low carrier concentrations. For ex-
ample, if the doping level of the trench fill is decreased
by 2.5 times, the resistivity of the polysilicon fill
increases by 2.7 times (see Table 4). If this should
occur, resistances of the trench may approach resist-
ances of " 30 kΩ in the 0.14 µm generation. Second,
oxide interfaces within the trench are extremely prob-
lematic for low-resistance control. It is not uncommon
to see thin oxide residuals lying in the polysilicon fill;
oxide films within the trench often lead to low chip
yield at low operation temperatures.
For the 0.18 µm generation of trench DRAMs the
resistance of the trench fill does not appear to present
a problem at low operating temperatures. It is unclear
whether the resistance of the trench-fill imposes a low-
temperature reliability problem at the 0.14 µm node.
Certainly, beyond the 0.14 µm node, it is envisioned
that lower resistive materials will be explored. Thus,
the use of silicides or thermally robust metals for the
trench fill will most likely be key areas of research in
the future.
5. Conclusions
Arguably, the impact of materials science in semi-
conductor processing has been significant. As future
generations drive towards increased density with lower
supply voltages, maintaining yield and retention of
DRAM and eDRAM chips will be the key challenges.
In order to meet these challenges, especially for trench-
DRAMs
based DRAMs, three key areas of materials research
need to be actively addressed:
$ High capacitor materials to replace Si N as the
node dielectric; $ %
$ low dielectric materials in the BEOL; and
$ integration of low resistive materials such as
copper and silicides.
The success in this business is predicated on con-
tinued research and development of materials.
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