Scribd Logo
Upload

Welcome to Scribd!

  • 8 views

    Saloni Garg (B21AI036) - (Lab 3) Practice Questions

    Uploaded by

    Saloni Garg
    The document contains code for testbenches and designs of basic logic gates including NAND, OR, XOR gates using both dataflow and behavioral modeling styles. Testbenches stimulate the gate designs with different input patterns and monitor the output. Gate designs using dataflow style implement the logic function directly using HDL operators. Behavioral models use if/else conditional statements to model the logic function.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content

    You might also like

    Saloni Garg (B21AI036) - (Lab 3) Practice Questions

    Uploaded by

    Saloni Garg
    8 views11 pages
    The document contains code for testbenches and designs of basic logic gates including NAND, OR, XOR gates using both dataflow and behavioral modeling styles. Testbenches stimulate the gate designs with different input patterns and monitor the output. Gate designs using dataflow style implement the logic function directly using HDL operators. Behavioral models use if/else conditional statements to model the logic function.

    Original Description:

    VHdl codes

    Original Title

    Saloni Garg (B21AI036) - [Lab 3] Practice Questions

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document contains code for testbenches and designs of basic logic gates including NAND, OR, XOR gates using both dataflow and behavioral modeling styles. Testbenches stimulate the gate designs with different input patterns and monitor the output. Gate designs using dataflow style implement the logic function directly using HDL operators. Behavioral models use if/else conditional statements to model the logic function.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    8 views11 pages

    Saloni Garg (B21AI036) - (Lab 3) Practice Questions

    Uploaded by

    Saloni Garg
    The document contains code for testbenches and designs of basic logic gates including NAND, OR, XOR gates using both dataflow and behavioral modeling styles. Testbenches stimulate the gate designs with different input patterns and monitor the output. Gate designs using dataflow style implement the logic function directly using HDL operators. Behavioral models use if/else conditional statements to model the logic function.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 11

    Question 1

    Using dataflow
    Testbench
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity nand_uni_gate_ts IS
    end nand_uni_gate_ts;

    ARCHITECTURE dataflow OF nand_uni_gate_ts IS

    component nand_uni_gate
    PORT(
    a: IN std_logic;
    b:IN std_logic;
    c:IN std_logic;
    y:OUT std_logic);
    END COMPONENT;

    signal a: std_logic:='0';
    signal b: std_logic:='0';
    signal c: std_logic:='0';

    signal y:std_logic;

    BEGIN
    uut:nand_uni_gate PORT MAP(
    a=>a,
    b=>b,
    c=>c);
    stim_proc:process
    begin
    a<='0';
    b<='0';
    c<='0';

    wait for 100 ns;


    a<='0';
    b<='0';
    c<='1';
    wait for 100 ns;
    a<='0';
    b<='1';
    c<='0';

    wait for 100 ns;


    a<='0';
    b<='1';
    c<='1';
    wait for 100 ns;
    a<='1';
    b<='0';
    c<='0';

    wait for 100 ns;


    a<='1';
    b<='0';
    c<='1';
    wait for 100 ns;
    a<='1';
    b<='1';
    c<='0';
    wait for 100 ns;
    a<='1';
    b<='1';
    c<='1';
    wait for 100 ns;

    wait;

    end process;
    end dataflow;

    Design
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity nand_uni_gate is
    Port ( a,b ,c : in std_logic;
    y: out std_logic
    );
    end nand_uni_gate;

    architecture dataflow of nand_uni_gate is


    begin
    y<= (((a nand a)nand c)nand(b nand(c nand c)));

    end dataflow;

    Ep wave

    Question 2
    Or gate (dataflow)
    design
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity nand_uni_gate is
    Port ( a,b : in std_logic;
    y: out std_logic
    );
    end nand_uni_gate;

    architecture dataflow of nand_uni_gate is


    begin
    y<= a or b;
    end dataflow;

    testbench
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity nand_uni_gate_ts IS
    end nand_uni_gate_ts;
    ARCHITECTURE dataflow OF nand_uni_gate_ts IS

    component nand_uni_gate
    PORT(
    a: IN std_logic;
    b:IN std_logic;

    y:OUT std_logic);
    END COMPONENT;

    signal a: std_logic:='0';
    signal b: std_logic:='0';

    signal y:std_logic;

    BEGIN
    uut:nand_uni_gate PORT MAP(
    a=>a,
    b=>b);
    stim_proc:process
    begin
    a<='0';
    b<='0';

    wait for 100 ns;


    a<='0';
    b<='1';
    wait for 100 ns;
    a<='1';
    b<='0';

    wait for 100 ns;


    a<='1';
    b<='1';

    wait for 100 ns;

    wait;

    end process;
    end dataflow;
    epwave

    XOR(dataflow)
    design
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity nand_uni_gate is
    Port ( a,b : in std_logic;
    y: out std_logic
    );
    end nand_uni_gate;

    architecture dataflow of nand_uni_gate is


    begin
    y<= a xor b;
    end dataflow;

    testbench
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity nand_uni_gate_ts IS
    end nand_uni_gate_ts;

    ARCHITECTURE dataflow OF nand_uni_gate_ts IS

    component nand_uni_gate
    PORT(
    a: IN std_logic;
    b:IN std_logic;

    y:OUT std_logic);
    END COMPONENT;

    signal a: std_logic:='0';
    signal b: std_logic:='0';

    signal y:std_logic;

    BEGIN
    uut:nand_uni_gate PORT MAP(
    a=>a,
    b=>b);
    stim_proc:process
    begin
    a<='0';
    b<='0';

    wait for 100 ns;


    a<='0';
    b<='1';
    wait for 100 ns;
    a<='1';
    b<='0';

    wait for 100 ns;


    a<='1';
    b<='1';

    wait for 100 ns;

    wait;

    end process;
    end dataflow;

    epwave
    OR(behavioral)
    design

    library ieee;
    use ieee.std_logic_1164.all;
    entity or_E is
    port(
    a, b: in std_logic;
    c: out std_logic
    );
    end or_e;
    architecture arch of or_e is
    begin
    process(a, b)
    begin
    if a='1' and b='1' then
    c <= '0';
    else
    c <= '1';
    end if;
    end process;
    end arch;

    testbench
    -- Code your testbench here
    library IEEE;
    use IEEE.std_logic_1164.all;

    entity or_ts IS
    end or_ts;

    ARCHITECTURE arch OF or_ts IS

    component or_e
    PORT(
    a: IN std_logic;
    b:IN std_logic;

    y:OUT std_logic);
    END COMPONENT;

    signal a: std_logic:='0';
    signal b: std_logic:='0';

    signal y:std_logic;

    BEGIN
    uut:or_e PORT MAP(
    a=>a,
    b=>b);
    stim_proc:process
    begin
    a<='0';
    b<='0';

    wait for 100 ns;


    a<='0';
    b<='1';
    wait for 100 ns;
    a<='1';
    b<='0';

    wait for 100 ns;


    a<='1';
    b<='1';

    wait for 100 ns;

    wait;

    end process;
    end arch;
    epwave

    XOR(behavioral)
    design

    library ieee;
    use ieee.std_logic_1164.all;
    entity or_E is
    port(
    a, b: in std_logic;
    c: out std_logic
    );
    end or_e;
    architecture arch of or_e is
    begin
    process(a, b)
    begin
    if a='0' and b='0' then
    c <= '0';
    elsif a='1' and b='1' then
    c<='0';
    else
    c <= '1';
    end if;
    end process;
    end arch;

    testbench

    -- Code your testbench here


    library IEEE;
    use IEEE.std_logic_1164.all;

    entity or_ts IS
    end or_ts;
    ARCHITECTURE arch OF or_ts IS

    component or_e
    PORT(
    a: IN std_logic;
    b:IN std_logic;

    y:OUT std_logic);
    END COMPONENT;

    signal a: std_logic:='0';
    signal b: std_logic:='0';

    signal y:std_logic;

    BEGIN
    uut:or_e PORT MAP(
    a=>a,
    b=>b);
    stim_proc:process
    begin
    a<='0';
    b<='0';

    wait for 100 ns;


    a<='0';
    b<='1';
    wait for 100 ns;
    a<='1';
    b<='0';

    wait for 100 ns;


    a<='1';
    b<='1';

    wait for 100 ns;

    wait;

    end process;
    end arch;
    epwave

    You might also like