25g4ch 100g Allpcs Ref Guide v3.2

4 Channel 100G Ethernet Multirate PCS Mapper
with RS-FEC
Reference Guide
Version 3.2 - March 2017
100 Gigabit Ethernet

4x10/25G / 40G / 2x50G / 100G
Base-R PCS Mapper
with Clause 91 Reed-Solomon FEC

(with optional 100GBase-KP4 using
RS(544, 514) support)
Reference Guide
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Contents
1 INTRODUCTION ............................................................................................................................. 7
2 CORE FEATURES OVERVIEW ...................................................................................................... 8
2.1 100GETH PCS LAYER FEATURES .............................................................................................. 8
2.2 10/25/40/50GETH PCS LAYERS FEATURES ............................................................................... 8
2.3 BASE-R (FIRECODE) FEC FEATURES ......................................................................................... 8
2.4 REED-SOLOMON FEC (RS-FEC) FEATURES .............................................................................. 9
2.5 MULTIRATE FEATURES ............................................................................................................... 9
3 100G BASE-R PCS MAPPER CORE BLOCK DIAGRAM ........................................................... 10
4 CORE PINOUT .............................................................................................................................. 11
4.1 CORE SIGNALS ........................................................................................................................ 12
4.2 CORE MEMORY INTERFACE SIGNALS ........................................................................................ 20
4.3 OPTIONAL BASE-R FEC (FEC-74) MEMORY INTERFACE SIGNALS ............................................. 21
5 MODE CONFIGURATION AND CHANNEL/LANE ASSOCIATIONS .......................................... 24
5.1 PCS/ENDEC INTERFACES OVERVIEW ....................................................................................... 24
5.2 MODE CONFIGURATION PINS ................................................................................................... 24
5.3 MODE CONFIGURATION PCS REGISTERS ................................................................................. 26
5.3.1 50G with RS-FEC Specific Settings Requirements .......................................................... 27
5.4 SOFTWARE RESET USAGE ........................................................................................................ 27
6 100GETH PCS ............................................................................................................................... 28
6.1 USE OF BLOCKS ...................................................................................................................... 28
6.2 64B/66B TRANSMISSION CODE................................................................................................ 28
6.2.1 Overview ........................................................................................................................... 28
6.2.2 Block Structure .................................................................................................................. 28
6.2.3 Control Codes ................................................................................................................... 29
6.2.4 Ordered Sets ..................................................................................................................... 29
6.2.5 Valid and Invalid Blocks .................................................................................................... 30
6.2.6 Idle (/I/) .............................................................................................................................. 30
6.2.7 Start (/S/) ........................................................................................................................... 30
6.2.8 Terminate (/T/)................................................................................................................... 31
6.2.9 Ordered_Set (/O/).............................................................................................................. 31
6.2.10 Error (/E/) ....................................................................................................................... 31
6.3 TRANSMIT FUNCTIONS ............................................................................................................. 31
6.3.1 Overview ........................................................................................................................... 31
6.3.2 Scrambler .......................................................................................................................... 31
6.4 RECEIVE FUNCTIONS ............................................................................................................... 32
6.4.1 Overview ........................................................................................................................... 32
6.4.2 Descrambler ...................................................................................................................... 32
7 BLOCK SYNCHRONIZATION ...................................................................................................... 33
8 MULTI-LANE DISTRIBUTION (MLD) ........................................................................................... 34
8.1 TRANSMIT MLD ....................................................................................................................... 34
8.2 MARKER ENCODINGS............................................................................................................... 34
8.2.1 100G Markers.................................................................................................................... 34
8.2.2 40G/50G Markers .............................................................................................................. 35
8.2.3 25G Markers...................................................................................................................... 35
8.3 RECEIVE MLD ......................................................................................................................... 36
9 MARKER COMPENSATION REQUIREMENTS .......................................................................... 37
10 FORWARD ERROR CORRECTION (FEC, CLAUSE 74) OPTION ............................................. 39
10.1 OVERVIEW .............................................................................................................................. 39
10.2 TRANSMIT FEC ENCODER ....................................................................................................... 39
10.3 RECEIVE FEC DECODER ......................................................................................................... 40
11 REED-SOLOMON FEC (RS-FEC) ................................................................................................ 41
11.1 OVERVIEW .............................................................................................................................. 41
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11.2 STATUS AND CONTROL REGISTERS INFORMATION ..................................................................... 42
11.3 CORRECTION BYPASS OPTION ................................................................................................. 42
11.4 ERROR INDICATION BYPASS OPTION ........................................................................................ 42
12 SYSTEM CLOCK DISTRIBUTION................................................................................................ 44
12.1 CLOCK DOMAINS ..................................................................................................................... 44
12.1.1 Asynchronous Design Variant ....................................................................................... 44
12.1.2 Synchronous Design Variant ......................................................................................... 44
12.2 CLOCK FREQUENCIES OVERVIEW ............................................................................................. 44
12.3 CORE SYSTEM CLOCK DISTRIBUTION ....................................................................................... 46
12.3.1 Asynchronous Core Variant .......................................................................................... 46
12.3.2 Synchronous Core Variant ............................................................................................ 46
13 CLOCK DECOUPLING FIFOS AND LOOPBACK ....................................................................... 48
13.1 OVERVIEW .............................................................................................................................. 48
13.2 CGMII LOOPBACK ................................................................................................................... 48
14 CGMII INTERFACE ....................................................................................................................... 49
14.1 OVERVIEW .............................................................................................................................. 49
14.2 TRANSMIT ............................................................................................................................... 50
14.2.1 Frame Transmit Operation ............................................................................................ 50
14.2.2 Frame Transmit with Error ............................................................................................ 52
14.2.3 Start Control Character Alignment ................................................................................ 52
14.3 RECEIVE ................................................................................................................................. 53
14.3.1 Start Control Character Alignment ................................................................................ 53
14.3.2 Link Fault Signaling ....................................................................................................... 53
15 XLGMII INTERFACE ..................................................................................................................... 54
15.1 OVERVIEW .............................................................................................................................. 54
15.2 FRAME TRANSMIT / RECEIVE OPERATION.................................................................................. 55
15.3 FRAME TRANSMIT WITH ERROR ................................................................................................ 56
15.4 FRAME RECEIVE WITH ERROR .................................................................................................. 56
15.5 START CONTROL CHARACTER ALIGNMENT ............................................................................... 56
15.6 LOW POWER IDLE (LPI) TRANSMISSION .................................................................................... 56
15.7 LINK FAULT SIGNALING ............................................................................................................ 56
16 ENERGY EFFICIENT ETHERNET (EEE) ..................................................................................... 58
16.1 OVERVIEW .............................................................................................................................. 58
16.2 LPI SIGNALING WITH XLGMII ................................................................................................... 58
16.3 APPLICATION INTERFACE OVERVIEW ........................................................................................ 58
17 TEST PATTERNS ......................................................................................................................... 60
17.1 TEST PATTERN GENERATOR .................................................................................................... 60
17.2 TEST PATTERN CHECKER ........................................................................................................ 61
18 GEARBOX ..................................................................................................................................... 62
19 SERDES INTERFACE................................................................................................................... 63
19.1.1 Serialization Bit Ordering .............................................................................................. 63
19.1.2 Clock-Enable based Serdes Interface Rate Control ..................................................... 63
20 HOST PROCESSOR INTERFACE ............................................................................................... 65
20.1 OVERVIEW .............................................................................................................................. 65
20.2 REGISTER W RITE .................................................................................................................... 65
20.3 REGISTER READ ...................................................................................................................... 65
21 MEMORY READ/WRITE INTERFACES ....................................................................................... 67
21.1 W RITE INTERFACE ................................................................................................................... 67
21.2 READ INTERFACE .................................................................................................................... 67
21.3 READ/W RITE TO SAME ADDRESS .............................................................................................. 67
22 CORE REGISTERS ....................................................................................................................... 68
22.1 100G PCS REGISTER MAP...................................................................................................... 68
22.1.1 100G PCS Vendor PCS_MODE Register (32784) ....................................................... 76
22.2 10G..50G PCS REGISTER MAP............................................................................................... 77
22.2.1 PCS status 1 Register (1) ............................................................................................. 83
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22.2.2 10..50G PCS Vendor PCS_MODE Register (32784) ................................................... 84
22.3 RS-FEC REGISTERS ............................................................................................................... 86
22.3.1 RS-FEC Control Register .............................................................................................. 89
22.3.2 RS-FEC Status Register ............................................................................................... 91
22.3.3 RS-FEC Lanemapping Register .................................................................................... 92
22.3.4 RS-FEC Vendor Control Register ................................................................................. 92
22.3.5 RS-FEC Vendor Info 1 Register .................................................................................... 94
22.3.6 RS-FEC Vendor Info 2 Register .................................................................................... 95
22.4 100G PCS STANDARD VIRTUAL LANE MARKER VALUES ........................................................... 95
23 REFERENCES .............................................................................................................................. 96
24 DOCUMENT HISTORY ................................................................................................................. 96
25 CONTACT ..................................................................................................................................... 98
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List of Figures
Figure 1: 100G PCS Mapper Transmit Block Diagram ................................................................................ 10

Figure 2: 100G PCS Mapper Receive Block Diagram ................................................................................. 10
Figure 3: Core Pinout Overview....................................................................................................................... 11
Figure 4: 64B/66B Block Formats.................................................................................................................... 29
Figure 5: Scrambler ........................................................................................................................................... 32
Figure 6: Descrambler ....................................................................................................................................... 32
Figure 7: Block Lock State Machine................................................................................................................ 33
Figure 8: Alignment Marker Format ................................................................................................................ 34
Figure 9: Transmit FEC Functions Overview ................................................................................................. 39
Figure 10: Receive FEC Functions Overview ................................................................................................ 40
Figure 11: RS-FEC PCS Integration Conceptual Overview ........................................................................ 41
Figure 12: Asynchronous Core variant Clock Distribution ........................................................................... 46
Figure 13: Synchronous Core Variant Clock Distribution ............................................................................ 47
Figure 14: Clock Decoupling FIFOs Overview .............................................................................................. 48
Figure 15: Frame Transmit ............................................................................................................................... 51
Figure 16: Frame Transmit with Error ............................................................................................................. 52
Figure 17: Frame Transmit ............................................................................................................................... 56
Figure 18: Low Power Idle Indication on XLGMII .......................................................................................... 58
Figure 19: Test Pattern Generation / Check Overview ................................................................................ 60
Figure 20: Serdes Serialization/De-serialization Overview.......................................................................... 63
Figure 21: Serdes Interface Clock-Enable Timing Example........................................................................ 64
Figure 22: Register Write .................................................................................................................................. 65
Figure 23: Register Read .................................................................................................................................. 66
Figure 24: Memory Write Interface .................................................................................................................. 67
Figure 25: Memory Read Interface.................................................................................................................. 67
List of Tables
Table 1: Signal Description............................................................................................................................... 12

Table 2: Memory Interfaces Signal Description ............................................................................................. 20
Table 3: FEC74 (Optional) Memory Interfaces Signal Description ............................................................. 21
Table 4: Core Interface Definitions .................................................................................................................. 24
Table 5: Mode Control Pins Overview ............................................................................................................ 24
Table 6: Mode Control PCS Registers ............................................................................................................ 26
Table 7: Control Codes ..................................................................................................................................... 30
Table 8: 100G Virtual Lanes Requirement ..................................................................................................... 34
Table 9: 100GBASE-R Alignment Marker Encodings .................................................................................. 35
Table 12: PCS and MAC Marker Distance Settings ..................................................................................... 37
Table 13: System System Clock Frequencies ............................................................................................... 44
Table 14: Serdes Interface Clock Frequencies ............................................................................................. 45
Table 15: Lane Association .............................................................................................................................. 49
Table 16: TXD / TXC Encoding ....................................................................................................................... 50
Table 17: Link Fault Sequences ...................................................................................................................... 53
Table 18: Lane Association .............................................................................................................................. 54
Table 19: TXD / TXC Encoding ....................................................................................................................... 54
Table 20: 40Geth and 50Geth XLGMII Link Fault Sequences (Clause 82) .............................................. 57
Table 21: 10Geth and 25Geth XGMII Link Fault Sequences (Clause 49) ................................................ 57
Table 22: Control Signals Description/Coding ............................................................................................... 58
Table 23: Register Map ..................................................................................................................................... 68
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Table 24: PCS Vendor PCS_MODE Register ............................................................................................... 76
Table 25: Register Map ..................................................................................................................................... 77
Table 26: PCS status 1 Register ..................................................................................................................... 83
Table 27: 10..50G PCS Vendor PCS_MODE Register ................................................................................ 84
Table 28: RS-FEC Register Map ..................................................................................................................... 86
Table 29: RS-FEC Control Register ................................................................................................................ 89
Table 30: RS-FEC Status Register ................................................................................................................. 91
Table 31: RS-FEC Lanemapping Register..................................................................................................... 92
Table 32: RS-FEC Vendor Control Register .................................................................................................. 92
Table 33: RS-FEC Vendor Info 1 Register ..................................................................................................... 94
Table 34: RS-FEC Vendor Info 2 Register ..................................................................................................... 95
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1 Introduction
The 4 Channel 100 Gigabit Ethernet Multirate PCS Mapper allows flexible use of a 4-lane 100G PMA
Interface for 4x10G, 4x25G, 2x50G, 1x40G and 1x100G 100G applications.
The PCS Mapper encodes the different channels into 4 Serdes lanes operating at up to 25.78Gbps or
2 Serdes at up to 53.125Gbps each, performing the necessary rate multiplexing, lane distribution,
synchronization and lane reordering.
It includes a multiplexed 802.3bj Clause 91 Reed-Solomon Forward Error Correction (RS-FEC)
function for use by different channels at various speeds.
The Core implements four independent 10/25/40/50G capable PCS channels for direct connection to
multi-rate MACs and one 100Geth MAC interface.
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2 Core Features Overview
2.1 100Geth PCS Layer Features

 Complete 100G Base-R PCS solution compliant with IEEE 802.3ba Clause 82
Specification
 Can be used together with any 100 Gigabit Ethernet PHY application or in integrated 100
Gigabit Ethernet controller devices
 4 x parallel SerDes line interface with 25.78Gbps
 Multi-Lane Distribution (MLD) for 100G Ethernet over 4 Lanes (CAUI-4)
 Periodic Alignment Marker insertion / striping on transmit / receive, respectively
 Implements 100 Gigabit Ethernet data Scrambler on the Core transmit path, and data De-
Scrambler on the Core receive path
 64b/66b Encoder / Decoder performing 66-bit block synchronization, 64b/66b receive
path decoding, 64b/66b transmit path encoding, and 66b/64b transmit path conversion for
block overhead bits
 Programmable loopback on the Core CGMII interface available for application test
 Implements Bit Error Rate (BER) monitoring, with high error rate indication, providing
constant line quality monitoring
 Can be seamlessly connected to the MorethanIP 100 Gigabit Ethernet MAC to build
single chip 100 Gigabit Ethernet controller
 16-bit host interface to access to the internal registers of the PCS
2.2 10/25/40/50Geth PCS Layers Features

 Configurable Base-R PCS compliant with IEEE 802.3ba Clause 49 and Clause 82 for 10
and 40G operation respectively and compliant with IEEE 802.3by Draft 1.1
 Independent 64bit XLGMII MAC interfaces per channel.
 Multi-Lane Distribution (MLD) for 40G/50G Ethernet over 4 or 2 Lanes (XLAUI, RXLAUI)
 Codeword Marker (CWM) insertion/removal for 25G/50G when used in combination with
a RS-FEC datapath
 Periodic Alignment/Codeword Marker insertion / striping on transmit / receive,
respectively
 Implements 100 Gigabit Ethernet data Scrambler on the Core transmit path, and data De-
Scrambler on the Core receive path
 64b/66b Encoder / Decoder performing 66-bit block synchronization, 64b/66b receive
path decoding, 64b/66b transmit path encoding, and 66b/64b transmit path conversion for
block overhead bits
 Programmable loopback on the XLGMII interface available for application test
 16-bit host interface to access to the internal registers of each PCS
2.3 Base-R (Firecode) FEC Features

 Optional Forward Error Correction (FEC) according to Clause 74 of IEEE 802.3
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 Usable for Channels 0..3 only (i.e. not used for 100G PCS)
 Support for Error Indication to PCS when uncorrectable errors are detected
2.4 Reed-Solomon FEC (RS-FEC) Features

 IEEE802.3bj Clause 91 RS-FEC supporting 100GBase-KR4 and 100GBase-CR4 PHYs
using RS(528, 514) codewords and 100GBase-KP4 using RS(544, 514)
 Usable on Channels 0..3 with flexible speeds of 10/G25G/40G/50G as well as for 100G
PCS.
 Support for Error Indication to PCS when uncorrectable errors are detected
 Separate register access interface
2.5 Multirate Features

 Up to 4 channels independently usable for 10Geth or 25Geth Ethernet single-lane
applications.
 Up to 2 50Geth channels using two 25Gbps lanes or a single 50Gbps lane
 One 100Geth Channel over four 25Gbps lanes or over two 50Gbps lanes
 Multi-Link Gearbox over 100G PMA offering up to 10x 10G or 2x 40G + 2x 10G PCS links.
 Support for Base-R Firecode FEC (802.3 Clause 74) per channel for 10Geth, 25Geth,
40Geth and 50Geth applications
 Support for Reed-Solomon FEC (528,514) per channel (802.3bj Clause 91) for 25Geth,
50Geth and 100Geth applications
 Support for Reed-Solomon FEC (544,514) per channel for 50Geth and 100Geth
applications
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3 100G Base-R PCS Mapper Core Block Diagram
4-Channel PCS Mapper - TX
100G PCS TX 20 VLs
CGMII PCS
MLD 20 VLs
Encode
TX
64/66
SERDES TX
10x 66b 4x 10.3/25.78G
Transcode RSFEC
Interface
GB
Channelized
RS-FEC TX
GB
25/50/100G
XLGMII 0 Lane
4x 66b 4x 66b
10/25/40/50G CH0 Transcode Distribution
CH0 4x 66b
PCS GB
4x 66b FEC74
XLGMII 1 (4x) GB
66b Marker
10/25G 1:4 Transcode
CH1 CH1 Insert 66b
PCS 66b
XLGMII 2 4x 66b FEC74

10/25/50G 4x 66b Transcode (4x)
CH2 CH2 4x 66b
PCS 4x 66b
XLGMII 3
10/25G 66b Marker
CH3 CH3
1:4 Transcode
PCS Insert 66b
66b
Figure 1: 100G PCS Mapper Transmit Block Diagram
4-Channel PCS Mapper - RX
100G PCS RX 20 VLs
CGMII PCS
MLD 20 VLs
Decode
RX
64/66
SERDES RX
4x 10.3/25.78G
Transcode RSFEC
Interface FEC74
Sync Demux
(2x)
Channelized
RS-FEC RX FEC74
Sync Demux
25/50/100G (2x)
Deskew
XLGMII 0 4x 66b 4x 66b and
10/25/40/50G Transcode FEC74
CH0 CH0 4x 66b Lane Re-order Sync Demux
PCS (2x)
4x 66b
FEC74
XLGMII 1 Sync Demux
66b Marker (2x)
10/25G 4:1 Transcode
CH1 CH1 66b Remove 66b
PCS lane1
XLGMII 2
4x 66b
10/25/50G Transcode
CH2 CH2 4x 66b 4x 66b lane2,3
PCS
XLGMII 3 Marker
66b 4:1 Transcode
10/25G Remove
CH3 CH3 66b
PCS 66b lane3
Figure 2: 100G PCS Mapper Receive Block Diagram
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4 Core Pinout
cgmii_txd(191:0)
Transmit
cgmii_txc(23:0)
Interface
cgmii_txclk_ena reset_sd0_tx_clk
CGMII sd0_ tx_clk
cgmii_rxd(191:0)
Receive sd0_tx(n:0)
Interface cgmii_rxc(23:0) . .
. . PMA Transmit
cgmii_rxclk_ena . .
reset_sd3_tx_clk Interface
xlgmiiN_txclk_ena
sd3_ tx_clk
xlgmiiN_txd(63:0)
xlgmiiN_txc(7:0) sd3_tx(n:0)
10..50G PCS
xlgmiiN_rxclk_ena sd_tx_clk_ena(3:0)
Channels
0..3 xlgmiiN_rxd(63:0)
reset_sd0_rx_clk
xlgmiiN_rxc(7:0) sd0_rx_clk
xlgmiiN_rxt0_next sd0_rx(n:0)
. .
Link Status . .
xl_link_status(3:0) . .
Channels PMA Receive
xl_hi_ber(3:0) reset_sd3_rx_clk
0..3 Interface
sd3_rx_clk
regN_rden
sd3_rx(n:0)
regN_wren
sd_rx_clk_ena(3:0)
PCS Register regN_addr(15:0)
Access signal_det(3:0)
regN_din(15:0)
Channels 0..3
regN_dout(15:0)
align_lock
regN_busy
block_lock(19:0)
PCS Status
reset_ref_clk hi_ber
Global ref_clk link_status
Signals reset_reg_clk
reg_clk rsfec_aligned(3:0)
RS-FEC Status
amps_lock(3:0)
100G
reg_rden PMA Interface
reg_wren
PCS/PMA sd_n2(3:0) Width Config.
100G PCS
Register reg_addr(15:0) Mapper
Access reg_din(15:0) fec91_ena_in(3:0)
reg_dout(15:0) kp_mode_in(3:0)
reg_busy fec91_1lane_in{0,2}
rxlaui_ena_in{0,2} Configuration
reg91_rden pcs100_ena_in
reg91_wren mode40_ena_in
RS-FEC
Register reg91_addr(7:0) pacer_10g(3:0)
Access fast_1lane_mode(3:0)
reg91_din(15:0)
scrambler_bypass_100g
reg91_dout(15:0)
descr_bypass_100g
reg91_busy
lpi_tick_tx(3:0) ber_timer_short PCS

ber_timer_done100 Test Signals
lpi_tick_rx(3:0)
ber_timer_done(3:0)
Optional energy_detect(3:0)
EEE Client tx_lpi_mode(7:0) fec_ena(3:0)
Controls; fec_err_ena(3:0)
tx_lpi_state(11:0) Optional
Channels
0..3 rx_lpi_active(3:0) fec_locked(7:0) Clause 74
FEC Controls
rx_lpi_mode(3:0) fec_cerr(7:0)
rx_lpi_state(11:0) fec_ncerr(7:0)
pcs0_lane_active(3:0)
pcs2_lane_active(1:0)
Active
tx_lane_thresh0[3:0]
Configuration
indicators tx_lane_thresh1[3:0]
Figure 3: Core Pinout Overview
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4.1 Core Signals

Table 1: Signal Description
Signal Name Mode Description
Global Signals
reset_ref_clk In Active high reset signal for ref_clk clock domain.
reset_sd0_tx_clk
Active high reset signal for sd0_tx_clk ... sd3_tx_clk clock domains.
reset_sd1_tx_clk
In
reset_sd2_tx_clk
Note: do not exist when the synchronous Core variant is used.
reset_sd3_tx_clk
reset_sd0_rx_clk
Active high reset signals for sd0_rx_clk ... sd3_rx_clk clock domains.
reset_sd1_rx_clk
In
reset_sd2_rx_clk
reset_sd3_rx_clk
reset_reg_clk In Active high reset signal for reg_clk clock domain (register interface).
reg_clk In Register Interface Reference Clock.
ref_clk In PCS Reference Clock. See 12 page 44 for clock frequency requirements.
CGMII (100G PCS)

(All synchronous to ref_clk)
CGMII Transmit Clock Enable Signal (sampling of cgmii_txd/c).

cgmii_txclk_ena Out
Synchronous to ref_clk
CGMII Receive Clock Enable Signal (validity of cgmii_rxd/c).
cgmii_rxclk_ena Out
CGMII Transmit Data from MAC representing 24 octet lanes. Bit 0 is LSB.
cgmii_txd(191:0) In Synchronous to ref_clk and valid when cgmii_txclk_ena is set to ‘1’ by the
Core.
CGMII Transmit Control. Indicates data or control characters for each of the 24
cgmii_txc(23:0) In data lanes of cgmii_txd. Bit 0 is LSB. Synchronous to ref_clk and valid when
cgmii_txclk_ena is set to ‘1’ by the Core.
CGMII Receive Data. cgmii_rxd is a bundle of 192 data signals organized into
24 octet lanes (cgmii_rxd(7:0), cgmii_rxd(15:8), cgmii_rxd(23:16),
cgmii_rxd(191:0) Out
...). Each lane is associated with a cgmii_rxc signal. Synchronous to ref_clk
and valid when cgmii_rxclk_ena is set to ‘1’ by the Core.
CGMII Receive Control. cgmii_rxc indicates that the CGMII data bus is
presenting either decoded data or control characters. The cgmii_rxc signal for
a lane is de-asserted (0) when a data octet is being received on the
corresponding lane, and asserted when a control character is being received. In
cgmii_rxc(23:0) Out the absence of errors, the cgmii_rxc signals are de-asserted by the PHY for
each octet of the preamble (except the first octet that is replaced with a Start
control character) and remain de-asserted while all octets to be received are
presented on the data bus lanes. Bit 0 is LSB. Synchronous to ref_clk and valid
when cgmii_rxclk_ena is set to ‘1’ by the Core.
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Channel 0 to 3 PCS XLGMII (N=0..3)

(All synchronous to ref_clk)
xlgmiiN_txd(63:0) In XLGMII Transmit Data from MAC representing 8 octet lanes. Bit 0 is LSB.
xlgmiiN_txc(7:0) In XLGMII Transmit Control. Indicates data or control characters for each of the 8
data lanes of xlgmii_txd. Bit 0 is LSB.
XLGMII Transmit Clock Enable.

xlgmiiN_txclk_ena Out
Note: xlgmii_txd/txc are sampled only when xlgmii_txclk_ena=1.
xlgmiiN_rxd(63:0) Out XLGMII Receive Data to MAC representing 8 octet lanes. Bit 0 is LSB.
xlgmiiN_rxc(7:0) Out XLGMII Receive Control. Indicates data or control characters for each of the 8
data lanes of xlgmii_rxd. Bit 0 is LSB.
xlgmiiN_rxt0_next Out Advance indication if TERM block without data is next after current (directly from
decoder classification block type 0x87, T0)
XGMII Receive Clock Enable.

xlgmiiN_rxclk_ena Out
Note: xlgmii_rxd/rxc must be sampled only when xlgmii_rxclk_ena=1.
Channel 0 to 3 PCS Receive Status
Per channel link status. One bit per channel.

xl_link_status(3:0) Out Asserts (1) when the link is established and in its normal operational state.
Note: this signal is e.g. usable by Clause 73 autonegotiation function.
Per channel high bit error indication. One bit per channel.
Asserts (1) when too many invalid sync header errors were found (depending on
xl_hi_ber(3:0) Out mode). When hi-ber is asserted for a channel the PCS produces local-fault
sequences to the MAC and the corresponding xl_link_status bit deasserts.
Is 0 during normal operation.
Channel 0 to 3 PCS Energy-Efficient Ethernet Client Interfaces

(Optional)
A timer tick (separate per datapath), to assert for one ref_clk cycle in average
every 100ns. Ten ticks represent the duration of 1µs.
lpi_tick_tx(3:0) It is used as the time-base for all LPI statemachine timers. It causes a maximum
In
lpi_tick_rx(3:0) uncertainty of 100ns.
Note: for fast-wake only support these inputs are unused and can be wired to 0.
1-bit per channel.
A variable reflecting state of the LPI transmit function as described by the LPI
transmit state diagram. When tx_mode is set to QUIET the sublayer may go into a
tx_lpi_mode(4*2-1:0) Out
low power. Refer to 16.3 for the coding values.
2-bit per channel.
Informal variable reflecting state of the LPI SM as described by the LPI transmit
tx_lpi_state(4*3-1:0) Out state diagram. Refer to 16.3 for the coding values.
3-bit per channel.
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A variable reflecting state of the LPI receive function as described by the LPI
receive state diagram.The parameter has one of two values: DATA (0) and QUIET
rx_lpi_mode(3:0) Out
(1). Refer to 16.3 for the coding values.
1-bit per channel.
Informal variable reflecting state of the LPI SM as described by the LPI transmit
rx_lpi_state(4*3-1:0) Out state diagram. Refer to 16.3 for the coding values.
3-bit per channel.
A Boolean variable that is set to true (1) when the receiver is in a low power state
rx_lpi_active(3:0) Out and set to false (0) when it is in an active state and capable of receiving data.
1-bit per channel.
A parameter generated by the PMA/PMD sublayer to reflect the state of the
received signal per lane. In the PMD this has the same definition as parameter
signal_detect and is passed through without modification by the PMA (and FEC).
The energy_detect is expected to assert when the ALERT pattern is received (i.e.
energy_detect(3:0) In the remote transmitter is in the ALERT state).
If the PMA has no such separate indication it may be wired together with
signal_detect.
1-bit per channel.
Asynchronous input (synchronized to ref_clk).
PMA Transmit Interface

sd0_tx_clk
PMA Transmit Clocks. Transmit data is produced on the clock rising edge.
sd1_tx_clk
In
sd2_tx_clk
sd3_tx_clk
sd0_tx(39:0) PMA Transmit Data. 4 x 40-Bit line interface.
sd1_tx(39:0) The configuration signal sd_n2(x) defines the active interface width to be 20bits
Out
sd2_tx(39:0) (sd_n2=1) or 40bits (sd_n2=0) per lane. For 20bit only bits 19:0 are relevant.
sd3_tx(39:0) See also 12.2 page 44
PMA Transmit Clock enable signals for sd0_tx_clk ... sd3_tx_clk clock
domains. Should be connected to always high for full data rate.
sd_tx_clk_ena(3:0) In
Must be wired to all 1 if not used.
Note: Exist when the synchronous Core variant is used.
PMA Receive Interface

sd0_rx_clk PMA Receive Reference Clocks. All receive data is sampled on the clock rising
sd1_rx_clk edge.
In
sd2_rx_clk
sd3_rx_clk Note: Do not exist when the synchronous Core variant is used.
sd0_rx(39:0) PMA Receive Data. 4 x 40-Bit line interface.
sd1_rx(39:0) The configuration signal sd_n2(x) defines the active interface width to be 20bits
In
sd2_rx(39:0) (sd_n2=1) or 40bits (sd_n2=0) per lane. For 20bit only bits 19:0 are relevant.
sd3_rx(39:0) See also 12.2 page 44
PMA Receive Clock enable signals for sd0_rx_clk ... sd3_rx_clk clock
domains. Should be always asserted high for full data rate.
sd_rx_clk_ena(3:0) In
Must be wired to all 1 if not used.
Note: Exist when the synchronous Core variant is used.
PMA Signal Detect indication for sd0_rx … sd3_rx lanes.

signal_det(3:0) In
Must be all 1 for normal operation.
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100G PCS Receive Status

Alignment Marker Lock indication. When asserted (1) the alignment marker lock
state machines could successfully lock onto detection of alignment markers on all
align_lock Out virtual lanes. The signal stays asserted as long as alignment marker lock is
maintained.
Synchronous to ref_clk.
High Bit Error Rate indication. If asserted, at least 97 invalid synchronization

headers have been found in a 500µs measurement period for 100GBASE-R
indicating a high bit error rate. As long as hi_ber stays asserted, local fault is
signaled on CGMII.
hi_ber
Out hi_ber deasserts again, only if less than 97 invalid synchronization headers
have been detected within the same measurement period.
Refer to IEEE 802.3ba Clause 82.2.18.3. Its purpose is to help monitor the quality
of the link.
Final link status indication for 100G PCS.

This is the logical result of align_lock=1 and hi_ber=0. When asserted (1) it
link_status Out indicates the link is in its normal operational state. The signal represents the link-
status indication that e.g. can be used by Clause 73 Backplane Autonegotiation.
Block synchronization indication for each (virtual) lane. When asserted (1) the
block synchronization state machines could successfully lock onto 66-bit block
boundaries. The signals stay asserted as long as block lock is maintained.
All 20 bits are relevant when the 100G PCS operates in normal mode indicating
lock per Virtual Lane. They are not relevant in RS-FEC mode.
When the 100G PCS is not used the following bits per serdes lane are valid:
block_lock(19:0) Out
block_lock(1:0) - Serdes lane 0 (bit 1 relevant only when 50G is active).
RS-FEC Status
Per serdes lane RS-FEC codeword alignment status.
One bit per Serdes lane. The signal asserts if the codeword alignment markers
amps_lock(3:0) Out
were detected on a lane (before RSFEC deskew and lane re-ordering).
It is the same indication available in the RS-FEC Status register.
RS-FEC alignment status for every channel.
Bit 0 indicates alignment for Channel 0 with 25G/50G as well as 100G PCS.
rsfec_aligned(3:0) Out Bit 1 indicates alignment for Channel 1 with 25G
Bit 2 indicates alignment for Channel 2 with 25G/50G
Bit 3 indicates alignment for Channel 3 with 25G
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Configuration
Per Serdes lane: Number bits used at the line interfaces: When set to 1 the
interface lower 20 bits are used, when set to 0 the full 40 bits of the interface are
used.
sd_n2(3:0) In A serdes interface operating at 10.3Gbps should use 20 bits (sd_n2=1).
A serdes interface operating at 25.78Gbps should use 40bits (sd_n2=0).
Asynchronous input synchronized internally to the respective serdes domain.
See also 12.2 page 44 for PMA interface usage.
Enable control for RS-FEC (Clause 91) datapath per serdes lane. When asserted
(1) the Clause 91 RS-FEC datapath is active for the lane. If deasserted (0) the
datapath uses normal 66b coding and can optionally use FEC74.
If the current enabled channel occupiers multiple serdes lanes, then for all of them
fec91_ena_in must be set. (for details, see 5 page 24)
fec91_ena_in(3:0) In Note: this input is internally OR’ed with fec91_ena register settings (see Table 29
page 89). So the customer has an option how to enable the RS FEC – either
through this pin or through register settings. If the register settings are preferable,
then the pin should be wired to all zeros. The register default settings are also all
zeros.
Asynchronous input synchronized internally to ref_clk.
Enable control for RS-FEC (Clause 91) datapath per serdes lane. When asserted
(1) the RS (544, 514) codewords are used, otherwise the RS (528, 514)
codewords . The setting is relevant, only when RS FEC for the same lane is set.
If the current enabled channel occupiers multiple serdes lanes, then for all of them
kp_mode_in must be set (for details, see 5 page 24).
Note: this input is internally OR’ed with kp_mode register settings. (see Table 29
page 89). So the customer has an option how to enable the RS FEC – either
kp_mode_in(3:0) In through this pin or through register settings. If the register settings are preferable,
then the pin should be wired to all zeros. The register default settings are also all
zeros.
Note: This bit is available, only when the synthesis option to enable the
RS (544, 514) support is set. This feature support is a matter of package’s
delivery agreement and requires a different set of source files.
Define for Channel 0 and 2, when using RS-FEC, to operate at 25G-1lane (1) or
fec91_1lane_in0
In 50G-2lane mode (0).
fec91_1lane_in2
Note: Channels 1,3 have no such input as they operate at 25G-1lane only.
Define for Channel 0 and 2 to operate with 2:1 bitmuxing per lane to use 2-lanes
for the 4 VLs instead of 4 lanes. Can be used when RS-FEC is disabled for the
channel. Allows use of 50G over 2-lanes without FEC or with FEC74.
rxlaui_ena_in0
In When bit N is '0' the Channel N operates without lane bitmuxing (1:1). When bit N
rxlaui_ena_in2 is '1' the channel N uses 2:1 bitmuxing allowing it to operate with 50G over 2
lanes.
Note: Channels 1,3 have no such input as they operate at 1lane only.
100G PCS Enable. When set to '1' the 100G PCS is enabled. When set to '0' the
pcs100_ena_in In other channels can be used individually per lane.
Define 40G mode of operation for Channel 0.

When set '1' the Channel 0 PCS is used to operate over all 4 links. Channels 1..3
mode40_ena_in In
are disabled. Has an effect only when pcs100_ena_in=0.
When set '0' all Channels 0..3 are active and can be configured individually.
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Defined for a channel operated in the 10G/25G mode with no RS-FEC enabled.
For other modes, this pin’s value does not have any affect. One bit per channel.
Setting this bit to 1 guaranties that the Mapper does not read in burst from TX
PCS and does not write in burst in the RX PCS (at least one idle cycle between
pacer_10g(3:0) In
read/write). If this bit is set to 0, the read/write pattern from/to the PCS is
determined by TX FIFO/ De-skew FIFO’s level.
Note: The signal is not available in the synchronous Core variant (not relevant).
Per Serdes lane: When asserted(1), the low latency mode for the corresponding
channel serdes interface will be enabled. This mode allows decrease in latency
(by ~40ns) but requires higher reference clock (ref_clk) frequency. If this mode
enabled, the minimum frequency for reference clock (ref_clk) is 626 MHz.
if this pin is set, the sd_n2(x) for the corresponding serdes lane must be set also.
fast_1lane_mode(3:0) In
This setting can be used only for single lane 10G channel, when lower 20 bits of
the serdes interface are used(sd_n2 = 1). In other modes the pin must be always
deasserted.
Note: The signal is not available in the synchronous Core variant (not relevant).
100G Scrambler bypass mode. When set to ‘1’, the transmit data are not
scrambled. The input can be used for debug purpose in the 100g operational
scrambler_bypass_100g In mode. For standard operation in 100G mode this input must be set to 0.
100G Descrambler bypass mode. When set to ‘1’, the receive data are not
descrambled. The input can be used for debug purpose in the 100g operational
descr_bypass_100g In mode. For standard operation in 100G mode this input must be set to ‘0’.
PCS Test Signals

Test/Debug signal for 100G PCS. When asserted sets the hi-ber measurement
timer to 1/100th of its normal value. This allows speedup during simulations or to
ber_timer_short In perform specific testing. Affects the 100G PCS only.
Note: The other PCS layers use the vl_intvl register setting instead.
Must be 0 for normal (compliant) operation.
Test/Debug signal from 100G PCS. A pulse is generated at the beginning of the
BER measure window. This is an informal signal, which is typically left
ber_timer_done100 Out unconnected during normal operation.
Test/Debug signal from Channel 0..3 PCSs. One bit per channel.
A pulse is generated at the beginning of the BER measure window. This is an
ber_timer_done(3:0) Out informal signal, which is typically left unconnected during normal operation.
Optional FEC (Clause 74) Module Configuration

(signals exist only if FEC74 synthesis option is available)
Per channel enable Base-R (Firecode) Forward Error Correction (FEC74) in both
transmit and receive.
Enabling or Disabling FEC74 can occur at any time during operation. Due to the
link coding change this will cause a link re-start.
Every serdes lane contains two FEC74 functions. See 5.2 page 24 for FEC74 to
fec_ena(3:0) In serdes lane associations.
Note: The remote device needs to enable FEC support also before a link will be
established.
Asynchronous input.
Note: Availability of the FEC74 module is a synthesis option.
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Per channel enable optional error propagation in receive when FEC is active
(IEEE 802.3 Clause 74.8.3). When enabled uncorrectable error blocks will cause
fec_err_ena(3:0) In injection of sync header errors to allow error detection by the PCS layer.
Asynchronous input.
Per FEC receive lock indication. When FEC is enabled (fec_ena) each virtual lane
implements an independent FEC function. All FECs must be locked before the
fec_locked(7:0) Out PCS can achieve synchronization and alignment.
Note: FEC lock can take a significant amount of time (milliseconds).
Per virtual lane FEC correctable errors indication. When FEC is enabled (fec_ena)
and fec lock has been achieved the signal asserts whenever bit errors were
fec_cerr(7:0) Out detected that were fully corrected by the FEC.
Asserts at maximum once per FEC coding block (32x 66bit blocks ~204ns).
Per virtual lane FEC uncorrectable errors indication. When the FEC is enabled
(fec_ena) and fec lock has been achieved indicates whenever bit errors were
detected that could not be corrected. That is the receive data to the PCS
fec_ncerr(7:0) Out contained corrupt data.
Asserts at maximum once per FEC coding block (32x 66bit blocks ~204ns).
Channel 0 to 3 PCS Management Register Interface (N=0..3)

(Synchronous to reg_clk)
Register Write Enable.
regN_wren In
See 15 page 54 for interface details.
regN_rden In Register Read Enable.
regN_addr(15:0) In Register Address. Bit 0 is the least significant bit. Addresses 16-bit registers.
regN_din(15:0) In Register Write Data. Bit 0 is the least significant bit.
regN_dout(15:0) Out Register Read Data. Bit 0 is the least significant bit.
Register Interface Busy. Asserted (set to 1) during register read or register write
regN_busy Out access. Deasserts (0) for one reg_clk cycle to indicate the completion of the
current register access.
100G PCS Management Register Interface

reg_wren In
reg_rden In Register Read Enable.
reg_addr(15:0) In Register Address. Bit 0 is the least significant bit. Addresses 16-bit registers.
reg_din(15:0) In Register Write Data. Bit 0 is the least significant bit.
reg_dout(15:0) Out Register Read Data. Bit 0 is the least significant bit.
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reg_busy Out access. Deasserts (0) for one reg_clk cycle to indicate the completion of the
Clause 91 RS-FEC Management Register Interface

reg91_wren In
reg91_rden In Register Read Enable.
reg91_addr(7:0) In Register Address. Bit 0 is the least significant bit. Addresses 16-bit registers.
reg91_din(15:0) In Register Write Data. Bit 0 is the least significant bit.
reg91_dout(15:0) Out Register Read Data. Bit 0 is the least significant bit.
reg91_busy Out access. Deasserts (0) for one reg_clk cycle to indicate the completion of the
Configuration Indicators
(convenience signals only, not required to be used by the application for any specific purpose)
Indicates which lanes are currently in use by the PCS0.
4'b 0001 : 1-Lane - 10/25Geth
4'b 0011 : 2-Lane - 50Geth - 2-Lane 40Geth
pcs0_lane_active(3:0) Out 4'b 1111 : all other modes
Note: will indicate 4'b 1111 when 100G mode is active (i.e. not relevant as PCS0
is then not active).
Indicates which lanes are currently in use by the PCS2.
2'b 01 : 1-Lane - 10/25Geth
pcs1_lane_active(1:0) Out 2'b 11 : all other modes.
Note: will indicate 2'b 11 even when the PCS is not active (e.g. in 100G mode).
Presents the bits 3:0 of the PCS100 configuration register TX_LANE_

tx_lane_thresh0(3:0) Out
THRESH (offset 0x8003) which represent the setting for lane 0.

Presents the bits 11:8 bits of the PCS100 configuration register TX_LANE_

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4.2 Core Memory Interface Signals

The external memory interfaces are listed in table below. The memories interface behavior is
described in 21 page 67.
Table 2: Memory Interfaces Signal Description
RS-FEC Decoder Memory: 1 instance of

320 x 162bit (depth x width) - if the RS (544, 514) supported
Or
256 x 162bit (depth x width) - if the RS (544, 514) NOT supported
(all synchronous to ref_clk)
f91m_wren Out RSFEC memory write enable.
RSFEC memory write address. m = 8, if the the RS (544, 514) supported,

f91m_waddr(m:0) Out
otherwise 7
f91m_wdata(161:0) Out RSFEC memory write data to memory.
f91m_rden Out RSFEC memory read enable
RSFEC memory read address. m = 8, if the the RS (544, 514) supported,

f91m_raddr(m:0) Out
otherwise 7
f91m_rdata(161:0) In RSFEC memory read data from memory.
RS-FEC Error Propagation Delay Memory: 4 instances of 16 x 257bit each

(all synchronous to ref_clk)
f91dm_wren(3:0) Out Per RSFEC Delay Memory write enable. One bit per memory.
f91dm_waddr_0(3:0)
f91dm_waddr_1(3:0)
Out Per RSFEC Delay Memory write address
f91dm_waddr_2(3:0)
f91dm_waddr_3(3:0)
f91dm_wdata_0(256:0)
Out Per RSFEC Delay Memory write data to memory.
f91dm_rden(3:0) Out Per RSFEC Delay Memory read enable. One bit per memory.
f91dm_raddr_0(3:0)
f91dm_raddr_1(3:0)
Out Per RSFEC Delay Memory read address
f91dm_raddr_2(3:0)
f91dm_raddr_3(3:0)
f91dm_rdata_0(256:0)
In Per RSFEC Delay Memory read data from memory.
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Deskew Memory: 8 instances of 64 x 67bit (dual-clock) each
Write side interfaces operate synchronous to each lane's receive clock.

There are always 2 memories per serdes lane.
Per Deskew Memory write enable. One bit per memory.

Bits 1:0 are synchronous to sd0_rx_clk (memories 1,0)
desk_m_wren(7:0) Out Bits 3:2 are synchronous to sd1_rx_clk (memories 3,2)
Per Deskew Memory write address. 6-bit per memory.

desk_m_waddr(8*6-1:0) Out Bits 23:12 are synchronous to sd1_rx_clk (memories 3,2)
Per Deskew Memory write data to memory. 67-bit per memory.

desk_m_wdata(8*67-1:0) Out Bits 267:134 are synchronous to sd1_rx_clk (memories 3,2)
Read side interfaces operate synchronous to ref_clk.
Per Deskew Memory read enable. One bit per memory.

desk_m_rden(7:0) Out
all synchronous to ref_clk (memories 7..0)
Per Deskew Memory read address. 6-bit per memory.

desk_m_raddr(8*6-1:0) Out
Per Deskew Memory read data from memory. 67-bit per memory.
desk_m_rdata(8*67-1:0) In
4.3 Optional Base-R FEC (FEC-74) Memory Interface Signals

The Clause 74 FEC (Base-R FEC or Firecode FEC) memory interfaces are available only if the
FEC74 option is available and has been enabled in the Core package file (see User Guide).
When the option is available and enabled, per serdes lane two FEC instances exist.
Table 3: FEC74 (Optional) Memory Interfaces Signal Description
FEC74 Decoder Memories: 8 instances of 32 x 65bit.

When the asynchronous Core variant is implemented, all interfaces operate synchronous to each lane's
individual receive clock. For the synchronous Core variant all operate on ref_clk.
There are always 2 memories per serdes lane.
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fm_wren_sd_vec(7:0) Out Bits 3:2 are synchronous to sd1_rx_clk (memories 3,2)

fm_waddr_sd_vec(8*5-1:0) Out Bits 19:10 are synchronous to sd1_rx_clk (memories 3,2)

fm_wdata_sd_vec(8*65-1:0) Out Bits 259:130 are synchronous to sd1_rx_clk (memories 3,2)

fm_rden_sd_vec(7:0) Out Bits 3:2 are synchronous to sd1_rx_clk (memories 3,2)
fm_raddr_sd_vec(8*5-1:0) Out Bits 19:10 are synchronous to sd1_rx_clk (memories 3,2)
fm_rdata_sd_vec(8*65-1:0) In Bits 259:130 are synchronous to sd1_rx_clk (memories 3,2)
FEC74 RX Error Propagation Delay Memories

fdm_wren_sd_vec(7:0) Out Bits 3:2 are synchronous to sd1_rx_clk (memories 3,2)

fdm_waddr_sd_vec(8*5-1:0) Out Bits 19:10 are synchronous to sd1_rx_clk (memories 3,2)
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fdm_wdata_sd_vec(8*66-1:0) Out Bits 263:132 are synchronous to sd1_rx_clk (memories 3,2)

fdm_rden_sd_vec(7:0) Out Bits 3:2 are synchronous to sd1_rx_clk (memories 3,2)
fdm_raddr_sd_vec (8*5-1:0) Out Bits 19:10 are synchronous to sd1_rx_clk (memories 3,2)
fdm_rdata_sd_vec(8*66-1:0) In Bits 263:132 are synchronous to sd1_rx_clk (memories 3,2)
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5 Mode Configuration and Channel/Lane Associations

Depending on the mode of operation the different datapathes through the Core are active.
5.1 PCS/Endec Interfaces Overview

The Core exposes 6 separate data interfaces which are used as applicable:
Table 4: Core Interface Definitions
Interface Used for Mode Uses Notes

Serdes
Lanes
CGMII 100G Ethernet 0..3 When operating with the normal 100G PCS a
100G Ethernet MAC is attached through the
CGMII
CH0 - 10G/25G - 1 lane 0 or Channel 0 allows operation in 10/25/40/50G.
XLGMII
40G - 4 Lanes 0..3 or When operating in 10/25G Clause 49 mode of
operation should be used implementing XGMII.
50G - 2 Lanes 0,1
When operating in 40G over 4 lanes none of the
other channel interfaces is useable.
When operating in 50G over 2 lanes it uses
Serdes lanes 0,1 and the other 2 Serdes lanes
can be used by channels 2..3.
CH1 - 10/25 - 1 lane 1 Channel 1 allows operation in 10/25G.
XLGMII
The PCS should always be configured in Clause
49 mode of operation implementing XGMII.
CH2 - 10/25 - 1 lane 2 or Channel 2 allows operation in 10/25/40/50G.
XLGMII
50G - 2 lanes 2,3 When operating in 10/25G Clause 49 mode of
operation should be used implementing XGMII.
When operating in 50G over 2 lanes it uses
Serdes lanes 2,3 and channel 3 is not usable.
CH3 - 10/25 - 1 lane 3 Channel 3 allows operation in 10/25G.
XLGMII
The PCS should always be configured in Clause
49 mode of operation implementing XGMII.
5.2 Mode Configuration Pins

The following pins are relevant for mode configuration
Table 5: Mode Control Pins Overview
PinName Description Notes

sd_n2(3:0) Defines 40bit(0) or When a serdes operates at 10.3Gbps it
20bit(1) interface per should be configured for 20bit width (Using
serdes lane. bits 19:0).
Otherwise it should be set to 40bit width.
fec91_ena_in(3:0) Enables RS-FEC When a channel operates at 25G, 50G or
operation per serdes. 100G the RS-FEC can be used.
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For 25G each bit enables the corresponding

channel's RS-FEC datapath.
For 50G both bits 1:0 must be set when
channel 0 operates with 50G. Bits 3:2 must
both be set for channel 2 accordingly.
To configure RS-FEC for 100G, all 4 bits
must be set to 1.
kp_mode_in(3 :0) Selects RS codewords Enable control for RS-FEC (Clause 91)
used for RS-FEC datapath per serdes lane. When asserted (1)
operation. the RS (544, 514) codewords are used,
otherwise the RS (528, 514) codewords .
The setting is relevant, only when RS FEC
for the same lane is set.
The kp_mode_in is set per serdes lane.
For 50G both bits 1:0 must be set when
channel 0 operates with 50G. Bits 3:2 must
both be set for channel 2 accordingly.
To configure RS-FEC for 100G, all 4 bits
must be set to 1.
fec91_1lane_in0 Defines for Channel 0 When set, it implicitly defines to operate
and 1 to operate RS-FEC serdes with 25G using 40bit: i.e. when
fec91_1lane_in2
in fec91_1lane_inN=1 then sd_n2(N) must
25G over 1 lane (1) or be 0.
50G over 2 lanes (0).
rxlaui_ena_in0 Defines for Channel 0 In this mode the FEC74 can be used (must
and 2 to operate over 2 then be enabled for all lanes that correspond
rxlaui_ena_in2
lanes using 2:1 bitmuxing to the channel).
of the 4 Virtual lanes
When set, it implicitly defines to operate
without RS-FEC. Allows
serdes with 25G using 40bit: i.e. when
use of FEC74 with 50G.
rxlaui_ena_inN=1 then sd_n2(N) must
be 0.
fec_ena_rx(3:0) Enables FEC74 support Every serdes lane contains 2 FEC74
per channel. functions.
fec_ena_tx(3:0)
There are 2 FEC74 Lane 0: uses FEC74 0 and 1
fec_err_ena(3:0)
functions per serdes lane. Lane 1: uses FEC74 2 and 3
Lane 2: uses FEC74 4 and 5
Lane 3: uses FEC74 6 and 7
When a lane is used for a single-lane
protocol then FEC74 0,2,4,6 are relevant for
serdes lanes 0,1,2,3 respectively.
When multi-lane protocols are used then the
FEC association is as follows:
FEC74(0,2,4,6) is used for 40G Channel0
operating at 10G per lane.
which uses 2:1 bitmuxing on serdes lanes
0,1.
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which uses 2:1 bitmuxing on serdes lanes

2,3.
pcs100_ena_in Enables the 100G PCS When enabled the 100G PCS can be used
datapath. with a 100G MAC (CGMII).
mode40_ena_in Enable 40G Mode of When enabled (1) the Channel 0 is using all
operation of 4 lanes. 4 lanes. Channels 1..3 are unusable.
When disabled (0) all channels operate
independently and can be configured to
10/25 or 50 individually.
Requires pcs100_ena_in=0, as 100G takes
precedence.
Optional Settings
fast_1lane_mode Lower Latency 10G Optional latency reduction when using a higher
reference clock. Relevant for the asynchronous
operation for a channel
design variant only.
pacer_10g 10G interface rate burst Optional setting to avoid bursts occurring at the
10G interfaces. Relevant for the asynchronous
avoidance
design variant only.
scrambler_bypass_100g Enables Scrambler When set to ‘1’, the transmit data are not
scrambled. The input can be used for debug
bypass for 100G mode.
purpose in the 100g operational mode.
For standard operation in 100G mode this input
must be set to 0.
descr_bypass_100g Enables Descrambler When set to ‘1’, the receive data are not
descrambled. The input can be used for debug
bypass for 100G mode.
purpose in the 100g operational mode.
For standard operation in 100G mode this input
must be set to ‘0’.
5.3 Mode Configuration PCS Registers

In addition to the above shown mode control pins, the related PCS layers when active in a mode
need to be configured as required by the mode. The following registers are relevant and the
application should take care of initializing these during system configuration.
Table 6: Mode Control PCS Registers
PCS Register Mode of Operation Notes

(offset within
PCS register
map)
10G 25G 40G 50G
VL_INTVL not 20479 16383 depending on RS- See also 9 page
relevant FEC usage. 37 for marker
(0x8002)
distances and
CH1 same as CH0;
compensation
CH3 same as CH2.
requirements.
VL0_0, VL0_1 not relevant only must be CH1 same as CH0; See 8.2 page
relevant when using set CH3 same as CH2. 34 for correct
(0x8008,
RS-FEC. marker values
0x8009)
to set.
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PCS_MODE must Channels 0,2 Channels Channels 0,2 must

disable must enable 0,2 must enable MLD and
(0x8010)
MLD and MLD and enable Clause 82
enable Clause 49 MLD and
(value 0)
Clause 49 (value 0x03) Clause
82
(value Channels 1,3
0x03) to enable (value 0)
Clause 49
(value 0x01)
5.3.1 50G with RS-FEC Specific Settings Requirements
When operating channel 0 or channel 2 with 50G over 2 lanes with RS-FEC, the PCS that is
associated with the 2nd lane must be configured identically with respect to marker distance and
marker values, even though that other lane's PCS layer is not in use. The configuration of the
other lane's PCS is still affecting the lane synchronization modules at the individual serdes lane.
This means:
 When channel 0 PCS is used in 50G then Channel 1 PCS settings must be identical.
 When channel 2 PCS is used in 50G then Channel 3 PCS settings must be identical.
5.4 Software reset usage

Each PCS has SW reset capability (bit 15 of Control 1 register).
The setting SW reset bit in the 100G PCS Control 1 register will reset complete Mapper including
Serdes lane interfaces independently on the IP configuration.
PCS0..3: The writing one in this bit brings the data path and control logic for this channel to an
initial state. Depending on the channel configuration all serdes lanes used in this mode will be also
reset. Generally the SW reset should be used for a clean start of the channel operation.
If the SW reset is applied to an operational channel, only its PCS and a Mapper logic, related to
this channel, will be reset with no effect to other channels. For example, Channel 0 operates over
lane 0 and 1, and Channel 2 over lane 2 and 3. Both channels can be reset independently from
each other.
Note: It should be avoided to issue SW reset for a non-active channel. The SW logic treats a non-
active channel as a channel operated over single Serdes lane. Thus SW reset to such channel will
cause the reset not only to the relevant PCS but also to Mapper related logic including Serdes
lane. For example: If the channel 0 is running over four lanes, and SW reset is issued for the
Channel 2 (which is not active), the Serdes Lane logic and core/data path for lane 2 will be reset.
This will eventually cause internal reset for Channel 0.
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6 100Geth PCS
6.1 Use of Blocks

The PCS maps CGMII signals into 66-bit blocks, and vice versa, using a 64B/66B coding scheme.
The synchronization headers of the blocks allow establishment of block boundaries by the PCS
Synchronization process. Blocks are unobservable and have no meaning outside the PCS. The
PCS functions ENCODE and DECODE generate, manipulate, and interpret blocks as provided by
the rules in 6.2.2.
6.2 64B/66B Transmission Code

6.2.1 Overview
The PCS uses a transmission code to improve the transmission characteristics of information to be
transferred across the link and to support transmission of control and data characters. The
encodings defined by the transmission code ensure that sufficient transitions are present in the
PHY bit stream to make clock recovery possible at the receiver. The encoding also preserves the
likelihood of detecting any single or multiple bit errors that may occur during transmission and
reception of information. In addition, the synchronization headers of the code enable the receiver
to achieve block alignment on the incoming PHY bit stream. The 64B/66B transmission code
specified for use in this standard has a high transition density and is a run-length-limited code.
64B/66B encodes 8 data octets or control characters into a block. Blocks containing control
characters also contain a block type field. Data octets are labeled D 0 to D7. Control characters
other than /O/, /S/ and /T/ are labeled C0 to C7 . The control character for Ordered Set is labeled as
O0 since it is only valid on an 8B boundary of the CGMII. The control character for Start is labeled
as S0 for the same reason. The control character for Terminate is labeled as T0 to T7.
One CGMII transfer provides 24 characters which are encoded into three 66-bit transmission
blocks. The subscript in the above labels indicates the position of the character on an 8B boundary
of the CGMII for each of the three blocks.
Contents of block type fields, data octets and control characters are shown as hexadecimal
values. The LSB of the hexadecimal value represents the first transmitted bit.
For instance, the block type field 0x1e is sent from left to right as 01111000. The bits of a
transmitted or received block are labeled TxB<65:0> and RxB<65:0>, respectively, where TxB<0>
and RxB<0> represent the first transmitted bit. The value of the sync header is shown as a binary
value. Binary values are shown with the first transmitted bit (the LSB) on the left in the following
tables to conform with IEEE 802.3ae notation.
6.2.2 Block Structure
Blocks consist of 66 bits. The first two bits of a block are the synchronization header (sync
header). Blocks are either data blocks or control blocks. The sync header is 01 (lsb msb) for data
blocks and 10 (lsb msb) for control blocks. Thus, there is always a transition between the first two
bits of a block. The remainder of the block contains the payload. The payload is scrambled and the
sync header bypasses the scrambler. Therefore, the sync header is the only position in the block
that always contains a transition. This feature of the code is used to obtain block synchronization.
Data blocks contain eight data characters. Control blocks begin with an 8-bit block type field which
indicates the format of the remainder of the block. For control blocks containing a Start, Terminate
or Ordered Set character, that character is implied by the block type field. Other control characters
are encoded in a 7-bit control code. Each control block contains eight characters.
The format of the blocks is as shown in Figure 4. In the figure, the column labeled “Input Data”
shows, in abbreviated form, the eight characters used to create the 66-bit block. These characters
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are either data characters or control characters and, when transferred across the CGMII interface,
the corresponding TXC or RXC bit is set accordingly. Within the “Input Data” column, D 0 through
D7 are data octets and are transferred with the corresponding TXC or RXC bit set to zero. All other
characters are control octets and are transferred with the corresponding TXC or RXC bit set to
one. The single bit fields (thin rectangles with no label in the figure) are sent as zero and ignored
upon receipt.
Bits and field positions are shown with the least significant bit on the left. Hexadecimal numbers
are shown in normal hexadecimal. For example the block type field 0x1e is sent as 01111000 (lsb
first) representing bits 2 through 9 of the 66 bit block.
All unused values of block type field are reserved.
6.2.3 Control Codes
The same set of control characters are supported by the CGMII and the 100GBASE-R PCS. The
representations of the control characters are the control codes. CGMII encodes a control character
into an octet (an eight bit value). The 100GBASE-R PCS encodes the Start and Terminate control
characters implicitly by the block type field. The 100GBASE-R PCS encodes the Ordered Set
control codes using the block type field. The 100GBASE-R PCS encodes each of the other control
characters into a 7-bit C code.
The control characters and their mappings to 100GBASE-R control codes and CGMII control
codes are specified in Table 7. All CGMII and 100GBASE-R control code values that do not
appear in the table shall not be transmitted and shall be treated as an error if received.
Sync
Input Data Block Payload
Bit Position : 0 1 2 65
Data Block Format :

D0 D1 D2 D3/D4 D5 D6 D7 01 D0 D1 D2 D3 D4 D5 D6 D7
Block
Control Block
Type
Formats:
Field
C0 C1 C2 C3/C4 C5 C6 C7 10 0x1e C0 C1 C2 C3 C4 C5 C6 C7
S0 D1 D2 D3/D4 D5 D6 D7 10 0x78 D1 D2 D3 D4 D5 D6 D7
O0 D1 D2 D3/C4 C5 C6 C7 10 0x4b D1 D2 D3 O0 C4 C5 C6 C7
T0 C1 C2 C3/C4 C5 C6 C7 10 0x87 C1 C2 C3 C4 C5 C6 C7
D0 T1 C2 C3/C4 C5 C6 C7 10 0x99 D0 C2 C3 C4 C5 C6 C7
D0 D1 T2 C 3/C4 C5 C6 C7 10 0xaa D0 D1 C3 C4 C5 C6 C7
D0 D1 D2 T3/C4 C5 C6 C7 10 0xb4 D0 D1 D2 C4 C5 C6 C7
D0 D1 D2 D 3/T4 C5 C6 C7 10 0xcc D0 D1 D2 D3 C5 C6 C7
D0 D1 D2 D 3/D4 T5 C6 C7 10 0xd2 D0 D1 D2 D3 D4 C6 C7
D0 D1 D2 D 3/D4 D5 T6 C7 10 0xe1 D0 D1 D2 D3 D4 D5 C7
D0 D1 D2 D 3/D4 D5 D6 T7 10 0xff D0 D1 D2 D3 D4 D5 D6
Figure 4: 64B/66B Block Formats
6.2.4 Ordered Sets
Ordered Sets are used to extend the ability to send control and status information over the link
such as remote fault and local fault status. With 8B alignment in 100 Gigabit Ethernet, ordered
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sets span 8 bytes. Ordered sets always begin on an 8B boundary of the CGMII. 100 Gigabit
Ethernet uses one kind of ordered_set: the sequence ordered_set (see 82.2.3.9 in [1]). The
sequence ordered_set control character is denoted /Q/. An additional ordered_set, the signal
ordered_set, has been reserved and it begins with another control code. See Table 7, page 30 for
the mappings.
6.2.5 Valid and Invalid Blocks
A block is invalid if any of the following conditions exists:

a) the sync field has a value of 00 or 11;
b) the block type field contains a reserved value;
c) any control character contains a value not in Table 7.
d) a set of eight CGMII characters does not have a corresponding block format in Figure 4.
6.2.6 Idle (/I/)
Idle control characters (/I/) are transmitted when idle control characters are received from the
CGMII. Idle characters may be added or deleted by the PCS to adapt between clock rates. /I/
insertion and deletion shall occur in groups of 8. /I/s may be added following idle or ordered sets.
They shall not be added while data is being received. When deleting /I/s, the minimum IPG of one
character is maintained.
Note: the PCS uses a clock-enable based scheme to adapt the rates making idle insertion/deletion
at the CGMII obsolete.
Table 7: Control Codes
Control CGMII 100GBASE-R 100GBASE-R

Notation
Character Control Code O Code Control Code
idle /I/ 0x07 0x00
start /S/ 0xfb encoded by block type field
terminate /T/ 0xfd encoded by block type field
error /E/ 0xfe 0x1e
encoded by block type 0x4b

Sequence
/Q/ 0x9c 0x0 plus O code, control codes
ordered_set
are set to 0x00
encoded by block type 0x4b

Signal
/Fsig/ 0x5c 0xf plus O code, control codes
ordered_set‡
are set to 0x00
‡ Reserved for INCITS T11 Fibre Channel use.
6.2.7 Start (/S/)
The start control character (/S/) indicates the start of a packet. This delimiter is only valid on an 8B
boundary of the CGMII (TXD<7:0>, TXD<71:64>, TXD<135:128>, …, RXD<7:0>, RXD<71:64>,
RXD<135:128>, …). Receipt of an /S/ on any other octet of TXD indicates an error. Block type field
values implicitly encode an /S/ as the first character of the block. This is the only character of a
block on which a start can occur.
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6.2.8 Terminate (/T/)
The terminate control character (/T/) indicates the end of a packet. Since packets may be any
length, the /T/ can occur on any octet of the CGMII interface and within any character of the block.
The location of the /T/ in the block is implicitly encoded in the block type field. A valid end of packet
occurs when a block containing a /T/ is followed by a control block that does not contain a /T/.
6.2.9 Ordered_Set (/O/)
The ordered_set control characters (/O/) indicate the start of an ordered_set. There are two kinds
of ordered sets: the sequence ordered_set and the signal ordered_set (which is reserved). When it
is necessary to designate the control character for the sequence ordered_set specifically, /Q/ will
be used. /O/ is only valid on an 8B boundary of the CGMII. Receipt of an /O/ on any other octet of
TXD indicates an error. Block type field values implicitly encode an /O/ as the first character of the
block.
Sequence ordered_sets may be deleted by the PCS to adapt between clock rates. Such deletion
shall only occur when two consecutive sequence ordered sets have been received and shall
delete only one of the two. Only Idles may be inserted for clock compensation. Signal
ordered_sets are not deleted for clock compensation.
6.2.10 Error (/E/)
The error control character (/E/) is sent whenever an /E/ is received. It is also sent when invalid
blocks are received. The /E/ allows the PCS to propagate received errors. See R_BLOCK_TYPE
and T_BLOCK_TYPE function definitions in [1] Clause 82.2.19.2.3 for further information.
6.3 Transmit Functions

6.3.1 Overview
The transmit process generates blocks based upon the TXD<191:0> and TXC<23:0> signals
received from the CGMII. Each CGMII data transfer is encoded into 3 blocks. It takes e.g. 1.65 40-
bit transfers on the PMA Service Interface to send a block of data. Therefore, if the PCS is
connected to a CGMII and PMA sublayer where the ratio of their transfer rates is exactly 64:66,
then the transmit process does not need to perform rate adaptation. Where the CGMII and PMA
sublayer data rates are not synchronized to that ratio, the transmit process will need to insert idles,
delete idles, or delete sequence ordered sets to adapt between the rates.
The transmit process generates blocks as specified in the transmit process state machine. The
contents of each block are contained in a vector tx_coded<65:0> which is passed to the
scrambler. tx_coded<1:0> contains the sync header, and the remainder of the vector contains the
block payload.
6.3.2 Scrambler
The payload of the block is scrambled with a self-synchronizing scrambler. The scrambler shall
produce the same result as the implementation shown in Figure 5. This implements the scrambler
polynomial1 :
G x1 + x39 + x58 (1)
1
The convention here, which considers the most recent bit into the scrambler to be the lowest order term, is
consistent with most references and with other scramblers shown in the 802.3 standard. Some references
consider the most recent bit into the scrambler to be the highest order term and would therefore identify this as
the inverse of the polynomial in equation (1). In case of doubt, note that the conformance requirement is based
on the representation of the scrambler in the figure rather than the polynomial equation.
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There is no requirement on the initial value for the scrambler. The scrambler is run continuously on
all payload bits. The sync header bits bypass the scrambler.
Figure 5: Scrambler
6.4 Receive Functions

6.4.1 Overview
The receive process decodes blocks to produce RXD<191:0> and RXC<23:0> for transmission to
the CGMII. One CGMII data transfer is decoded from 3 blocks. Where the CGMII and PMA
sublayer data rates are not synchronized to a 64:66 ratio, the receive process will insert idles,
delete idles, or delete sequence ordered sets to adapt between rates.
If the receive state machine is not in sync (block_lock deasserted) or experiences high bit errors
(hi_ber asserted), the PCS will provide the Local Fault Sequence to the Reconciliation Sublayer
via CGMII.
6.4.2 Descrambler
The descrambler processes the payload to reverse the effect of the scrambler using the same
polynomial. It shall produce the same result as the implementation shown in the figure below.
Figure 6: Descrambler
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7 Block Synchronization
When the receive channel is operating in normal mode, the block synchronization function
receives data in 66-bit words, obtains lock to the 66-bit blocks using the sync headers and outputs
66-bit blocks. Lock is obtained as specified in the block lock state machine shown in Figure 7
below.
Figure 7: Block Lock State Machine
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8 Multi-Lane Distribution (MLD)
8.1 Transmit MLD

Multi-Lane Distribution on the transmit channel comprises the Virtual Lane Distribution and
Alignment Marker Insertion. The encoded transmit data is distributed across n virtual lanes in a
round-robin fashion on a 66-bit block basis.
The number of virtual lanes chosen is based on the Least Common Multiple (LCM) of the n lane
electrical interface and the m lane PMD that should be supported. In order to cover all of the
possible combinations of lanes, the required number if 20 for 100G Base-R PCS.
Table 8: 100G Virtual Lanes Requirement
Electrical Lane Widths PMD Lane Widths Virtual Lanes Needed
10, 5, 4, 2, 1 10, 5, 4, 2, 1 20
This allows all data (bits) from one virtual lane to be transmitted over the same electrical and
optical lane combination and ensures that the data from a virtual lane is always received with the
correct bit order at the receive MLD.
Periodic alignment blocks (alignment markers) are added to each virtual lane. The alignment
markers allow the receive PCS to perform skew compensation, realign all the virtual lanes, and
reassemble a single 100G aggregate stream (with all the blocks in the correct order). The
alignment markers are inserted after every 16383 66-bit blocks on each virtual lane at the same
time. The alignment markers are 66-bit blocks containing a virtual lane identifier, as shown in
Figure 8 below.
2-bit 32-bit 32-bit

01 2 33 34 65
10 VL ~VL
Figure 8: Alignment Marker Format
Note: The PCS Core does not compensate for inserted alignment markers. The MAC is expected
to remove one block of Idle every 16384 blocks resulting in 16383 blocks at the CGMII (which is
implemented as such in the 40/100G MAC).
8.2 Marker Encodings

8.2.1 100G Markers
When the Core operates in 100Geth mode the encodings of the virtual lane identifiers are shown
in Table 9 for 100GBASE-R.
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Table 9: 100GBASE-R Alignment Marker Encodings
Marker Value Marker Value

VL Number VL Number
{m0, m1, m2} {m0, m1, m2}
0 C1, 68, 21 10 FD, 6C, 99
1 9D, 71, 8E 11 B9, 91, 55
2 59, 4B, E8 12 5C, B9, B2
3 4D, 95, 7B 13 1A, F8, BD
4 F5, 07, 09 14 83, C7, CA
5 DD, 14, C2 15 35, 36, CD
6 9A, 4A, 26 16 C4, 31, 4C
7 7B, 45, 66 17 AD, D6, B7
8 A0, 24, 76 18 5F, 66, 2A
9 68, C9, FB 19 C0, F0, E5
The 4th byte in every marker (not shown in above table) contains a Bit Interleaved Parity (BIP)
field.
8.2.2 40G/50G Markers
The 40G/50G capable PCS Layers should use the following markers as defined in [1] Table 82-3.
Note that 50G is the same as 40G, but may use different markers in the future.
The PCS layers provide programmable marker registers to allow adapting for future standards.
Marker Value
VL Number
{m0, m1, m2}
0 0x90, 0x76, 0x47
1 0xF0, 0xC4, 0xE6
2 0xC5, 0x65, 0x9B
3 0xA2, 0x79, 0x3D
8.2.3 25G Markers
When operating at 25Gbps with RS-FEC the MLD mechanism is used to insert markers into the
datastream allowing the receiver to recover the RS-FEC codeword boundaries. As the markers are
no longer used for lane deskew they are named Codeword Markers (CWM).
25G modes use the 100G VL0 marker to allow re-use of the same alignment sync function
independent of the mode of operation of a 25Gbps link. The marker 1..3 are taken from 40G hence
the marker table is as follows.
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Marker Value
VL Number
{m0, m1, m2}
0 0xC1, 0x68, 0x21
1 0xF0, 0xC4, 0xE6
2 0xC5, 0x65, 0x9B
3 0xA2, 0x79, 0x3D
The PCS layers provide programmable marker registers to allow adapting for future standards.
8.3 Receive MLD

Multi-Lane Distribution on the receive channel comprises the Alignment Marker Detection,
Alignment Marker Deletion and Virtual Lane Realignment.
Due to how virtual lanes are multiplexed, and due to skew on the electrical and optical interfaces,
transmitted virtual lanes can appear on any received virtual lane
In order to realign all the virtual lanes and to reassemble a single 100G aggregate stream, the VL
assignment need to be uniquely identified on the received virtual lanes. The incoming data on
each VL is parsed for one of the 20 alignment markers for 100GBASE-R. Alignment is declared on
each VL after finding 2 consecutive non-errored alignment patterns in the expected locations (after
every 16383 66-bit blocks). Out of alignment is declared on a VL after finding 4 consecutive
errored patterns. Once the alignment pattern is found on all VLs, then the VLs can be aligned.
Deskew buffers are required on each VL to compensate the different lane skews. The suggested
deskew buffer (FIFO) sizes (see 82.2.13 in [1]) are 928 bits per VL for 100G (20 VLs).
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9 Marker Compensation Requirements

On transmit depending on mode of operation markers are inserted into the datastream for multi-
lane (MLD) or RS-FEC modes to allow receiver synchronization and lane alignment. In addition the
Multi-link Gearbox function also uses the 100G PCS functions with multi-lane distribution.
The (external) MAC or PCS tx datapath needs to be aware of this and depending on the mode
must remove the corresponding amout of Idle data to compensate for the bandwidth loss
introduced by the marker insertion. Such compensation must be performed on the unencoded
CGMII/XLGMII/XGMII before the PCS encoding and scrambling.
The 100G PCS Mapper does not perform Idle compensation (as it operates with scrambled data).
Idle compensation is normally required on transmit direction only. In receive, the markers will be
removed and due to the clock-enable based concept there is no need to replace the removed
markers with additional idles. This however may depend on the PCS that is attached to the
Mapper Core's 66b Endec interfaces which may insert IDLEs as necessary on its own.
Depending on the Mode, the PCS MLD function inserts markers at different distances. The MAC
(when performing marker compensation) and PCS must be configured to the same and correct
marker distance setting to allow a proper link establishment. The marker distance settings are
configured in registers:
 PCS Register: VL_INTVL (Vendor specific register region)
 MAC Register: TX_IPG_LENGTH (depending on MAC variant)
The following table lists the required settings for standard compliance. In addition, for simulation
speedup non-compliant smaller values can be used.
Table 12: PCS and MAC Marker Distance Settings
PCS Mode Uses PCS MAC Notes

Marke (marker
rs ? compen-
sation)
Marker Distance
Setting
40G yes 16383 16383 Standard required setting for normal operation.
For simulation speedup the PCS can be configured
with a marker distance of 127 (or 63 if no/small
skew is present).
25G - no FEC no n.a. 0 No markers are used. MAC must not perform
25G - FEC74 compensation.
25G - RSFEC yes 20479 20479 Standard required setting for normal operation.
50G - RSFEC For simulation speedup the PCS setting can be 159
(or 79 if no/small skew is present).
50G - no FEC yes 16383 16383 Standard required setting for normal operation.
50G - FEC74 For simulation speedup the PCS can be configured
with a marker distance of 127 (or 63 if if no/small
skew is present).
100G yes 16383 16383 Standard required setting for normal operation. The
setting applies to normal mode as well as FEC
modes.
For simulation speed-up the values 63 or 255 can
be used (no others are allowed).
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Note: The table lists the amount of 66b blocks within which the amount of 8 Idle bytes must have
been removed. For a Clause 82 PCS (40G/50G/100G) this is identical to dropping one 66b block
of idles. For a Clause 49 PCS (10G/25G) this requires dropping two times 4-byte XGMII Idle
columns to respect the minimum IPG requirement of 5 for XGMII (see 802.3 Clause 46.2.1 and
49.2.4.7)
Note: When a PCS mode change occurs the application is responsible to initialize the PCS and
MAC (or other function responsible for marker compensation) marker distance registers correctly.
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10 Forward Error Correction (FEC, Clause 74) Option

The Clause 74 FEC module is an optional module (synthesis option) and may not exist in the
licensed Core configuration.
10.1 Overview
The IEEE 802.3 Clause 74 defines the Forward Error Correction (FEC) sublayer for Base-R PHYs
which is used on a per (virtual) lane basis. The FEC provides coding gain to increase the link
budget and BER (Bit Error Rate) performance. The Core optionally implements Transmit and
Receive FEC functions to provide additional margin to account for variations in manufacturing and
environmental conditions.
The FEC operates after the PCS on each virtual lane independently. Hence for 100GBase-R there
are 20 individual modules in each direction of the datapath.
10.2 Transmit FEC Encoder

The block diagram of the FEC Encoder is illustrated in “Figure 9”. The 32x65-bit payload blocks
are encoded by a (2112, 2080) code. This code is a shortened cyclic code that is encoded by
generator polynomial g(x). The FEC block is scrambled using the PN-2112 pseudo-noise
sequence.
66-Bit Encoded Blocks
PN-2112
Generation
Message or Parity
Compress Sync bits Selector
+
FEC 32-Bit Parity Generator
FEC Data
Figure 9: Transmit FEC Functions Overview
The generator polynomial g(x) for the (2112, 2080) parity-check bits are defined as given in the
following equation:
 g(x) = X32 + X23 + X21 + X11 + X2 + 1
PN-2112 is a pseudo-noise sequence of length 2112 generated by the following polynomial:
 r(x) = 1 + X39 + X58
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Scrambling with the PN-2112 sequence at the FEC codeword boundary is necessary for
establishing FEC block synchronization (to ensure that any shifted input bit sequence is not equal
to another FEC codeword) and to ensure DC balance.
10.3 Receive FEC Decoder

The FEC decoder establishes FEC block synchronization based on repeated decoding of the
received sequence. Decoding and error correction is performed after FEC synchronization is
achieved. The FEC is able to indicate decoding errors to PCS upper layers by generating errored
blocks.
The FEC decoding function block diagram is shown in “Figure 10”. The decoder processes the
data from the PMA and descrambles the data using the PN-2112 pseudo-noise sequence.
PMA Data
PN-2112
Generation
FEC Block Sync
Decoder FEC Error Monitor
66-Bit Block Generation
66-Bit Encoded Blocks
Figure 10: Receive FEC Functions Overview
Each of the 32 65-bit data words is extracted from the recovered FEC block and the 2-bit sync
header is reconstructed for the 66b code blocks.
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11 Reed-Solomon FEC (RS-FEC)
11.1 Overview
The IEEE802.3bj specification Clause 91 defines a Reed-Solomon Forward Error Correction (RS-
FEC) function for use with 100G applications using 4x 25.8Gbps Serdes technology.
The implemented RS-FEC supports 100GBase-KR4 and 100GBase-CR4 PHYs using RS(528,
514) codewords allowing correction of up to seven 10bit symbols within 514 such symbols.
Optionally the implementation also supports 100GBase-KP4 PHYs using RS(544, 514) codewords
allowing correction of up to fifteen 10bit symbols within 514 such symbols. (Note: This feature is
available, only when the synthesis option to enable the RS (544, 514) support is set. This feature
support is a matter of package’s delivery agreement and requires a different file list.)
In addition it allows usage for 25G single-lane and 50G 2-lane modes of operation.
The RS-FEC function can be enabled by the RS-FEC control register (see 22.1.1 page 76) or
toplevel input fec91_ena_in. When enabled, the 100G PCS datapath is changed and a different
coding is used that allows inserting the FEC overhead. The FEC layer is integrated directly into the
PCS omitting Virtual Lane (VL) distribution (MLD) and 66B block mux/de-mux functions providing a
low latency implementation.
The following figure shows the RS-FEC integration concepts when used with the 100G PCS Layer.
For clarity both datapathes are shown with their logical datapathes. This may not represent the
actual implementation which e.g. will share the deskew buffers and other common functions.
PCS TX
CGMII Trans-
code RS-FEC TX
GB SERDES TX
257
PCS MLD (4x 25.75G)
Error GB
Encode Marker
Inject
64/66 Insert
Lane GB
Lane
MLD * MUXLane
MUXBit GB
TX * 5:1
MUX
BIP8 5:1
MUX
5:1
5:1
20VL
rsfec_enable
PCS RX Lane Sync

Trans- RS-FEC Lane Lane Sync
code Check/ Re- Deskew
257 Correct order (4)
Lane Sync
Lane Sync SERDES RX

(4x 25.75G)
PCS Hi-Ber BIP8
Decode
(64/66) BS Bit
BS
5VL BS De-MUX GB
BS
BS 5:1
MLD
*
RX
*
Reorder 5VL BS + DeMux + GB
Deskew
(20VL)
* 5VL BS + DeMux + GB
*
5VL BS + DeMux + GB
Figure 11: RS-FEC PCS Integration Conceptual Overview
In transmit the RS-FEC datapath performs the following tasks:
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 Transcodes four encoded and scrambled 66bit blocks from PCS encoder into 257bit units
to create space for the FEC overhead information.
 Transcodes the PCS alignment markers to allow the remote receiver to determine symbol
boundaries and achieve lane synchronization.
 Adds the RS-FEC overhead
 Distributes the RS-FEC 10B symbols over the four serdes lanes.
In receive the RS-FEC datapath performs the following tasks:
 Synchronizes each serdes lane to the incoming marker patterns found in the bitstream to
recover RS-FEC symbol and codeword boundaries.
 Aligns (deskews) and reorders the four serdes lanes
 Forwards the reassembled codewords to the RS-FEC decoder for checking and possibly
correcting symbol errors.
 Removes the FEC overhead and Inverse-Transcodes the incoming 257bit units back into
66bit blocks which are forwarded to the PCS decoder function.
11.2 Status and Control Registers Information

The RS-FEC datapath does not use the PCS 66B block sync and lane reordering functions as the
FEC operates with a different lane encoding and 10B symbols. Hence, when operating in RS-FEC
mode, the per VL block synchronization (block lock) status and lane mapping status registers
within the PCS have no meaning (see 22.1 page 68). Instead the FEC provides its own lane
synchronization (amps lock) and lane mapping status registers (see 22.1.1 page 76).
The other PCS status indications operate normally as they are transparent to the RS-FEC and the
corresponding registers provide valid information. These are:
 PCS link status (alignment done): PCS register #1 "Status 1" bit 2 and #32 "Base-R Status
1" bit 12.
 PCS Hi-Ber monitoring function: PCS register #32 "Base-R Status 1" bit 1 and #33 "Base-
R Status 2" bit 14.
 Per VL alignment marker lock indications: PCS registers #52, 53 "Alignment Status 3,4".
These indicate detection of markers in correct positions.
 Per VL BIP8 (Bit Interleave Parity): PCS registers #90 .. #109 "BIP ERR CNT".
Resetting the PCS layer with the PCS register #0 "Control 1" bit 15 will also reset the FEC
datapath causing a link restart.
11.3 Correction Bypass Option

The RS-FEC receive datapath does not offer a configurable correction bypass feature. When RS-
FEC is enabled it always performs corrections.
11.4 Error Indication Bypass Option

The RS-FEC has the capability to indicate errors to the PCS layer when an uncorrected FEC
codeword has been detected. It does this by corrupting sync-headers of the decoded 66-bit blocks
after inverse-transcoding (forces 11 errors per FEC codeword which is 20x 4x66bit blocks).
Normally (correcting mode) the RS-FEC indicates errors to the PCS on codewords where it found
uncorrectable errors. However if correction is bypassed then errors are indicated for any incorrect
RS-FEC codeword detected.
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It is possible to disable this error propagation functionality through the RS-FEC Control register
(see Table 29 page 89). When it is disabled, latency is reduced by ~45ns when operating in
normal (correcting) mode.
When error indication is bypassed, the FEC keeps monitoring the amount of symbol errors
detected (802.3bj Clause 91.5.3.3). The errors from all lanes are accumulated over 8192
codeword intervals and if during such interval more than 416 symbol errors are found, the FEC will
corrupt sync-headers to the PCS continuously. This will cause the PCS to enter Hi-Ber state
indicating local fault to the CGMII. This high symbol error (SER) state will be kept for another
~60ms after the high error threshold is no longer reached. Then the FEC will clear the indication
again and fall back to normal operation.
The RS-FEC Status register bit 2 (high SER) asserts in this situation (see Table 30 page 91).
Note: If Autonegotiation is enabled, hi-ber assertion will cause it to restart.
Note: If short marker interval is configured (vl_intvl) the measurement window is shortened to 1/50 (164
codewords).
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12 System Clock Distribution
12.1 Clock Domains

The Core can be delivered in two variants: Either as an asynchronous variant or as a synchronous
variant. This is a deliverables variation and not configurable. Although the cores are functionally
identical for both variants, the clocking schemes differ for the serdes interfaces.
12.1.1 Asynchronous Design Variant
For the asynchronous variant the Core implements line interface asynchronous FIFOs to decouple
between the PMA Service Interface clocks and the reference clock ref_clk. The decoupling
FIFOs are placed at the Serdes interfaces.
The reference clock and the Serdes interfaces can be independent with no frequency or phase
requirements as long as the minimum frequency requirements are met (see below).
12.1.2 Synchronous Design Variant
For the synchronous variant the Core implements no serdes interface FIFOs. Instead it operates
all serdes interfaces with ref_clk. The serdes interfaces then must implement the clock-enable
based rate control as shown in Figure 21 page 64.
12.2 Clock Frequencies Overview

The frequency requirement for the reference clock ref_clk only depends on the Core mode of
operation. The highest mode active in any of the channels defines the minimum requirement.
The reference clock frequency can be any value higher than specified below, only restricted by the
chosen technology capability.
Table 13: System System Clock Frequencies
Reference Clock (ref_clk)

Mode of Operation
Minimum frequency
10Geth 516 MHz
10Geth with Low latency mode
626 MHz
enabled (fast_1lane_mode configured)
10/25Geth 645 MHz
10/25/40Geth 645 MHz
10/25/40/50Geth 782 MHz

100Geth 652 MHz
100Geth (RS FEC with RS (544, 514) ) 665 MHz
IMPORTANT: The given minimum frequencies must be respected. Any lower is not allowed (e.g.
644.53125 for 25G will not work, it must be 645MHz or higher).
The PMA interface clocks (sd_rx_clk(3:0) and sd_tx_clk(3:0), async variant only)
frequency is defined by to the Serdes speed and Serdes interface active width controlled with the
signal sd_n2.
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Table 14: Serdes Interface Clock Frequencies
PMA Interface Active Serdes

Serdes Speed sd_n2 PMA Interface frequency
Width Width
(257.8125MHz)
0 (40)
10.3125 Gbps 40 not recommended
1 20 515.625MHz
0 40 644.53125
25.78125 Gbps 40
(1) (20) (1.2890625GHz)
26,5625 Gbps
40 0 40 664,0625MHz
for RS FEC with
RS (544, 514) )
only
When the PMA operates at half-width (sd_n2=1) the lower 20 bits (19:0) of the interface are used and
the upper bits are ignored/arbitrary.
Notes:
 The ref_clk clock frequency can be of any frequency higher than specified above, only
restricted by the chosen technology capability.
 The SERDES/PMA interface clocks for one direction (TX/RX) are all independent and can
have arbitrary skew but must not drift. TX and RX interfaces are fully independent from
each other.
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12.3 Core System Clock Distribution

12.3.1 Asynchronous Core Variant
For the asynchronous Core variant having independent Serdes clocks, Figure 12 below shows the
system clock distribution as an example for the 100GBase-R PCS datapath when using a 40-bit
SERDES / PMA interface. The concepts and clock domain crossings are valid for all modes of
operation.
ref_clk
txclk 782 MHz
66 Clk Comp FIFO 66 Gearbox 40

sd0_tx_clk
sd1_tx_clk
XLGMII PCS MLD 66 Clk Comp FIFO 66 Gearbox 40
sd2_tx_clk
PMA Service Interfaces

MAC Interfaces
.. sd3_tx_clk
Deskew Buf 66 Block Sync 66 Gearbox 40

sd3_rx_clk
XLGMII PCS MLD Deskew Buf 66 Block Sync 66 Gearbox 40

sd2_rx_clk
sd1_rx_clk
sd0_rx_clk
rxclk
Figure 12: Asynchronous Core variant Clock Distribution
12.3.2 Synchronous Core Variant
The synchronous Core variant does not have separate serdes clocks and operates completely
with the single global reference clock ref_clk. The serdes interfaces then must implement the
clock-enable based rate control as shown in Figure 21 page 64.
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ref_clk
txclk
66 FIFO 66 Gearbox 40
XLGMII PCS MLD 66 FIFO 66 Gearbox 40
PMA Service Interface

..
MAC Interface
XLGMII PCS MLD Deskew Buf 66 Block Sync 66 Gearbox 40
rxclk
Figure 13: Synchronous Core Variant Clock Distribution
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13 Clock Decoupling FIFOs and Loopback
13.1 Overview
The PCS implements FIFOs to decouple between the PMA Service Interface clocks and the
system/CGMII clocks. The clock compensation FIFOs at the TX Serdes interfaces and the Rx MLD
Deskew Buffers on receive decouple the CGMII and PMA Service Interface transmit and receive
clocks, respectively.
cgmii_rxclk sd*_rx_clk
PCS Receive
XL/CGMII Interface
cgmii_txclk
Remote Fault
sd_tx_clk PCS Transmit
Figure 14: Clock Decoupling FIFOs Overview
Note: Even though the above figure shows independent cgmii_rx/txclk clocks these are connected to a
single reference clock (ref_clk).
13.2 CGMII Loopback

The CGMII loopback path is enabled when the 100G PCS loopback_ena control register bit is
set to '1' (PCS "Control 1" register bit 14). When the loopback path is enabled, data from CGMII
transmit is directly forwarded to CGMII receive.
When the loopback path is enabled the transmit data is transmitted normally. Data received from
the line (PMA) is discarded, however the receive clocks must be stable and running at the proper
frequencies (i.e. the PMA may need to be configured to operate it's receive interface from a local
reference clock if necessary).
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14 CGMII Interface
14.1 Overview
The CGMII output of the PCS can be connected directly to MorethanIP's 100G MAC as both Cores
implement the same 192-Bit CGMII interface.
On transmit, the 192 cgmii_txd signals and 24 cgmii_txc signals are organized into 24 data
lanes, as are the 192 cgmii_rxd signals and 24 cgmii_rxc on receive. The 24 lanes in each
direction share a common clock - cgmii_clk for both transmit and receive. The 24 lanes are
used in round-robin sequence to carry an octet stream. On both transmit and receive, signals are
synchronized on the clock rising edge only. The mapping of the 192-Bit transmit and receive data
signals is shown in Table 15.
Table 15: Lane Association
cgmii_txd cgmii_txc
Lane
cgmii_rxd cgmii_rxc
(7:0) (0) 0
(15:8) (1) 1
(23:16) (2) 2
(31:24) (3) 3
(39:32) (4) 4
(47:40) (5) 5
(55:48) (6) 6
(63:56) (7) 7
(71:64) (8) 8
(79:72) (9) 9
(87:80) (10) 10
(95:88) (11) 11
(103:96) (12) 12
(111:104) (13) 13
(119:112) (14) 14
(127:120) (15) 15
(135:128) (16) 16
(143:136) (17) 17
(151:144) (18) 18
(159:152) (19) 19
(167:160) (20) 20
(175:168) (21) 21
(183:176) (22) 22
(191:184) (23) 23
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14.2 Transmit
Code groups are used to indicate the Start of a Frame, Idle, End of a Frame and Sequence or
Error control characters.
Table 16: TXD / TXC Encoding
cgmii_txc cgmii_txd Description
0 Data Frame Data

1 0x00 through 0x06 Reserved
1 0x07 Idle
1 0x08 through 0x9B Reserved
Sequence
1 0x9C Only set on CGMII interface Lane 0, Lane 8, Lane 16,
etc.
1 0x9D through 0xFA Reserved
Start
1 0xFB Only set on CGMII interface Lane 0, Lane 8, Lane 16,
etc. Replaces the first byte of preamble
1 0xFC Reserved
Terminate
1 0xFD
Can be set on any Lane from 0 to 23
Transmit Error Propagation
1 0xFE
Can be set on any Lane from 0 to 23
1 0xFF Reserved
A start of frame code is always sent on an 8-Byte boundary, starting from Lane 0, that is, Lane 0,
Lane 8, Lane 16, etc.
14.2.1 Frame Transmit Operation
When no Ethernet Frame is available for transmission, the inter-frame gap is filled with Idles.
Idles are send on the lanes when the command bus (cgmii_txc) bit is set to 1 and 0x07 (Idle)
is on the data bus (cgmii_txd) [1]. A Frame starts when cgmii_txc is set to 1 and 0xFB
(Start) is on the data bus cgmii_txd [2]. The start of frame is only set on Lane 0, Lane 8,
Lane 16, etc. The pattern 0xFB on the data bus replaces the first Preamble byte. Frame Data
or Preamble bytes are sent on a lane when the corresponding command line is set to 0 [3]. The
end of frame is reached when one command line is set to 1 and the corresponding data bus is
set to 0xFD (Term) [4].
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1 2 3 4
xlmii_txc(3:0) 0xF 0x1 0x0 0x0 0x0 0xF
Lane 0 - xlmii_txd(7:0) Idle Start Data Data Data Idle
Lane 1 - xlmii_txd(15:8) Idle Dp Data Data Data Idle
Lane 7 - xlmii_txd(63:56) Idle SFD Data Data Data Idle
xlmii_txc (19:16) 0xF 0x0 0x0 0x0 0xC 0xF
Lane 16 - xlmii_txd (135:128) Idle Data Data Data Data Idle
Lane 18 - xlmii_txd (151:144) Idle Data Data Data T Idle
Lane 19 - xlmii_txd (159:152) Idle Data Data Data Idle Idle
xlmii_txc (23:20) 0xF 0x0 0x0 0x0 0xF 0xF
Figure 15: Frame Transmit
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14.2.2 Frame Transmit with Error
To propagate transmission errors, the transmitting device can insert error control characters in
the data stream by setting the control line n to ‘1’ with the Lane n set to 0xFE (Error) [1].
Lane 0 - xlmii_txd(7:0) Idle Start Data Data Data Idle
Lane 5 - xlmii_txd(47:40) Idle Dp Data Error Data Idle
Lane 7 - xlmii_txd(63:56) Idle SFD Data Data Data Idle
xlmii_txc (19:16) 0xF 0x0 0x0 0x0 0xC 0xF
Lane 18 - xlmii_txd (151:144) Idle Data Data Data T Idle
xlmii_txc (23:20) 0xF 0x0 0x0 0x0 0xF 0xF
Figure 16: Frame Transmit with Error
14.2.3 Start Control Character Alignment
On transmit, the start-of-frame character can only appear on an 8-Byte boundary, starting from
Lane 0, that is, Lane 0, Lane 8, Lane 16, etc. Additional Idle characters are inserted (by the
transmitting MAC) between frames to align the frame start on Lane 0, Lane 8, Lane 16, etc.
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14.3 Receive
14.3.1 Start Control Character Alignment
On the receive interface, a start-of-frame character may be received on any 8-Byte boundary,
starting from Lane 0, that is, Lane 0, Lane 8, Lane 16, etc.
14.3.2 Link Fault Signaling
The PCS is capable of detecting faults that render a Link unreliable for communication (loss of
synchronization or excessive bit errors). Upon recognition of a fault condition, the PCS device
indicates Local Fault status to the PCS Client via the CGMII interface. Link Fault status is
indicated in an 8-Byte Sequence (see Table 17 on page 53).
On the CGMII interface, a Sequence is represented as a control character on Lane n*8 set to
0x9C (with rxc=1) and data characters (with rxc=0) on Lanes (n*8)+1, (n*8)+2, (n*8)+4, (n*8)+5,
(n*8)+6, (n*8)+7 set to 0x00 and Lane (n*8)+3 set to 0x01 or 0x02 for a Local Fault or a
Remote Fault, respectively (see 81.3.4 in [1]).
Table 17: Link Fault Sequences
Lane Lane Lane Lane Lane Lane Lane

Lane n*8
(n*8)+1 (n*8)+2 (n*8)+3 (n*8)+4 (n*8)+5 (n*8)+6 (n*8)+7 Description
rxc=1
rxc=0 rxc=0 rxc=0 rxc=0 rxc=0 rxc=0 rxc=0
0x9C
0x00 0x00 0x01 0x00 0x00 0x00 0x00 Local Fault
(Sequence)
0x9C
0x00 0x00 0x02 0x00 0x00 0x00 0x00 Remote Fault
(Sequence)
It is up to the PCS Client (i.e., the Reconciliation Sublayer) to react to these sequences. The
PCS itself will only generate local fault sequences if it cannot recover correct data from the
attached PMA.
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15 XLGMII Interface
15.1 Overview
On transmit, the 64 xlgmii_txd signals and 8 xlgmii_txc signals are organized into 8 data
lanes, as are the 64 xlgmii_rxd signals and 8 xlgmii_rxc signals on receive.
When operating in 10Geth/25Geth mode of operation, two blocks of 4 octets XGMII data are
placed on the 64-bit XLGMII transmit and receive busses. The 4-octet block on
xlgmii_txd(31:0) is transmitted first, and the 4-octet block on xlgmii_rxd(31:0) is
received first.
The 8 lanes are used in round-robin sequence to carry an octet stream. On both transmit and
receive, signals are synchronized on the clock rising edge only.
The mapping of the 64-bit transmit and receive data signals is shown in the following table.
Table 18: Lane Association
xlgmii_txd xlgmii_txc
Lane
xlgmii_rxd xlgmii_rxc
(7:0) (0) 0
(15:8) (1) 1
(23:16) (2) 2
(31:24) (3) 3
(39:32) (4) 4
(47:40) (5) 5
(55:48) (6) 6
(63:56) (7) 7
On Transmit, the MAC should set on a lane the appropriate xlgmii_txd values with
xlgmii_txc to generate code groups or transmit frame data and on Receive, the Core decodes
the xlgmii_rxd values with xlgmii_rxc to generate code groups or frame data to the MAC.
Code groups are used to indicate the start of a Frame, Idle, end of Frame and Sequence or Error
control characters.
Table 19: TXD / TXC Encoding
xlgmii_txc xlgmii_txd
Description
xlgmii_rxc xlgmii_rxd
0 Data Frame Data
1 0x00 through 0x05 Reserved
1 0x06 Low Power Idle
1 0x07 Idle
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1 0x08 through 0x9B Reserved
Sequence
40Geth and 50Geth Modes: Only set on MAC Core
1 0x9C Lane 0
10Geth and 25Geth Mode: Only set on MAC Core
Lane 0 or Lane 4
1 0x9D through 0xFA Reserved
Start
40Geth and 40Geth Modes: Only set on MAC Core
Lane 0
1 0xFB
10Geth an 25Geth Mode: Only set on MAC Core Lane
0 or Lane 4
Replaces the first byte of preamble
1 0xFC Reserved
Terminate
1 0xFD
Can be set by the MAC Core on any Lane from 0 to 7
Transmit Error Propagation

1 0xFE
Can be set by the MAC Core on any Lane from 0 to 7
1 0xFF Reserved
15.2 Frame Transmit / Receive Operation

When no Ethernet Frame is available for transmission, the MAC should fill the inter-frame gap with
Idles. An Idle is send by the MAC when the command bus bit N (xlgmii_txc(N)) bit is set to 1
and the corresponding data byte is set to 0x07 on xlgmii_txd 1.
In 40Geth or 50Geth modes of operation, a frame starts when xlgmii_txc(0) is set to 1 and
0xFB (Start) is on the data bus xlgmii_txd(7:0) 2. The start of frame is only set on the MAC
Core interface Lane 0.
In 10Geth or 25Geth modes of operation, a frame starts when xlgmii_txc(0)is set to 1
and xlgmii_txd(7:0)is set to 0xFB or when xlgmii_txc(4)is set to 1 and
xlgmii_txd(39:32)is set to 0xFB. The start of frame is only set on the MAC Core interface
Lane 0 or Lane 4.
In all modes, the pattern 0xFB on the data bus should replace the first Preamble byte, Frame Data,
or preamble bytes, should be sent on a lane when the corresponding command bit (xlgmii_txc)
is set to 0 3.
The end of frame is reached when one command line is set to 1 and the corresponding Lane is set
to 0xFD (Term) 4.
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1 2 3 4
xlgmii_txc(7:0) 0xFF 0x01 0x00 0x00 0xC0 0xFF
Lane 0 - xlgmii_txd(7:0) Idle Start Data Data Data Idle
Lane 1 - xlgmii_txd(15:8) Idle Dp Data Data Data Idle
Lane 6 - xlgmii_txd(55:48) Idle Dp Data Data T Idle
Lane 7 - xlgmii_txd(63:56) Idle SFD Data Data Idle Idle
Figure 17: Frame Transmit
15.3 Frame Transmit with Error

To propagate transmission errors, the transmitting device can insert one or more error control
characters in the data stream by setting the control line n to ‘1’ with the corresponding Lane n set
to 0xFE (Error).
15.4 Frame Receive with Error

When the Core decodes an error encoded block or an invalid block or sequence of blocks, the
Core generates, on the XLGMII interface, an 8-byte column of 0xFE error control characters.
15.5 Start Control Character Alignment

In 40Geth and 50Geth modes of operation, the start-of-frame character is only allowed on Lane 0
and in 10Geth and 25Geth modes of operation, the start-of-frame character is only allowed on
Lane 0 or Lane 4.
15.6 Low Power Idle (LPI) Transmission

Low Power Idle should be indicated with the Idle Control Character 0x06 set on all 8 lanes.
15.7 Link Fault Signaling

In 40Geth and 50Geth modes of operation, Link Fault status is indicated in an 8 byte Sequence
(Table 20) and in 10Geth and 25Geth modes of operation, Link Fault status is indicated in a 4 byte
Sequence (Table 21).
In 40Geth and 50Geth modes, on the XLGMII interface, a Sequence should be received from the
MAC as a 0x9C control character on Lane 0 and data characters on Lanes 1 through 7 (see IEEE
802.3, 81.3.4).
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Table 20: 40Geth and 50Geth XLGMII Link Fault Sequences (Clause 82)
Lane 0 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7

Description
xlgmii_rxc=
xlgmii_rxc=0
1
0x9C
0x00 0x00 0x01 0x00 0x00 0x00 0x00 Local Fault
(Sequence)
0x9c
0x00 0x00 0x02 0x00 0x00 0x00 0x00 Remote Fault
(Sequence)
In 10Geth and 25Geth mode, n the XLGMII interface, a Sequence should be received as a 0x9C
control character on Lane 0 or Lane and data characters on Lanes 1 through 3 or Lanes 5 through
7 (see IEEE 802.3, 46.3.4).
Table 21: 10Geth and 25Geth XGMII Link Fault Sequences (Clause 49)
Lane 0/4 Lane 1/5 Lane 2/6 Lane 3/7 Description
xlgmii_rxc=1 xlgmii_rxc=0
0x9C
0x00 0x00 0x01 Local Fault
(Sequence)
0x9c
0x00 0x00 0x02 Remote Fault
(Sequence)
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16 Energy Efficient Ethernet (EEE)
16.1 Overview
The IEEE P802.3bj amendment defines procedures to implement Energy Efficient Ethernet. It
allows end stations to exchange a so-called low power idle (LPI) sequence to indicate the link is
not used and may be allowed to power down.
Note: EEE support is available only in 10Geth and 40Geth over 4 lanes (Only) modes. In all
modes only fast-wake should be used as deep-sleep is not supported due to the multi-channel
architecture.
16.2 LPI signaling with XLGMII

When operating in 40Geth or 10Geth modes, low power idle (LPI) sequences are encoded on the
XLGMII using the 0x06 control code (instead normal 0x07 idle) in all lanes.
low power idle indication
cgmii_c(7:0) 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
cgmii_d(63:0) Idle LPI LPI LPI Idle Idle
Figure 18: Low Power Idle Indication on XLGMII
Note:
Detection of low power idle occurs only if all lanes contain only the LPI control characters.
16.3 Application Interface Overview

For supporting applications that want to take advantage of Energy Efficient Ethernet (EEE)
functionality (IEEE P802.3bj) several control signals are available that need to interface with an
external application module to control available power modes of the link (technology specific).
Table 22: Control Signals Description/Coding
Control Signal Description/Coding
Boolean variable controlling the wake mode for the LPI transmit
and receive functions. This variable is set true when the link is to
use the fast wake mechanism, and false when the link is to use the
EEE Control&Capability optional deep sleep mechanism for each direction. This variable
Register fast-wake mode defaults true and may only be set to false if the optional deep sleep
bit mode is supported.
Note: The multi-channel Mapper cannot support deep sleep and
the application should only consider fast-wake operation.
tx_lpi_mode(1:0) A variable reflecting state of the LPI transmit function as described
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by the LPI transmit state diagram (Figure 82-16/Figure 49-12).

When tx_mode is set to QUIET the sublayer may go into a low
power.
Coding:
0: DATA
1: QUIET
2: ALERT
A variable reflecting state of the LPI transmit function as described
by the LPI transmit state diagram (Figure 82-16/49-12). When
tx_mode is set to QUIET the sublayer may go into a low power.
Coding:
0: TX_ACTIVE
1: TX_SLEEP
tx_lpi_state(2:0) 2: TX_QUIET
3: TX_ALERT
4: TX_WAKE (Clause 82 only)
5: TX_WAKE2 (Clause 82 only)
6: TX_SCR_BYPASS
Note: tx_lpi_state is informal only and should not be used for
controlling any system function.
A variable reflecting state of the LPI receive function as described
rx_lpi_mode by the LPI receive state diagram (Figure 82-17/49-13).The
parameter has one of two values: DATA(0) and QUIET(1).
A variable reflecting state of the LPI SM as described by the LPI
transmit state diagram (Figure 82-17 when Clause82 is enabled,
Figure 49-13 when Clause 49 is enabled).
Coding:
0: RX_ACTIVE
1: RX_TIMER (Clause 82 only)
2: RX_SLEEP
rx_lpi_state(2:0)
3: RX_FW (Clause 82 only)
4: RX_QUIET
5: RX_WAKE
6: RX_WTF (Clause 82 only)
7: RX_LINK_FAIL (Clause 82 only)
Note: rx_lpi_state is informal only and should not be used for
controlling any system function.
A Boolean variable that is set to true when the receiver is in a low
rx_lpi_active power state and set to false when it is in an active state and
capable of receiving data.
Note 1: To be able to transmit the sequences, the PCS must not be within an auto-negotiation
phase. Hence auto-negotiation must be either completed, or disabled.
Note 2: Deep sleep mode is not supported in any mode.
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17 Test Patterns
17.1 Test Pattern Generator

When the transmit channel is operating in test-pattern mode, it sends the test pattern in 20
separate data streams (for 100GBASE-R) of test pattern at a time via the PMA Service Interface.
The test-pattern generator shall be implemented.
There is a single type of required PCS transmit test pattern: pseudo-random (see 82.2.11 in [1]).
The pseudo-random test-pattern mode is suitable for receiver tests and for certain transmitter
tests.
When pseudo-random pattern is selected, the test pattern is generated by the scrambler. No
seeding of the scrambler is required during test pattern operation. The input to the scrambler is a
control block (block type=0x1e) with all idles. Note that the alignment markers are also added to
the stream so that the receive PCS can align and deskew the lanes.
64/66b Decoder
MLD Receive
De-
scrambler
Test Pattern
Monitoring
Checker
Error (82.2.17)
Counter
Test Pattern
Generator
(82.2.10)
data pattern
MLD Transmit
64/66b Coder
Scrambler
Figure 19: Test Pattern Generation / Check Overview
When the receiver operates in test pattern mode, the receive state-machine is disabled and the
PCS produces local fault sequences onto CGMII. As the test pattern checker is permanently
monitoring the incoming blocks, it will increment the error counter during normal operation.
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17.2 Test Pattern Checker

When the receive channel is operating in test pattern mode, the test pattern checker checks the
bits received at the descrambler output.
The pseudo-random test-pattern checker utilizes the PCS lane lock state diagram, the alignment
marker state diagram, the PCS deskew state diagram and the descrambler operating as they do
during normal data reception.
The BER monitor state diagram is disabled during receive test-pattern mode. When align_status is
true and the pseudo-random receive test-pattern mode is active, the pseudo-random test-pattern
checker observes the output from the descrambler.
When the output of the descrambler is the all idle pattern, a match is detected. When operating in
pseudo-random test pattern, the test-pattern error counter counts blocks with a mismatch. Any
mismatch indicates an error and shall increment the test-pattern error counter.
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18 Gearbox
The gearbox adapts between the 66-bit width of the blocks and the n-bit width of the PMA
interface. It receives the 66-bit blocks and produces n-bit blocks that are then transferred on the
PMA Service Interface (see Figure 1). When the transmit channel is operating in normal mode, the
gearbox sends n bits that are fully packed with bits. For example, with a 40-bit PMA interface, if
one block happened to start with the sync header on bits 0 and 1 of a transferred word, then the
last two bits of that block would be on bits 24 and 25 of the next transfer, and the next block would
begin with a sync header on bits 26 and 27 of that transfer.
The internal data path width between the PCS and PMA is an implementation choice. Depending
on the path width, the gearbox functionality may not be necessary.
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19 SerDes Interface
19.1.1 Serialization Bit Ordering
The Core implements a parallel Serdes interfaces. The following gives 40-bit implementations,
which can be extrapolated to other sizes accordingly.
On transmit, and to ensure proper data reception of the remote node, the least significant bit (LSB)
of the transmit bus (sdX_tx(0)) must be serialized first by the Serdes, the most significant bit
(MSB) of the Core output bus must be serialized last.
On Receive, the Serdes must de-serialize the first received bit into the least significant bit (LSB)
and the last bit into the most significant bit (MSB).
sd_tx(N:0)
39 0
Serialization
Serial Stream
sd_rx(N:0)
39 0
De-Serialization
Serial Stream
Figure 20: Serdes Serialization/De-serialization Overview
When the input pin sd_n2 is asserted (1), the interface changes to a half-wide (20-bit) interface.
Then only the lower 20 bits (19:0) are relevant and the upper half is ignored on receive and may
present arbitrary data on transmit. The clock frequency must then also be doubled accordingly.
19.1.2 Clock-Enable based Serdes Interface Rate Control
When the synchronous design variant is used (see 12.1.2 page 44), the serdes interfaces all
operate with the same common reference clock (ref_clk) as the complete design. Then the serdes
rates are controlled by an enable based scheme.
The following figure shows a timing example for a clock-enable based serdes interface. During a
hold cycle the data on the interface must be ignored. The distance and amount of hold cycles
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depends on the data rate to clock frequency relation. However care should be taken to spread the
hold cycles to avoid unnecessary bursts.
hold hold
sd_tx_clk *** ***
sdN_tx(*) *** 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 * * *
sd_tx_clk_ena
Figure 21: Serdes Interface Clock-Enable Timing Example
The example shows the tx interface but the same scheme applies to every rx interface where each
lane has its own individual clock enable (which may change at different times individually per lane).
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20 Host Processor Interface

The Core implements a generic host interface allowing direct access to all registers.
There are two separate host interfaces to access PCS registers separately from RS-FEC registers.
This allows e.g. merging of the RS-FEC registers with a PMA register space when creating a
management architecture following the Clause 45 MDIO organization of devices (RS-FEC at 1.200
.. 1.269).
20.1 Overview
Device configuration and control registers are accessed through a generic processor interface.
The interface implements a 16-Bit processor interface, which can be connected to various industry
standard processors.
20.2 Register Write

To write a device register, the host processor selects the device by putting the register number on
the reg_addr(15:0) pins, the write data on the reg_din(15:0) pins, and asserting
reg_wren. Data and address must be kept stable until the core acknowledges by de-asserting
reg_busy.
reg_clk
reg_wren
reg_rden
reg_addr() 0000 <address> 00
reg_din() 0000 <write data> 00000000
reg_dout() 0000
reg_busy
Figure 22: Register Write
20.3 Register Read

To read a device register, the host processor selects the device by putting the register number on
the reg_addr(15:0) pins, and asserting reg_rden. When data is available, the core de-asserts
reg_busy and the processor must read the data on the rising edge when reg_busy is de-
asserted.
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reg_clk
reg_wren
reg_rden
reg_addr() 0000 <address> 00
reg_din() 00000000
reg_dout() 0000 data 00
reg_busy
Figure 23: Register Read
Note: above given figures are examples of the interface. The deassertion of reg_busy can vary by a few
clock cycles.
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21 Memory Read/Write Interfaces

The following figures illustrate the expected behavior of a memory used at any place within the
Core.
21.1 Write Interface
xxx_clk
xxx_wren
xxx_clk
xxx_waddr(n:0)
xxx_wren
xxx_wdata(k:0)
xxx_waddr(n:0)
xxx_wdata(k:0)
Data Write
Data Write
Figure 24: Memory Write Interface
21.2 Read Interface
xxx_clk
rclk
xxx_rden
xxx_raddr(n:0) A1 A2 A3
xxx_raddr(n:0)
xxx_rdata(k:0) D1 D2 D3
xxx_rdata(k:0)
xxx_rden
Figure 25: Memory Read Interface
The output read data is expected to be stable the clock cycle following rden assertion or a change
of raddr (while rden is maintained). When rden becomes deasserted, the memory output must be
stable with the last data read.
The rden signal to the memory is typically coming from a combinatorial and hence should not be
highly loaded (timing).
21.3 Read/Write to same Address

The implementation does not expect to read and write to the same address at any time. However,
the address pointers will point to the same address whenever a FIFO is empty. At this time read
data is not expected to be valid.
During that condition however it must be guaranteed, that a write (wren assertion) will store the
data properly, while at the same time the read data output is allowed to be undefined.
.
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22 Core Registers
22.1 100G PCS Register Map

All registers are 16-Bit registers. The register address on pins reg_addr(15:0) is addressing
the register (i.e. the value given in column REG# in the table below must be given here).
Bit 0 is the least significant bit and all registers are initialized to zero upon reset except when
stated otherwise.
The following register types are used:
 RW: Read/write register. Unused bits should be written with 0 and ignored on read.
 RO: Read only, write has no effect.
 WO: Write only, returns all zero on read.
 ROR: Read only and Reset. The value is reset to zero after reading the register.
 LH: Latch high. Bit stays 1 if event occurred. Latch is cleared after reading the register.
 LL: Latch low. Bit stays 0 if event occurred. Latch is cleared after reading the register.
 SC: Self-clearing.
 NR: Non Roll-over.
Table 23: Register Map

Reg Reg# Reset
Register Name Type Description
# (hex) value
Control/Status
15: Reset. 1=PCS reset, 0=normal operation. (SC)

14: Loopback. 1=Enable loopback, 0=disable loopback.
13: Speed selection. (13,6)=11=bits 5:2 select speed.
12: Reserved. Always 0, writes ignored.
11: Low power. 1=Low power mode, 0=normal
operation.
10:7: Reserved. Always 0, writes ignored.
0 00 CONTROL 1 RW 5:2: Speed selection: 0100 = 100 Gb/s 0x2050
Notes:
 Only bits 15,14 are writeable. All others are read-
only.
 Bits (13,6:2) are fixed.
 Bit 11 is not available and always 0.
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15:8: Reserved
7: Fault. 1=Fault condition detected, 0=no fault
condition detected. This indication is the logical OR of
Status 2 Register bits 10 and 11.
1 01 STATUS 1 RO 6:3: Reserved 0
2: Receive link status. 1=Link up, 0=link down. (LL)
1: Low power ability. always 0=low power mode not
supported.
0: Reserved
2 02 DEVICE ID0 RO Bits 15:0 of Device Identifier. Always 0. 0
3 03 DEVICE ID1 RO Bits 31:16 of Device Identifier. Always 0. 0
15:9 Reserved
8: 100G capable
7: 40G capable
6:2: Reserved
4 04 SPEED ABILITY RO
1: 10PASS-TS/2Base-TL capable
0x0100
0: 10G capable
Note: Only bit 8 is set for 100GBase-R.
15:7: Reserved
6: TC present
5: DTE XS present
DEVICES IN 4: PHY XS present
5 05 PKG1
RO
3: PCS present (default: 1)
0x0008
2: WIS present
1: PMD/PMA present
0: Clause 22 registers present
15: Vendor specific device 2 present

DEVICES IN 14: Vendor specific device 1 present
6 06 PKG2
RO
13: Clause 22 extension present
0
12:0: Reserved

2:0: PCS type selection.
101: Select 100GBase-R PCS type
011: Select 10GBase-T PCS type
7 07 CONTROL 2 RO
010: Select 10GBase-W PCS type
0x0005
001: Select 10GBase-X PCS type
Note: Bits 2:0 are fixed to 101 for 100GBase-R.
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15:14: Device present. 10=device responding at this

address.
13:12: Reserved
11: Transmit fault. 1=Fault condition on transmit path.
(LH)
10: Receive fault. 1=Fault condition on receive path.
(LH)
9:6: Reserved
5: 100GBase-R capable
8 08 STATUS 2 RO
0x8020
3: 10GBase-T capable
2: 10GBase-W capable
1: 10GBase-X capable
Notes:
 Bits 5:0 are fixed to 100000 for 100GBase-R.
 Bits 11,10 are not relevant and always 0
9- 09 -
Reserved 0
13 0d
14 0e PKG ID0 RO Bits 15:0 of Package Identifier. Always 0. 0
15 0f PKG ID1 RO Bits 31:16 of Package Identifier. Always 0. 0
16 - 10 -
Reserved 0
31 1F
15:13: Reserved
12: Receive link status. 1=Link up, 0=link down.
BASE-R
32 20 STATUS 1
RO 11:2: Reserved 0
1: High BER. 1=PCS reporting a high BER.
0: Block lock. 1=PCS locked to received blocks.
15: Latched block lock. (LL)
14: Latched high BER. (LH)
13:8: BER counter. (NR)
7:0: Errored blocks counter. (NR)
BASE-R
33 21 STATUS 2
ROR Note: clear of counters and latches can take several 0
reg_clk cycles after the register has been read (clock
domain crossing into cgmii_rx_clk).
Note: the BER counter is updated only once every BER
measurement period.
34 - 22 -
Reserved 0
41 29
15:8: Reserved
BASE-R TEST
42 2a CONTROL
RW 7: Scrambled idle test-pattern enable. 0
6:0: Reserved
BASE-R TEST
43 2b ERR CNT
ROR Test-pattern error counter. (NR) 0
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BER HIGH
44 2c ORDER CNT
RO 15:0: Bits 21:6 of BER counter. (NR) 0
15: High order counter present. Always 1, writes

ERR BLK HIGH ignored.
45 2d ORDER CNT
RO
0x8000
13:0: Bits 21:8 of errored blocks counter. (NR)
46 - 2e -
Reserved 0
49 31
15:13: Reserved
12: Lane alignment status. 1=All Receive lanes locked
and aligned.
11:8: Reserved
7: Lane 7 block lock
MULTI-LANE
50 32 ALIGN STATUS RO
5: Lane 5 block lock (also 1-lane modes lane 1)
0
1
15:12: Reserved
MULTI-LANE 7: Lane 15 block lock (also 1-lane modes lane 3)
51 33 ALIGN STATUS RO 6: Lane 14 block lock 0
2 5: Lane 13 block lock
15:8: Reserved
7: Lane 7 alignment marker lock
MULTI-LANE 5: Lane 5 alignment marker lock
52 34 ALIGN STATUS RO 4: Lane 4 alignment marker lock 0
3 3: Lane 3 alignment marker lock
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15:12: Reserved
53 35 ALIGN STATUS RO 6: Lane 14 alignment marker lock 0
4 5: Lane 13 alignment marker lock
54 - 36 -
Reserved 0
199 c7
BIP ERR CNT

200 c8 ROR BIP error counter lane 0 (NR) 0
LANE 0
BIP ERR CNT

201 c9 ROR BIP error counter lane 1 (NR) 0
LANE 1
BIP ERR CNT

202 ca ROR BIP error counter lane 2 (NR) 0
LANE 2
BIP ERR CNT

203 cb ROR BIP error counter lane 3 (NR) 0
LANE 3
BIP ERR CNT

204 cc ROR BIP error counter lane 4 (NR) 0
LANE 4
BIP ERR CNT

205 cd ROR BIP error counter lane 5 (NR) 0
LANE 5
BIP ERR CNT

206 ce ROR BIP error counter lane 6 (NR) 0
LANE 6
BIP ERR CNT

207 cf ROR BIP error counter lane 7 (NR) 0
LANE 7
BIP ERR CNT

208 d0 ROR BIP error counter lane 8 (NR) 0
LANE 8
BIP ERR CNT

LANE 9
BIP ERR CNT

LANE 10
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BIP ERR CNT

LANE 11
BIP ERR CNT

LANE 12
BIP ERR CNT

LANE 13
BIP ERR CNT

LANE 14
BIP ERR CNT

LANE 15
BIP ERR CNT

LANE 16
BIP ERR CNT

LANE 17
BIP ERR CNT

218 da ROR BIP error counter lane 18 (NR) 0
LANE 18
BIP ERR CNT

219 db ROR BIP error counter lane 19 (NR) 0
LANE 19
220
dc-
- Reserved
18f
399
LANE 0 15:6: Reserved

400 190 RO 0
Mapping 5:0: Lane 0 mapping
401 191 RO 0
402 192 RO 0
403 193 RO 0
404 194 RO 0
405 195 RO 0
406 196 RO 0
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407 197 RO 0
408 198 RO 0
409 199 RO 0
410 19a RO 0
411 19b RO 0
412 19c RO 0
413 19d RO 0
414 19e RO 0
415 19f RO 0
416 1a0 RO 0
417 1a1 RO 0
418 1a2 RO 0
419 1a3 RO 0
420
- 1a4..
Reserved
327 7fff
67
Vendor Specific Registers
Scratch Register. Register address to test read and

32768 8000 SCRATCH RW 0
write operation. MoreThanIP Specific Register.
CORE_
32769 8001 RO Always 0. 0
REVISION
A 16-bit value defining the amount of data between
markers. (I.e. distance of markers-1)
32770 8002 VL_INTVL RW Following values are valid: 63, 255, 1023, 16383. 16383
The value 16383 is the IEEE standard distance when
operating in 100G.
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Per lane a 4-bit value to define the transmit line

decoupling FIFOs almost full threshold.
Bits 3:0: serdes lane 0
Valid values are 4..9.
Lower values result in lower latency but require a
higher system clock (ref_clk) to avoid the risk of buffer
TX_LANE_ underflows that would lead to transmit data corruption.
32771 8003 RW 0x9999
THRESH If a too low value is set and a FIFO underflow occurs
the PCS Status 2 register bit 11 (tx error) is set.
Note: when the Transmit FIFOs experience
over/underflow they are automatically resetting itself.
Note: the register is relevant only if the PCS Core
configuration implements a (possibly external) serdes
line decoupling FIFO that supports this feature. The
setting has no effect otherwise.
Note: the setting affects the FIFOs at all times, not only
when the PCS100 is active. Individual settings may be
used when lanes are used at different rates.
32772
8004..
.. reserved RO 0
32783 800f
32784 8010 PCS_MODE RW PCS options configuration. See Table 24 page 76. 0
Marker pattern for PCS Virtual Lane 0. A marker is

32832 8040 VL0_0 RW defined by 3 bytes m0, m1, m2. 0x68c1
Bits 7:0 = m0 (0xC1), Bits 15:8 = m1 (0x68)
Last byte of PCS Virtual Lane 0 marker pattern.
32833 8041 VL0_1 RW 0x21
Bits 7:0 = m2 (0x21)
Marker pattern for PCS Virtual Lane 1.

32834 8042 VL1_0 RW 0x719D
Bits 7:0 = m0 (0x9D), Bits 15:8 = m1 (0x71)

32835 8043 VL1_1 RW 0x8E
Bits 7:0 = m2 (0x8E)

32836 8044 VL2_0 RW 0x4B59
Bits 7:0 = m0 (0x59), Bits 15:8 = m1 (0x4B)

32837 8045 VL2_1 RW 0xE8
Bits 7:0 = m2 (0xE8)

32838 8046 VL3_0 RW 0x954D
Bits 7:0 = m0 (0x4D), Bits 15:8 = m1 (0x95)
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32839 8047 VL3_1 RW 0x7B
Bits 7:0 = m2 (0x7B)

32840 8048 VL4_0 RW 0x07F5
Bits 7:0 = m0 (0xF5), Bits 15:8 = m1 (0x07)

32841 8049 VL4_1 RW 0x09
Bits 7:0 = m2 (0x09)
see
32842 804A VL5_0/1
802.3
.. .. .. RW Marker patterns for lanes 5..19. Two registers per
32871 8067 marker. Table
VL19_0/1
82-2
22.1.1 100G PCS Vendor PCS_MODE Register (32784)
Note: This Register definition applies to the 100G PCS only.

Table 24: PCS Vendor PCS_MODE Register
Reset
Bits Name Description Type
Value
3:0 reserved unused 0 RW
MAC Interface Burst limit configuration.

When cleared (0) the PCS uses a 4-on pattern at the
cgmii interface's cgmii_rxclk_ena and
cgmii_txclk_ena. That is, it limits the maximum
burst length to 4 clock cycles at the MAC interfaces.
This is the default and should be used. It requires a
4 BURST_5 reference clock frequency of 652MHz or higher. 0 RW
When enabled (1) the PCS uses a 5-on pattern.
Hence the maximum burst length is increased to 5
clock cycles. This would allow a reduced reference
clock minimum of 645MHz instead 652MHz. This
requires corresponding support within the attached
100G MAC. Use with care and only if it is sure the
MAC supports this extended burst pattern.
15:5 reserved unused
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22.2 10G..50G PCS Register Map

The following table lists the Register map for the PCS on each of the Channels 0..3. Note that
multi-lane registers apply only for Channels 0 and 2 if they operate in a multi-lane mode of
operation.
Table 25: Register Map
Reg# Register Reset
Reg# Type Description
(hex) Name Value
Control/Status
15: Reset. 1=PCS reset, 0=normal operation. (SC)
14: Loopback. 1=Enable loopback, 0=disable loopback.
11: Low power. 1=Low power mode, 0=normal operation.
5:2: Speed selection: 0101=25G; 0011=40G; 0000=10G

0 00 CONTROL 1 RW 0x2040
Notes:
 Only bits 15,14 are writeable. All others read-only.
 Bits (13,6) are fixed.
 Bit 11 is not available and always 0.
 Bits 5:2 read the speed derived from settings in
register PCS_MODE or its corresponding mode
configuration pins. 25G is indicated when HiBer25 is
set. 10G is indicated if not 25G and MLD is disabled.
All other settings default to 40G. Write has no effect.
PCS status.
1 01 STATUS 1 RO
See Table 26 page 83.
0
2 02 DEVICE ID0 RO Always 0. 0
3 03 DEVICE ID1 RO Always 0. 0
15:5 Reserved
CH0,2:
4: 25G capable
0x0015
SPEED 3: 100G capable
4 04 ABILITY
RO
2: 40G capable
CH1,3:
1: 10PASS-TS/2Base-TL capable
0x0011
0: 10Geth capable
15:7: Reserved
6: TC present
5: DTE XS present
DEVICES IN 4: PHY XS present
5 05 PKG1
RO
3: PCS present (default: 1)
0x0008
2: WIS present
1: PMD/PMA present
0: Clause 22 registers present
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15: Vendor specific device 2 present

DEVICES IN 14: Vendor specific device 1 present
6 06 PKG2
RO
13: Clause 22 extension present
0
12:0: Reserved

2:0: PCS type selection.
011: Select 10GBase-T PCS type
7 07 CONTROL 2 RW 010: Select 10GBase-W PCS type 0x0000
001: Select 10GBase-X PCS type
The register is not writeable. The read value reflects the

mode resulting from vendor register PCS_MODE or pin
configurations if possible.
15:14: Device present. 10=device responding at this
address.
13:12: Reserved
11: Transmit fault. 1=Fault condition on transmit path.
(LH)
10: Receive fault. 1=Fault condition on receive path. (LH)
9:8: Reserved
6: reserved
7: 25GBase-R capable CH0,2:
6: Reserved 0x8091
8 8 STATUS 2 RO 5: 100GBase-R capable
4: 40GBase-R capable CH1,3:
3: 10GBase-T capable 0x8081
2: 10GBase-W capable
1: 10GBase-X capable
Notes:
 Bit 11 can indicate serdes interface decoupling buffer
over/underflow occurences if such buffer exists in the
implementation.
 Bit 10 is not relevant and always 0
9 - 13 9 - 0D Reserved 0
Bits 15:0 of Package Identifier defined by parameter

14 0E PKG ID0 RO
PACK_IDENTIFIER in PCS package file.
0
Bits 31:16 of Package Identifier defined by parameter

15 0F PKG ID1 RO
PACK_IDENTIFIER in PCS package file
0
16 - 10 –
Reserved 0
19 13
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15:12 : Reserved
11: 25GBASE-R deep sleep supported if 1 (RO)
10: 25GBASE-R fast wake supported if 1 (RO)
9: 40GBASE-R deep sleep supported if 1 (RO)
8: 40GBASE-R fast wake supported if 1 (RO)
7: reserved
6: 10GBASE-KR EEE support (RO) CH0,2:
1 = EEE is supported for 10GBASE-KR 0x0541
EEE control RO,
20 14 and capability RW 0 = EEE is not supported for 10GBASE-KR
5..1: n.a., all 0 CH1,3:
0: LPI_FW (RW) 0x0440
1 = Fast wake mode is used for LPI function
0 = Deep sleep is used for LPI function
Note: Bit 0 can be set in any mode disabling the EEE
statemachines. Even for 10G then it is possible to
transfer LPI sequences without powering down the PCS.
21 15 Reserved 0
A counter that is incremented each time that the LPI

Wake_error_ ROR receive state diagram enters the RX_WTF state
22 16 counter NR indicating that a wake time fault has been detected.
0
The counter saturates at 0xffff and is cleared upon read.
17
23-31 - Reserved 0
1F
15:13: Reserved
12: Receive link status. 1=Link up, 0=link down.
BASE-R
32 20 STATUS 1
RO 11:2: Reserved 0
1: High BER. 1=PCS reporting a high BER.
0: Block lock. 1=PCS locked to received blocks.
15: Latched block lock. (LL)

14: Latched high BER. (LH)
BASE-R 13:8: BER counter. (NR)
33 21 STATUS 2
ROR
7:0: Errored blocks counter. (NR)
0
Note: clear of counters and latches can take several
reg_clk cycles after the register has been read.
10GBase-R Test Pattern Seed A: Bits 15:0.

34 22 SEED A 0 RW 0x804F
Note: Default value see IEEE 802.3 Table 52-20.
35 23 SEED A 1 RW 10GBase-R Test Pattern Seed A: Bits 31:16. 0xCAB6
36 24 SEED A 2 RW 10GBase-R Test Pattern Seed A: Bits 47:32. 0xB44D
10GBase-R Test Pattern Seed A: Bits 57:48.

37 25 SEED A 3 RW 0x3C8
Bits 15:10 are unused.
10GBase-R Test Pattern Seed B: Bits 15:0.

38 26 SEED B 0 RW 0x8884
Note: Default value see IEEE 802.3 Table 52-20.
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39 27 SEED B 1 RW 10GBase-R Test Pattern Seed B: Bits 31:16. 0x85A3
40 28 SEED B 2 RW 10GBase-R Test Pattern Seed B: Bits 47:32. 0x06BB
10GBase-R Test Pattern Seed B: Bits 57:48.

41 29 SEED B 3 RW 0x349
Bits 15:10 are unused.
15:8: Reserved.
7: Select Random Idle test pattern (40G)
6:4: reserved
3: Transmit test-pattern enable.
2: Receive test-pattern enable.
1: Select Square Wave (1) or Pseudo Random (0) test
pattern.
0: Data Pattern Select: 1=all Zero, 0=2x Local Fault.
BASE-R TEST
42 2A CONTROL
RW 0
Notes:
 To enable test patterns Bits 2,3 need to be set.
 Pattern select Bit 7 takes precedence over Bits 1,0.
When set, the Bits 0,1 settings are ignored.
 Bits 0,1 are for 10Geth mode of operation affecting
only lane 0.
 Bit 1 (Square Wave) is only a transmitter test and
affects only lane 0.
BASE-R TEST
43 2B ERR CNT
ROR Test-pattern error counter. (NR) 0
BER HIGH
44 2C ORDER CNT
RO 15:0: Bits 21:6 of BER counter. (NR) 0
ERR BLK 15: High order counter present. Always 1, writes ignored.
45 2D HIGH ORDER RO 14: Reserved. Always 0, writes ignored. 0x8000
CNT 13:0: Bits 21:8 of errored blocks counter. (NR)
46 - 2E -
Reserved 0
49 31
15:13: Reserved
12: Lane alignment status. 1=All Receive lanes locked
and aligned.
11:4: Reserved
MULTI-LANE
50 32 ALIGN RO
0
STATUS 1
Note: Bits 3:0 are relevant only on Channels 0 and 2
when operating in 40/50G mode.
MULTI-LANE
51 33 ALIGN RO reserved 0
STATUS 2
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15:4: Reserved
52 34 ALIGN RO 2: Lane 2 alignment marker lock 0
STATUS 3 1: Lane 1 alignment marker lock
MULTI-LANE
53 35 ALIGN RO reserved 0
STATUS 4
54 - 36 –
Reserved 0
199 C7
BIP ERR CNT

200 C8 ROR BIP error counter lane 0 (NR) 0
LANE 0
BIP ERR CNT

201 C9 ROR BIP error counter lane 1 (NR) 0
LANE 1
BIP ERR CNT

202 CA ROR BIP error counter lane 2 (NR) 0
LANE 2
BIP ERR CNT

203 CB ROR BIP error counter lane 3 (NR) 0
LANE 3
204 CC
BIP ERR CNT
.. .. ROR reserved 0
LANE 4 .. 19
219 DB
220- DC-
Reserved 0
399 18F

400 190 RO 0
401 191 RO 0
402 192 RO 0
403 193 RO 0
404 194
LANE 4 .. 19
.. .. RO reserved. 0
Mapping
419 1A3
1A4
420-
.. Reserved 0
32767
7FFF
Vendor Specific Registers
Scratch Register. Register address to test read and write

32768 8000 SCRATCH RW 0
operation
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CORE_
32769 8001 RO Always 0. 0
REVISION
A 16-bit value defining the amount of data between
markers. (I.e. distance of markers-1)
Following values are valid:
FEC91 not enabled: (64*n)-1; 63, 1023, 16383.
FEC91 enabled: (80*n)-1; 159, 1279, 20479.
The value 16383 is the IEEE standard distance when
operating in 40G. The value 20479 is standard for
25G/50G modes operating with RS-FEC.
The setting from each PCS applies to a single lane only
(PCS0 to lane 0, PCS1 to lane 1, ...) and does not CH0,2:
consider the mode of operation. That is, when 40G mode 16383
32770 8002 VL_INTVL RW over 4 lanes is active, all the four VL_INTVL of PCS0..3
must be initialized to the same value. When a PCS CH1,3:
operates in 50G mode, the corresponding VL_INTVL of 20479
PCS0,1 or PCS2,3 must be set to the same value.
When the 100G PCS is active none of the PCS0..3
settings have an effect, but instead the 100G PCS has its
own VL_INTVL register, which then applies to all lanes.
Note: The application is responsible for initialization of
the correct setting when the operational mode changed.
In addition, when values less 16383 are set, it also
configures the internal hi-ber timer to operate with a
shorter window of 12.5µs instead 1.25ms (Clause 82) or
125µs (Clause 49).
Bits 3:0: A 4-bit value to define the transmit line
decoupling FIFOs almost full threshold. Valid values are
4..9.
Lower values result in lower latency but require a higher
system clock (ref_clk) to avoid the risk of buffer
TX_LANE_ underflows that would lead to transmit data corruption.
32771 8003 RW 7
THRESH If a too low value is set and a FIFO underflow occurs the
PCS Status 2 register bit 11 (tx error) is set.
Note: when the Transmit FIFOs experience
over/underflow they are automatically resetting itself.
Note: Not used. Threshold settings should be done in the
100G PCS TX_LANE_THRESH.
This register is unused in this implementation. RXLAUI CH0,2:
modes are configured with the configuration pins 0x0D80
RXLAUI_
32772 8004 RW rxlaui_ena_in0/2 (see 5 page 24).
CONFIG
Note: Exists only for Channels 0 and 2. Bits 11:0 are CH1,3
writeable but have no effect on any function. 0
32773 8005
.. .. reserved RO 0
32775 8007
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Marker pattern for PCS Virtual Lane 0. A marker is CH0,2:

defined by 3 bytes m0, m1, m2. 0x7690
32776 8008 VL0_0 RW Bits 7:0 = m0 (0x90 or 0xC1), Bits 15:8 = m1 (0x76 or
0x68) CH1,3:
see also 8.2 page 34 for mode specific settings 0x68C1
CH0,2:
0x47
32777 8009 VL0_1 RW
Bits 7:0 = m2 (0x47 or 0x21) CH1,3:
0x21

32778 800a VL1_0 RW 0xC4F0
Bits 7:0 = m0 (0xF0), Bits 15:8 = m1 (0xC4)

32779 800b VL1_1 RW 0xE6
Bits 7:0 = m2 (0xE6)

32780 800c VL2_0 RW 0x65C5
Bits 7:0 = m0 (0xC5), Bits 15:8 = m1 (0x65)

32781 800d VL2_1 RW 0x9B
Bits 7:0 = m2 (0x9B)

32782 800e VL3_0 RW 0x79A2
Bits 7:0 = m0 (0xA2), Bits 15:8 = m1 (0x79)

32783 800f VL3_1 RW 0x3D
Bits 7:0 = m2 (0x3D)
CH0,2:
Configure PCS supporting Clause 49 or Clause 82
0x303
Encoder/Decoder, MLD functionalities for multi-lane
32784 8010 PCS_MODE RW
support and single lane operation.
CH1,3:
see Table 27 page 84. 0x301
22.2.1 PCS status 1 Register (1)
Table 26: PCS status 1 Register

Reset
Bits Register Name Description Type
Value
0 Reserved Bits always set to ‘0’. 0 RO
Set to ‘1’ to indicate that the PCS implements a low

power mode.
1 Low-power Ability Note: this bit does not refer to Energy Efficient Ethernet 1 RO
(EEE). It only indicates that the control bit 11 in the PCS
Control register 1 is supported and allows to place the
PCS in a reset state.
When set to ‘1’, indicates that the PCS receive link is up.
PCS Receive Link
2 When set to ‘0’, indicates that the PCS receive link is or 0 RO, LL
Status
was down (latching low).
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6:3 Reserved Bits always set to ‘0’. 0 RO
When set to ‘1’, indicates that a fault condition is

detected. When set to ‘0’, indicates that no fault condition
7 Fault is detected. 0 RO
This indication is the logical OR of PCS Status 2 Register
bits 10 and 11.
1: receive is currently in LPI state (EEE).
8* RX_LPI_ACTIVE 0 RO
0: normal operation.
1: transmit is currently in LPI state (EEE).

9* TX_LPI_ACTIVE 0 RO
1: receive is or was in LPI state (EEE).

10* RX_LPI 0 RO, LH
1: transmit is or was in LPI (EEE).

11* TX_LPI 0 RO, LH
15:12 Reserved Bits always set to ‘0’. 0 RO
*Note: Bits 8..11 are implemented only if the Energy-Efficient-Ethernet (EEE) option is enabled in
synthesis. They are reserved (always 0) otherwise.
22.2.2 10..50G PCS Vendor PCS_MODE Register (32784)
Note: This Register definition applies only to the four Channel specific PCS modules.
Table 27: 10..50G PCS Vendor PCS_MODE Register
Reset
Bits Name Description Type
Value
When cleared (0) the PCS uses the Clause 82
encoder/decoder functions implementing XLGMII to
the MAC (i.e. 8-byte granularity).
When set (1) the PCS uses the Clause 49
0 ENA_CLAUSE49 encoder/decoder functions implementing a 64-bit 1 RW
XGMII to the MAC (i.e. 4-byte granularity).
Note: The toplevel input pcs_cl49 (if such exists) is
OR'ed with this control bit. Hence if the external
control pin should be used the register bit should be 0.
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When cleared (0) the PCS 4-lane MLD function is

active inserting/removing markers as described in 8
page 34.
When set (1) the MLD function is disabled and 66bit
encoded data are sent unmodified to the (single) lane
interface. If a FEC74 is available it can still be used. CH0,2:
The MLD function exists only for Channels 0 and 2. It 1
is always disabled (not existing) for Channels 1 and 3.
1 DISABLE_MLD RW
Note: The MLD must be disabled for single lane mode
CH1,3:
of operation (10Geth/25Geth) when the RS-FEC
should not be used. It needs to be enabled for 25G 0
with RS-FEC.
Note: The toplevel input pcs_dis_mld (if such
exists) is OR'ed with this control bit. Hence if the
external control pin should be used the register bit
should be 0.
The setting of this bit together with setting
ENA_CLAUSE49 (bit 0) determine the Hi-Ber
measurement interval for different operation modes as
below:
 HI_BER25=0, ENA_CLAUSE49=0: 1.25ms (40G,
Hi-BER error threshold 97)
2 HI_BER25 0 RW
 HI_BER25=0, ENA_CLAUSE49=1: 125µs(10G,
Hi-BER error threshold 16)
 HI_BER25=1, ENA_CLAUSE49=1: 2ms (25G, Hi-
BER error threshold 97)
 HI_BER25=1, ENA_CLAUSE49=0: undefined,
treated as both 0 (40G mode)
7:3 Reserved unused
Current status of Clause 49 setting. Returns the result

8 ST_ENA_CLAUSE49 1 RO
of the OR from the register bit and the external pin.
Current status of MLD setting. Returns the result of
9 ST_DISABLE_MLD the OR from the register bit and the external pin. 1 RO
Note: Always set for PCS of Channels 1 and 3.
15:10 reserved unused
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22.3 RS-FEC Registers

The IEEE 802.3bj Clause 91 Reed-Solomon FEC (RS-FEC) registers are accessible separately
from the PCS registers.
All registers implement 16-Bit. For multi-register values the lower 16bit must be read first (e.g.
counters, to latch the high value).
Bit 0 is the least significant bit and all registers are initialized to zero upon reset except when
stated otherwise.
The following register and bit types are used:
 RW: Read/write register. Unused bits should be written with 0 and ignored on read.
 RO: Read only, write has no effect.
 ROR: Read only and Reset. The value is reset to zero after reading the register.
 SC: Self-clearing.
 NR: Non Roll-over.
Reserved bits or registers default to 0 and are read-only if not stated otherwise.
Table 28: RS-FEC Register Map
Reg Reg# Typ

Register Name Description Reset
# (hex) e
RS-FEC Registers
Control register for enabling FEC functions.

0 00 RS-FEC CONTROL RW 0
Status register
1 01 RS-FEC STATUS RO 0x8002
ROR Counts number of corrected FEC codewords.
2 02 RS-FEC CCW_LO 0
, NR Lower 16 bit of counter. Must be read first.
ROR Counts number of corrected FEC codewords.
3 03 RS-FEC CCW_HI 0
, NR Upper 16 bit of counter.
ROR Counts number of uncorrected FEC codewords.
4 04 RS-FEC NCCW_LO 0
, NR Lower 16 bit of counter. Must be read first.
ROR Counts number of uncorrected FEC codewords.
5 05 RS-FEC NCCW_HI 0
, NR Upper 16 bit of counter.
FEC alignment status and lane mappings
6 06 RS-FEC LANEMAP RO 0
7..
7..9 reserved RO 0
9
Counts number of (corrected) 10bit symbol errors found in
RS-FEC ROR lane 0. Does increment only for correctable codewords.
10 0A 0
SYMBLERR0_LO , NR
Lower 16 bit of counter. Must be read first.
RS-FEC
11 0B ROR Upper 16 bit of counter. 0
SYMBLERR0_HI
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12 0C 0
SYMBLERR1_LO , NR
RS-FEC
13 0D ROR Upper 16 bit of counter. 0
SYMBLERR1_HI
14 0E 0
SYMBLERR2_LO , NR
RS-FEC
15 0F ROR Upper 16 bit of counter. 0
SYMBLERR2_HI
16 10 0
SYMBLERR3_LO , NR
RS-FEC
17 11 ROR Upper 16 bit of counter. 0
SYMBLERR3_HI
18.. 12..
reserved RO 0
63 3f
Another set of 8 registers for the 2nd RS-FEC channel
when it operates in multi-channel mode. It is space for the
64.. 40.. RS-FEC registers CONTROL, STATUS, CCW_LO/HI,
RS-FEC Channel 1 RW NCCW_LO/HI, LANEMAP (and 1 reserved). x
71 47
Note: The SYMBLERR registers are re-used on a per-
channel basis when not operating in 100G mode.
72.. 48..
RS-FEC Channel 2 RW Another set of 8 registers for the 3rd RS-FEC channel. x
79 4f
80.. 50..
RS-FEC Channel 3 RW Another set of 8 registers for the 4th RS-FEC channel. x
87 57
88.. 58..
reserved RO 0
127 7f
RS-FEC Vendor specific registers
RS-FEC VENDOR Additional control to enable RS-FEC operation.

128 80 RW 0
CONTROL See Table 32 page 92.
Implementation specific information that may be useful for
RS-FEC VENDOR
129 81 ROR debugging link problems. 0
INFO 1
RS-FEC VENDOR Implementation specific status information.
130 82 ROR 0
INFO 2 See Table 34 page 95.
RS-FEC VENDOR A version information taken from package file parameter
131 83 RO 0x22
REVISION FEC91_DEV_VERSION
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Bits 7:0. Must be written with the 8-bit value of 0x57 to

enable RS-FEC transmit test error injection capability. Any
other value will disable test abilities.
When the key is set, the transmitter supports bit error
RS-FEC VENDOR injection after the FEC encoder to allow testing a RS-FEC
132 84 RW 0
TX Test Key receiver.
Only when this register is set to the valid key, the following
registers (133..135) have an effect and become writeable.
Otherwise these registers will be cleared to all zero and
behave as a read-only register.
Bits 15:0. One bit per 10-bit Symbol to apply the pattern to.
When a bit is 1 the test pattern is applied to the
corresponding 10B symbol after the FEC encoding. Multiple
RS-FEC VENDOR RO/ bits can be set.
133 85 0
TX Test Symbols RW
The RS-FEC processes 16 10B symbols in one cycle. Bits
0..3 are 4 symbols of lane 0. Bits 4..7 are 4 symbols of lane
1, bits 8..11 lane2, bits 12..15 lane 3.
Bits 9:0. A 10-bit value which will be XORed with a 10B
symbol after the FEC encoder to manipulate the
RS-FEC VENDOR RO/ transmitted datastream. A pattern of all 0 has no effect.
134 86 0
TX Test Pattern RW
Bit 10: overwrite. If the bit is set the 10B symbol is replaced
by the pattern instead using XOR.
RS-FEC VENDOR RO/ Bit0: when written with 1 triggers the error insertion (on one
135 87 0
TX Test Trigger RW word of 16 symbols). Bit clears to 0 automatically.
136 88 reserved RO 0
137 89 reserved RO 0
Bits 5:0: RSFEC decoder channel 0 threshold to avoid

burstness of output data. A 6-bit value from 0 to 55 can be
set. A value of 51 is recommended for 25G mode of
operation to avoid bursts on channel 0. Higher values may
RS-FEC Vendor
138 8A RW be used for 50G and 100G operation in case of higher 51
DecoderThreshold0 reference clock frequencies (but not necessary).
A value of 0 disables the function causing periodic data
bursts to the PCS when using RSFEC mode.
Bits 31:6: reserved
RS-FEC Vendor
139 8B RW operation to avoid bursts on channel 1. 51
DecoderThreshold1 A value of 0 disables the function causing periodic data
Bits 31:6: reserved
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operation to avoid bursts on channel 2. Higher values may
RS-FEC Vendor
140 8C RW be used for 50G in case of higher reference clock 51
DecoderThreshold2 frequencies (but not necessary).
A value of 0 disables the function causing periodic data
Bits 31:6: reserved
RS-FEC Vendor
141 8D RW operation to avoid bursts on channel 3. 51
DecoderThreshold3 A value of 0 disables the function causing periodic data
Bits 31:6: reserved
142.. 8E..
reserved RO 0
255 ff
22.3.1 RS-FEC Control Register
Table 29: RS-FEC Control Register

Reset
value
1: Bypass the decoder's correction function for
reduced latency, accepting bit errors.
0: Normal FEC operation with correction of bit
errors (default).
0 RS-FEC Bypass Correction See 11.3 page 42 RW 0
Note: changing the bit is intrusive to the
datapath and may cause a link restart.
Note: correction bypass is not supported and
setting this bit to 1 has no effect.
1: Configure the FEC decoder to not indicate
errors to the PCS layer. May reduce latency.
0: The FEC decoder indicates errors to the
PCS layer (corrupting sync-headers). Errors
RS-FEC Bypass Error are indicated for uncorrected FEC codewords
1 RW 0
Indication or when correction is bypassed for any errors
(default).
See 11.4 page 42.
Note: changing the bit is intrusive to the
datapath and may cause a link restart.
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1: Enable RS-FEC datapath instead PCS MLD.

0: Use normal PCS MLD datapath (default).
Notes:
 The toplevel input fec91_ena_in(x) is
OR'ed with this control bit. Hence if the
external control bit should be used the
2 RS-FEC Enable register bit should be written with 0. 0
 This bit is used per serdes lane rather than
per channel. If for 100G channel the RS
FEC mode to be set, then RS-FEC bit for
all four RS-FEC control registers is to be
set. If for 50G channel over serdes lanes 0
an 1 the RS FEC mode to be set, then the
RS-FEC Enable bit of RS-FEC control
register for channel 0 and 1 is to be set.
3..7 reserved
Enable control for RS-FEC (Clause 91)

datapath per serdes lane:
1: the RS (544, 514) codewords are used.
0: the RS (528, 514) codewords are used.
Notes:
 The setting is relevant, only when RS FEC

mode for the same lane is set.
8 KP Mode Enable  The toplevel input kp_mode_in(x) is OR'ed
with this control bit. Hence if the external
control bit should be used the register bit
should be written with 0.
 This bit is used per serdes lane rather than
per channel.
 This bit is available, only when the
synthesis option to enable the RS (544,
514) support is set. This feature support is
a matter of package’s delivery agreement
and requires a file list.
The marker transcode pad bit value to use.
Defines the value for the pad bit to be used
when transcoding markers for transmit (i.e. bit
256 of the 257-bit marker word).
The bit is a compliance setting but not relevant
9 TC_PAD_VALUE for proper operation of the link. Depending on RW 0
mode of operation of the channel the following
settings should be used:
0: 25G IEEE mode ([2])
1: 25G and 50G Consortium mode ([3])
Note: relevant only when TX_PAD_ALTER=0.
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Enable the marker transcode function to insert

an alternating pad bit instead a static value.
When 1 the pad bit will be alternating. This
10 TC_PAD_ALTER should be set for IEEE 802.3 50G mode of RW 0
operation (Clause 134, [5]).
When 0 the pad bit is static as defined by the
TC_PAD_VALUE setting.
15:11 reserved RO 0
22.3.2 RS-FEC Status Register
Table 30: RS-FEC Status Register
Reset
value
Indicates existence of the receive correction
bypass option. The bypass function allows a
RS-FEC bypass correction reduced latency operation at the cost of being
0 RO 0
ability unable to correct receive errors.
Note: option not supported.
RS-FEC bypass error Indicates the ability to disable error propagation

1 RO 1
indication ability to the PCS layer.
Asserts when error indication bypass is

enabled (see Control register bit 1) and a high
symbol error rate is found (See 11.4 page 42).
2 RS-FEC high SER RO/LH 0
The bit resets to 0 upon read and the condition
is cleared, or if the error indication bypass is
disabled.
3..7 reserved RO 0
RS-FEC receive lane locked and aligned. One

11:8 amps_lock RO 0
bit per lane: Bit 8 =lane0, ..., Bit 11=lane3.
12..13 reserved RO 0
Indicates, when 1, RS-FEC receiver has locked

on incoming data and deskew completed. The
14 fec_align_status RS-FEC receiver has reached its normal RO 0
operational state.
Real-time indication
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This bit is not applicable (RS-FEC has no PCS

receive function within the transmit datapath)
RS-FEC PCS align status and always 1.
15 RO 1
(transmit datapath) Note: This bit should not be confused with the
PCS' receive alignment status, which is
available in the status register of the PCS.
22.3.3 RS-FEC Lanemapping Register
Table 31: RS-FEC Lanemapping Register

Reset
value
7:6: FEC lane <x> mapped to PMA lane 3
7:0 PMA Mapping RO 0
8 .. 15 reserved RO 0
22.3.4 RS-FEC Vendor Control Register
Table 32: RS-FEC Vendor Control Register

Reset
value
0 reserved RO 0
1 reserved RO 0
1: Enable RS-FEC datapath instead PCS MLD.

0: Use normal PCS MLD datapath (default).
The toplevel input fec91_ena_in(0) is OR'ed
with this control bit. Hence if the external
control bit should be used the register bit
RS-FEC Enable Notes:

2 RW 0
(Ch0/100G)  This enable controls use of RS-FEC for
100G PCS when 100G PCS is active.
Otherwise it configures RS-FEC for
Channel 0.
 This is a compatibility bit only, which
should not be used and be set 0 always.
The RS-FEC Control register bit 2 should
be used instead to enable RSFEC for
100G and Channel0.
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3 reserved RO 0
Enable Channel 0 single lane mode (25G).

When 1 operates 25G over single lane 0.
When 0 operates 50G over two lanes 0 and 1.
The bit is OR'ed with the toplevel input pin
fec91_1lane_in0. Hence if the external
4 CH0_1LANE_MODE control bit should be used the register bit RW 0
Note: Setting has an effect only if RS-FEC is

enabled for Channel 0 (RS-FEC Control
Register) and the RS-FEC is currently not used
with the 100G PCS.
Enable Channel 2 single lane mode (25G).
When 1 operates 25G over single lane 2.
When 0 operates 50G over two lanes 2 and 3.
The bit is OR'ed with the toplevel input pin
fec91_1lane_in2. Hence if the external
5 CH2_1LANE_MODE control bit should be used the register bit RW 0
Note: Setting has an effect only if RS-FEC is

enabled for Channel 2 (RS-FEC Control
Register) and the RS-FEC is currently not used
with the 100G PCS.
When set '1' the last 3 markers within the
RSFEC codeword marker mapping will not be
replaced with the marker from virtual lane 16.
6 Setting this bit is suggested for 100G over 2 RW 0
AM16_COPY_DIS lanes when using KP RSFEC.
Note: Is writeable only when RS(544/514) (KP)
synthesis option is available. It then affects
both RS FEC variants.
11:7 reserved RO 0
Indicates if RSFEC is currently enabled (1) or

not (0) for a channel.
Bit 12 is for Channel0 / 100G
Per Channel RS-FEC Bit 13..15 for Channels 1..3.
15:12 RO 0
enabled status
This may be asserted if a hardware pin is used
instead of the RS-FEC Control register bit 2 to
enable the FEC datapath.
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22.3.5 RS-FEC Vendor Info 1 Register
Table 33: RS-FEC Vendor Info 1 Register

Reset
value
Per PMA lane FEC synchronization status
ROR,
3:0 amps_lock (IEEE802.3bj, Fig. 91-8), latched high. 0
LH
Bit 0=lane0, ..., Bit3=lane3
fec alignment status, latched high. ROR,

4 fec_align_status 0
LH
(see lane mapping register for real-time).
The marker_check function (PCS sublayer)

caused an alignment restart to the FEC
ROR,
5 marker_check_restart because there were 4 consecutive marker 0
LH
columns with invalid markers detected.
latched high.
RX datapath (sync) reset occured (latch high).
ROR,
6 rx_datapath_restart Indicates deskew PMA FIFOs were flushed 0
LH
and alignment restarted.
TX datapath (sync) reset occured (latch high).
ROR,
7 tx_datapath_restart All TX PMA decoupling FIFOs were flushed 0
LH
and the transmitter started again.
RX datapath 4x66 pacing fifo overflow fatal
error (latch high).
ROR,
8 rx_dp_overflow Indicates a rate overshoot between PMA and 0
LH
CGMII which caused CGMII output data
corruption.
TX datapath 4x66 input fifo overflow fatal error
(latch high)
ROR,
9 tx_dp_overflow Indicates a rate overshoot between CGMII and 0
LH
the TX MLD or FEC transcoder caused data
corruption on input data.
fec alignment status, latched low. ROR,

10 fec_align_status 0
LL
(see lane mapping register for real-time).
11 reserved RO 0
Real-time indication from FEC deskew FIFO,

deskew_empty
15:12 per lane. RO 0
reserved
bit12=lane0, ... , bit15=lane3
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22.3.6 RS-FEC Vendor Info 2 Register
Table 34: RS-FEC Vendor Info 2 Register

Reset
value
Per PMA lane FEC synchronization status
(IEEE802.3bj, Fig. 91-8). Real-Time.
3:0 amps_lock Bit 0=lane0, ..., Bit3=lane3 RO 0
Note: these are the same bits as RS-FEC

STATUS(11:8)
Per Channel RS-FEC decoder input write error
status (latch-high, clear on read).
If a bit asserts it indicates that the data rate into
the RS-FEC decoder of that channel was too
high and a decoder buffer overflow occured. At LH,
7:4 rs_decoder_write_err 0
least one RS-FEC codeword has been ROR
corrupted.
These bits should never assert during normal
operation. They indicate a mis-configuration of
the Core.
15:8 reserved RO 0
22.4 100G PCS Standard Virtual Lane Marker Values

When operating in standard 100G PCS with or without RS-FEC, the markers for 20 virtual lanes
must be configured for the 100G PCS with registers VLX_0, VLX_1 {X=0..19} (2 registers per
marker). The values are defined in 802.3 Clause 82 Table 82-2 and shown in Table 9 page 35.
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23 References
[1] IEEE 802.3-2015 Edition
[2] IEEE 802.3by, Standard for Ethernet Amendment: Media Access Control Parameters. Physical
Layers and Management Parameters for 25 Gb/s Operation.
[3] 25G/50G Ethernet Consortium, Schedule 3 25G&50G Specification, Version 1.6, Aug. 2015.
[4] IEEE 802.3bj - August 2014
[5] IEEE 802.3cd, Amendment: Media Access Control Parameters for 50 Gb/s and Physical
Layers and Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operation;
Draft 1.2; Feb. 2017.
24 Document History
Version Changes
1.0, Apr '15 Initial (based on 1.2.1 4/14)
- added memory interfaces.
- added PCS100 PCS_MODE special vendor register
1.1, Apr '15 - added 25G and 40G marker tables
1.2 June ‘15 - added pacer_10g(3:0) input pin
1.3 July `15 - Added HI_BER25 (bit 2) in 10..50G PCS Vendor PCS_MODE
Register (32784), to set different Hi-BER measurement windows
depending on the operation mode
1.7 Dec. '15 Doc aligned to 1.7.
- Added “Software Reset Usage” subchapter (5.3)
- PCS 100G Vendor Specific Register CORE_REVISION redefined
- PCS 10..50G Vendor Specific Register CORE_REVISION redefined
- PCS 10..50G Vendor Specific Register TX_LANE_THRESH redefined
- PCS 100G TX_LANE_THRESH register’s reset value changed
- RS-FEC Status register’s reset value changed
- Description of PCS registers VL_INTVL updated to reflect mode
independence
- 25/50 Consortium Draft 1.6 update now using same markers for 25G
RSFEC as IEEE hence no separated Table 11 needed any more
- Updated PCS Registers Control1(#0), Speed Ability (#4), Control2 (#7),
Status2 (#8), VL0_0 (0x8008), VL0_1 (0x8009) reflecting 25G updates
- Updated PCS EEE Control&Capability register (#20) allowing Fast-
Wake bit 0 write for all modes and indicate 25G fast-wake support.
- removed write support for PCS Control2 register
- Added RSFEC Vendor Registers DecoderThreshold0..3
1.8 March ‘16 New configuration pins for 100G mode added:
- scramble_bypass_100g
- descr_bypass_100g
1.9 July’16 New configuration pin for 10G single lane mode low latency added:
fast_1lane_mode(3:0)
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- Added description of mode related PCS register settings that need

initialization (5.3). Specific note on 50G marker symmetric setting
requirement with adjacent PCS.
2.0 July '16 - Added documentation for brought out configuration indicator signals
(pcsX_lane_active, tx_lane_threshX).
- Merged Async and Sync clocking variation in single document.
- The description changed for fec91_ena_in pin and ‘fec91 enable’ bit of
RS-FEC Control register, to clarify that this settings are per lane rather
than per channel.
- Added optional support for 100GBase-KP4 PHYs using RS(544, 514)
3.0 Sept. ’16 codewords (RS FEC mode). New pin kp_mode_in(3:0) added. Also a
new bit ‘kp mode enable’ in the RS-FEC Control register added. (Note:
This feature is available, only when the synthesis option to enable the RS
(544, 514) support is set. This feature support is a matter of package’s
delivery agreement and requires a different file list.)
- RS-FEC Vendor Control Register updated (bit6: ‘AM16_COPY_DIS’)
3.1 Sept.’16 - Correct ber_timer_short pin acting on 100G PCS only, not VL_INTVL
register setting.
- Added RSFEC Control register bits 9 (TC_PAD_VALUE) and 10
3.2 Mar. '17 (TC_PAD_ALTER) (Table 29)
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25 Contact
MorethanIP GmbH
Muenchner Str. 199
85757 Karlsfeld
Germany
Tel : +49 (0) 8131 333939-0

FAX : +49 (0) 8131 333939-1
E-Mail : info@morethanip.com
Internet : www.morethanip.com
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25g4ch 100g Allpcs Ref Guide v3.2

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4 Channel 100G Ethernet Multirate PCS Mapper

100 Gigabit Ethernet

with Clause 91 Reed-Solomon FEC

Figure 1: 100G PCS Mapper Transmit Block Diagram ................................................................................ 10

Table 1: Signal Description............................................................................................................................... 12

2 Core Features Overview

2.1 100Geth PCS Layer Features

2.2 10/25/40/50Geth PCS Layers Features

2.3 Base-R (Firecode) FEC Features

2.4 Reed-Solomon FEC (RS-FEC) Features

2.5 Multirate Features

3 100G Base-R PCS Mapper Core Block Diagram

4-Channel PCS Mapper - TX

100G PCS TX 20 VLs

XLGMII 2 4x 66b FEC74

Figure 1: 100G PCS Mapper Transmit Block Diagram

4-Channel PCS Mapper - RX

100G PCS RX 20 VLs

Figure 2: 100G PCS Mapper Receive Block Diagram

lpi_tick_tx(3:0) ber_timer_short PCS

Figure 3: Core Pinout Overview

4.1 Core Signals

Signal Name Mode Description

reset_ref_clk In Active high reset signal for ref_clk clock domain.

reg_clk In Register Interface Reference Clock.

CGMII (100G PCS)

CGMII Transmit Clock Enable Signal (sampling of cgmii_txd/c).

Channel 0 to 3 PCS XLGMII (N=0..3)

XLGMII Transmit Clock Enable.

XGMII Receive Clock Enable.

Channel 0 to 3 PCS Receive Status

Per channel link status. One bit per channel.

Channel 0 to 3 PCS Energy-Efficient Ethernet Client Interfaces

PMA Transmit Interface

PMA Receive Interface

PMA Signal Detect indication for sd0_rx … sd3_rx lanes.

100G PCS Receive Status

High Bit Error Rate indication. If asserted, at least 97 invalid synchronization

Final link status indication for 100G PCS.

Define 40G mode of operation for Channel 0.

PCS Test Signals

Optional FEC (Clause 74) Module Configuration

Channel 0 to 3 PCS Management Register Interface (N=0..3)

regN_rden In Register Read Enable.

regN_din(15:0) In Register Write Data. Bit 0 is the least significant bit.

100G PCS Management Register Interface

reg_rden In Register Read Enable.

reg_din(15:0) In Register Write Data. Bit 0 is the least significant bit.

Clause 91 RS-FEC Management Register Interface

reg91_rden In Register Read Enable.

reg91_din(15:0) In Register Write Data. Bit 0 is the least significant bit.

Presents the bits 3:0 of the PCS100 configuration register TX_LANE_

Presents the bits 7:4 of the PCS100 configuration register TX_LANE_

Presents the bits 15:12 of the PCS100 configuration register TX_LANE_

4.2 Core Memory Interface Signals

Signal Name Mode Description

RS-FEC Decoder Memory: 1 instance of

(all synchronous to ref_clk)

f91m_wren Out RSFEC memory write enable.

RSFEC memory write address. m = 8, if the the RS (544, 514) supported,

f91m_wdata(161:0) Out RSFEC memory write data to memory.

f91m_rden Out RSFEC memory read enable

RSFEC memory read address. m = 8, if the the RS (544, 514) supported,