Module 3

MODULE 3
CST 307 : Microprocessors &

Microcontrollers
Syllabus- Module 3 2
Stack and interrupts

 Stack structure of 8086  Programmable Interrupt
o Programming using stack Controller – 8259
 Interrupts o Architecture
(Just mention the control word, no need
o Types of Interrupts
to memorize the control word)
o Interrupt Service Routine
 Interfacing Memory with 8086.
o Handling Interrupts in 8086
o Interrupt programming.
Stack, Subroutine, Macros 3
 As the resources of a microprocessor and its memory is limited, in

order to handle lengthy programs, we use Stack, Subroutine and
Macro.
o All of them help to reduce the recurring instructions and to have partial
results of a program
Subroutine 4
 Subroutine is a sub task of a main program, which may occur more than one
time during the execution.
o Instead of writing a single big program, it is split it into number of sub-tasks that
constitute the complete application and then write separate routines for each
subtask.
o After that, a main program is prepared that calls the specific routines for the specific
tasks.
• CALL instruction is used to divert the main program execution to sub program/ subroutine/
procedure
o After executing the main program up to the CALL instruction, the control will be
transferred to the subroutine address.
Stack 5
 When the control of a main program is transferred to subroutine,

o Microprocessor must know where the control is to be returned after the execution.
• A similar problem may arise while handling interrupts.
o Stack is a temporary storage mechanism to store the address of re-entry into the
main program.
o Stack also stores the register status, flag status etc.. at the time of calling a subroutine
and getting it back at the time of returning
• The registers or memory locations already used during the main program can be reused by the
subroutine without any loss of data.
• Some of the registers of the main program may be modified due to the execution of the
subroutine, which will be avoided using stack
MODULE 3

Microcontrollers

Stack 8
 The stack is a block of memory that may be used for temporarily storing the contents
of the registers inside the CPU
o The stack is a block of memory locations which is accessed using the SP and SS registers.
o It is a top-down data structure whose elements are accessed using a pointer that is
implemented using the SP and SS registers.
 As we go on storing the data words onto the stack, the pointer goes on decrementing
and on the other hand, the pointer goes on incrementing as we go on retrieving the
word data.
o For each such access, the stack pointer is decremented or incremented by two.
Stack 9
 The stack is required in case of CALL instructions.

o The data in the stack, transferred back from stack to register, whenever required by the CPU.
 Stack operation
o The process of storing the data in the stack is called ‘pushing into’ the stack and
o The reverse process of transferring the data back from the stack to the CPU register is known
as ‘popping off’ the stack.
 The stack is essentially Last-In-First-Out (LIFO) data segment.

o The data which is pushed into the stack last will be on top of stack and will be popped off the
stack first.
Stack Procedure 10
 Suppose, a main program is being executed by the processor. And all the registers in the CPU may
contain useful data.
o In case there is a subroutine CALL instruction at this stage, there is a possibility that all or some of the
registers of the main program may be modified due to the execution of the subroutine.
• This may result in loss of useful data, which may be avoided by using the stack.
o At the start of the subroutine, all the registers’ contents of the main program may be pushed onto the
stack one by one. After each PUSH operation SP will be modified as already explained before.
o Now these registers may be used by the subroutine, since their original contents are saved onto the
stack.
o At the end of the execution of the subroutine, all the registers can get back their original contents by
popping the data from the stack.
• The sequence of popping is exactly the reverse of the pushing sequence.
• The register or memory location that is pushed into the stack at the end should be popped off first.
Stack Procedure 11
 After a subroutine is called using the CALL instruction,

o The IP is incremented to the next instruction.
o Then the contents of IP, CS and flag register are pushed automatically to the stack.
o The control is then transferred to the specified address in the CALL instruction,
• i.e the starting address of the subroutine.
• Then the subroutine is executed.
 There should be an equal number of PUSH and POP instructions in the subroutine that has to be
executed so that the SP contents at the time of calling the subroutine must be equal to the
contents of SP at the time of executing the RET instruction, at the end of the subroutine.
Otherwise, the control that should be returned to the next instruction after the CALL instruction
will not be returned back properly.
Stack Segment register (SS) and Stack Pointer register (SP) 12
Stack Structure 13
 The Stack top points to a memory location (52050 H) means, the location is
already occupied
o i.e. previously pushed data is available at that location (52050 H).
 The next 16-bit push operation will decrement the stack pointer by 2
o New stack-top will be 5204EH Contents of SP will be 5204E H.
o New data will be pushed to this location
 For a selected value of SS, the maximum value of SP = FFFF H

o Segment can have maximum of 64K locations.
 After successive push operations, when the Stack Pointer contains 0000 H, any
attempt to further push the data to the stack will result in Stack Overflow.
Stack Segment register (SS) and Stack Pointer register (SP) 14
15
 The Execution of Bracketed PUSH AX Instruction Results in Stack Overflow

Effect of PUSH and POP on SP 16
MODULE 3

Microcontrollers

Programming for Stack 19
 The memory bank of 8086/88 is organised according to segments.

 The 8086/8088 has four segment registers, namely, CS,DS,SS and ES.
 Out of these segment registers
o SS: ‘Stack Segment Register’ contains the segment value for stack
o SP: Stack Pointer contains the offset for the stack-top.
 In a program the stack segment can be defined in a similar way as the data segment.
o The ASSUME directive directs the name of the stack segment to the assembler.
o The SS register and the SP register must be suitably initialised in the program
Qu 1: Write a program to calculate squares of BCD numbers 0 to 9
20
and store them sequentially from 2000H offset onwards in the
current data segment. The numbers and their squares are in the BCD
format. Write a subroutine for the calculation of the square of a
number
Qu 1: Write a program to calculate squares of BCD numbers 0 to 9 and store them
sequentially from 2000H offset onwards in the current data segment. The numbers and 21
their squares are in the BCD format. Write a subroutine for the calculation of the square of
a number
 The procedure of computing the square of a number is to be repeated for all the numbers.
o A subroutine for calculating the square is written which is called repetitively from the main program.
 The 8086/88 does not have single instruction for calculation of the square of a number.
o Thus you may calculate the square of a number using ADD and DAA instructions.
• [why not to use the MUL instruction for calculating the squares of the number?
MUL instruction does not calculate the square of a decimal number and
the DAA instruction is to be used only after the ADD or ADC instructions.]
 One of the advantages of the subroutine is that, a recurring sequence of instructions can be
assigned with a procedure name, which may be called again and again whenever required,
resulting in a comparatively smaller sequence of instructions.
Main Program 22
Sub Program 23
Qu 2: Write a program to change a sequence of sixteen 2-byte numbers from
24
ascending to descending order. The numbers are stored in the data segment.
Store the new series at addresses starting from 6000 H. Use the LIFO property
of the stack
25
MODULE 3

Microcontrollers

Interrupts 28
 Interrupt is some event that breaks the sequence of operation.
 If an ‘Interrupt occurs while CPU is executing a program
o Breaks the normal sequence of execution of instructions
o Diverts its execution to some other program called Interrupt Service

Routine (ISR).
o After executing ISR, the control is transferred back again to the main
program which was being executed at the time of interruption.
Interrupts 29
 Multiple interrupt processing capability.

o It is the ability of a processor to properly handle the interrupts from a number
of devices
 In 8086, there are two interrupt pins

o NMI: a non-maskable interrupt input pin
• Any interrupt request at NMI input cannot be masked or disabled by any means
o INTR: Interrupt input Pin

• May be masked using the Interrupt Flag (IF).
Interrupt Service Routine 30
 INTR is of 256 types.

o The INTR types may be from 00 to FFH (or 0 to 255).
o An external Programmable Interrupt controller is used to handle the occurrence of
more than one type INTR at a time.
 Interrupt Service Routines (ISRs) are the programs to be executed by

interrupting the main program execution of the CPU, after an interrupt request
appears.
o After the execution of ISR, the main program continues its execution further from the
point at which it was interrupted.
Types of Interrupts 31
 There are two types of interrupts.

o External interrupt
• An external device or a signal interrupts the processor from outside (Interrupt is
generated outside the processor).
• Example- a keyboard interrupt
o Internal interrupt.
• Generated internally by the processor circuit, or by the execution of an interrupt
instruction.
• Examples- Divide by zero interrupt, Overflow interrupt, Interrupts due to INT instructions, etc.
Interrupt Cycle of 8086 32
 When an external device interrupts the CPU at the interrupt pin (either NMI
or INTR), while the CPU is executing an instruction of a program.
o The CPU first completes the execution of the current instruction.
o The IP is then incremented to point to the next instruction.
o The CPU then acknowledges the requesting device on its INTA# pin immediately if
it is a NMI, TRAP or Divide by Zero interrupt.
o If it is an INT request, the CPU checks the IF flag.
• If the IF is set , the interrupt request is acknowledged using the INTA# pin.
• If the IF is not set, the interrupt requests are ignored.

• Note: The responses to the NMI, TRAP and Divide by Zero interrupt requests are independent of the IF flag.
 After an interrupt is acknowledged 33
o CPU computes the vector address of the interrupt
• Internally -In case of software interrupts, NMI, TRAP and Divide by Zero interrupts or
• Externally from an interrupt controller - In case of external interrupts.
o The contents of IP and CS are next pushed to the stack.

• To point to the address of the next instruction of main program from which the execution is to be
continued after ISR.
o The PSW is also pushed to the stack, The Interrupt Flag (IF) is cleared.
• The TF is also cleared, after every response to the single step interrupt.
o The control is then transferred to the Interrupt Service Routine for serving the interrupting
device.
• The new address of ISR is found out from the interrupt vector table.
o The execution of the ISR starts.

Interrupt Cycle of 8086 34
 If further interrupts are to be responded to during the time the first interrupt is being
serviced, the IF should again be set to 1 by the ISR of the first interrupt.
o If the interrupt flag is not set, the subsequent interrupt signals will not be acknowledged by
the processor, till the current one is completed.
o The programmable interrupt controller is used for managing such multiple interrupts based
on their priorities.
o At the end of ISR the last instruction should be IRET.

• When the CPU executes IRET , the contents of flags, IP and CS which were saved at the start by the CALL
instruction are now retrieved to the respective registers.
 The execution continues onwards from this address, received by IP and CS.
Address of an ISR 35
 Every external and internal interrupt is assigned with a Type (N)

o Implicit (in case of NMI, TRAP and Divide by Zero) or
o Specified in the instruction INT N (in case of internal interrupts)
o In case of external interrupts, the type is passed to processor by programmable interrupt

controller.
 Intel has reserved 1,024 locations (1K) for storing the address of ISR, in the zeroth segment
of physical address space, i.e. CS = 0000– Called INTERRUPT VECTOR TABLE
 8086 supports a total of 256 (00 to FF) types of the interrupts,

o Each interrupt requires 4 bytes, i.e. two bytes each for IP and CS of its ISR.
o Total of 1,024 bytes are required for 256 interrupt types [from 0000:0000 to 0000:03FFH]
Interrupt Vector Table 36
 The interrupt vector table contains the IP and CS of all the
interrupt types stored sequentially from address 0000:0000 to

0000:03FF H.
o The interrupt type N is multiplied by 4 and the hexadecimal
multiplication obtained gives the offset address in CS:0000, at which
the IP and CS addresses of the Interrupt Service Routine (ISR) are stored.
o The execution automatically starts from the new CS:IP.

Interrupt Response Sequence 37
IVT 38
5 Dedicated Interrupts 39
 Type 0: Divide by Zero Interrupt
 Type 1: Single Step Interrupt (INT1)
 Type 2: NMI (Non Mask-able Interrupt) (INT2)
 Type 3: One Byte Interrupt/Breakpoint Interrupt (INT3)
 Type 4: Interrupt on Overflow (INTO)

Type 0: Divide by Zero Interrupt 40
 8086 will automatically do a type 0 interrupt if the result of DIV or IDIV operation
is too large to fit in destination register.
 When type 0 interrupt is internally generated, microprocessor will
o Push flag register, Reset TF and IF, Push CS and IP (i.e. return address), Get NEW CS and
NEW IP for the ISR
o After returning from ISR, microprocessor will pop CS and IP (OLD CS/OLD IP) as well as pop
flag register.
 Type 0 is automatic and cannot be disabled i.e. non mask-able.

o Users have to account it in the program where he/she uses DIV/IDIV instruction.
o To avoid this interrupt, user can check before division that divisor is not zero.
Type 1: Single Step Interrupt (INT1) 41
 The microprocessor executes this interrupt after every instruction if the TF

is set.
 It puts microprocessor in single stepping mode

o Microprocessor pauses after executing every instruction.
o Very useful during debugging.
 Its ISR generally displays contents of all registers.

o Its ISR address is stored at location 1 x 4 = 00004H in the IVT.
Type 2: NMI (Non Mask-able Interrupt) (INT2) 42
 Highest priority hardware interrupt and is non mask-able.

o The input is edge triggered (LOW to HIGH) but is synchronized with the CPU clock
o Must be active for two clock cycles to generate recognition.
 The interrupt signal may be removed prior to entry to the service routine.
 Its ISR address is stored at location 2 x 4 = 00008H in the Interrupt Vector Table
(IVT).
 Basically NMI interrupt input is used for catastrophic failures for example
power failure, time out of system watchdog timer.
Type 3: One Byte Interrupt/Breakpoint Interrupt (INT3) 43
 This type is invoked by a special form of the software interrupt instruction which requires a single byte of
code space i.e. CCH (INT3).
 This interrupt is primarily used as a breakpoint interrupt for software debug.
 When we insert a breakpoint in program, the system executes instructions up to the breakpoint and then
goes to the breakpoint procedure.
 When user informs debugger program to insert breakpoint at some point in program, they actually do it by
temporarily replacing the instruction byte at that address with CCH i.e. code for INT3 instruction.
 Thus this single byte instruction can be mapped into the smallest instruction for absolute resolution in
setting breakpoints.
 Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
 A breakpoint ISR routine usually saves all the register contents on the stack.
Type 4: Interrupt on Overflow (INTO) 44
 This interrupt occurs if the overflow flag (OF) is set in the flag register.
 The OF flag is set if the signed result of an arithmetic operation on two

signed number is too large to be represented in destination register or
memory location.
o This interrupt is used to capture overflow errors.
 Its ISR address is stored at location 4 x 4 = 00010H in the IVT

Interrupts- Non Maskable Interrupt (NMI) 45
 Highest priority among the external interrupts.
o TRAP(Single Step-Type I) is an internal interrupt having the highest priority amongst all the interrupts except the Divide
By Zero (Type0) exception.
 The NMI is activated on a positive transition (low to high voltage).

o The assertion of the NMI interrupt is equivalent to an execution of instruction INT 02, i.e. Type 2 INTR interrupt.
 The NMI pin should remain high for at least two clock cycles and need not synchronized with the clock for
being sensed.
 When the NMI is activated, the current instruction being executed is completed and then the NMI is served.
o In case of string type instructions, this interrupt will be served only after the complete string has been manipulated.
o Another high going edge on the NMI pin of 8086, during the period in which the first NMI is served, triggers another
response.
 The signal on the NMI pin must be free of logical bounces to avoid erratic NMI responses.
Interrupts - Maskable Interrupt (INTR) 46
 Lower priority as compared to NMI.

o Further the priorities within the INTR types are decided by the type of the INTR signal that is to be passed to the
processor via data bus by some external device like the programmable interrupt controller.
 The INTR signal is level triggered and can be masked by resetting the interrupt flag.
 The INTR requests appearing after the last clock cycle of the current instruction will be responded to after
the execution of the next instruction.
o The status of the pending interrupts is checked at the end of each instruction cycle.
 If the IF is set, the processor is ready to respond to any INTR interrupt
 If the IF is reset, the processor will not serve any interrupt appearing at this pin.
o Once the processor responds to an INTR signal, the IF is automatically reset.
 If one wants the processor to further respond to any type of INTR signal, the IF should again be set.
MODULE 3

Microcontrollers

Interrupt Programming 49
 While programming for any type of interrupt,

o the programmer must, either externally or through the program,
o set the interrupt vector table for that type
o with the CS and IP addresses of the interrupt service routine.
 The method of defining the interrupt service routine for software as

well as hardware interrupt is the same.
o It is assumed that the interrupt vector table is initialised suitably to point to
the interrupt service routine.
Interrupt Programming- Transfer of control 50
Transfer of Control for Nested Interrupt 51
Interrupt Cycle 52
Write a program to create a file RESULT and store in it 500H bytes from the
53
memory block starting at 1000:1000, if either an interrupt appears at INTR
pin with Type 0AH or an instruction equivalent to the above interrupt is
executed
54
55
Write a program that gives display ’IRT2 is OK’ if a hardware signal appears
on IRQ2 pin and ’IRT3 is OK’ if it appears on IRQ3 pin of PC IO Channel 56
57
MODULE 3

Microcontrollers
Basic Peripherals and their Interfacing with 8086 59
 In the minimal working system configuration of a general microprocessor, along with the CPU, there
will be
o a keyboard
o display system
o memory system and
o I/O ports
• All these devices are called PERIPHERAL DEVICES.
 There are also some additional dedicated peripheral devices like

o PIC [Programmable Interrupt Controller]
o DMA [Direct Memory Access] controller
o CRT controller, etc.
 All the peripheral circuits including memory system are built around the microprocessor.
o Memory (primary) is considered as an integral part of a microprocessor system.
 Most of the peripheral devices are designed and interfaced with a CPU
o To enable to communicate with the user or an external process
o To ease the circuit operations so that the microprocessor works more efficiently and
effectively.
 Use of a peripheral device simplifies both the hardware circuits and the software
 Each of these special purpose devices need a typical sequence of instructions to
make it work.
o This instruction sequence appropriately initialises the peripheral and makes it work
under the control of the microprocessor.
 Unlike the peripheral devices, memory does not need any initialization and does
not directly participate in the process of communication between CPU and the user.
o Memory acts as a media for the communication between a peripheral with the
microprocessor.
 While memory may be treated as a peripheral, on the other hand, peripheral

devices are often treated as memory locations.
 Thus as far as the CPU is concerned, there is no special difference in the method
of handling memory or peripherals, except for the use of respective control
signals.
MODULE 3

Microcontrollers

Programmable Interrupt Controller (PIC) - 8259 64
 The processor 8085 had 5 hardware interrupt pins.

o 4 pins were allotted fixed vector addresses
o Pin INTR was not allotted any vector address
 An external device was supposed to hand over the type of the interrupt, i.e. (Type 0 to 7 for
RST0 to RST7), to the microprocessor.
o The microprocessor then gets this type and derives the interrupt vector address from that.
 Consider an application, where a number of I/O devices connected with a CPU desire to
transfer data using interrupt driven data transfer mode.
o Here, more number of interrupt pins are required than available in a typical microprocessor.
o In these multiple interrupt systems, the processor will have to take care of the priorities for the
interrupts, simultaneously occurring at the interrupt request pins.
Programmable Interrupt Controller (PIC) - 8259 65
 To overcome all these difficulties, we require a programmable interrupt

controller which is able to handle a number of interrupts at a time.
 This controller takes care of a number of simultaneously appearing interrupt

requests along with their types and priorities.
 The programmable interrupt controller 8259 was designed to operate only

with 8-bit processors like 8085.
 A modified version, 8259A was later introduced that is compatible with 8-bit as
well as 16-bit processors.
MODULE 3

Microcontrollers

Architecture of 8259A 68
 Interrupt Request Register (IRR)

o The interrupts at IRQ input lines are handled by IRR internally.
o IRR stores all the interrupt requests in its order to serve them one by one
on the priority basis.
 ln-Service Register (ISR)

o Stores all the interrupt requests those are being served,
o ISR keeps a track of the requests being served.

 Priority Resolves
o Determines the priorities of the interrupt requests appearing
simultaneously.
o The highest priority is selected and stored into the corresponding bit of ISR
during INTA# pulse.
o The IR0 has the highest priority while the IR7 has the lowest one, normally in
fixed priority mode.
o The priorities however may be altered by programming the 8259A in rotating
priority mode.
 Interrupt Mask Register (IMR)

o Stores the bits required to mask the interrupt inputs.
o IMR operates on IRR at the direction of the Priority Resolves.
 Interrupt Control Logic

o Manages the interrupt and the interrupt acknowledge signals to be sent to
the CPU for serving one of the eight interrupt requests.
o Also accepts the interrupt acknowledge (INTA) signal from CPU that causes the
8259A to release vector address on to the data bus
 Data Bus Buffer

o Tristate bidirectional buffer
o Interfaces internal 8259A bus to the microprocessor system data bus.
o Control words, Status and Vector information pass through data buffer during
read or write operations.
 Read/Write Control Logic

o This circuit accepts and decodes commands from the CPU.
o Allows the status of the 8259A to be transferred on to the data bus.
 Cascade Buffer/Comparator
o Stores and compares the IDs of all the 8259As used in the system.
o The three I/O pins CA S0-S2 are outputs when the 8259A is used as a master.
• The same pins act as inputs when the 8259A is in the slave mode.
o The 8259A in the master mode, sends the ID of the interrupting slave device
on these lines.
• The slave thus selected, will send its pre-programmed vector address on the data bus
during the next INTA pulse
74
MODULE 3

Microcontrollers

Memory Interfacing 77
 Memory Types – RAM and ROM
 RAM Types – Static RAM and Dynamic RAM

Static RAM Interfacing 78
 Semiconductor memories are organised as two dimensional arrays of memory locations.

o For example, 4K x 8 or 4K byte memory contains 4096 locations
o Each location contains 8-bit data and only one of the 4096 locations can be selected at a time.
 Once a location is selected, all the bits in it are accessible using a group of conductors called
‘data bus’.
 For addressing 4K bytes of memory, 12 address lines are required.
 To address a memory location out of N memory locations , we will require at least n bits of
address,
o i.e. n address lines where n = Log2 N.
Static RAM Interfacing 79
 If the microprocessor has n address lines, then it is able to address at the most N
locations of memory, where 2n = N.
 Out of N locations only P memory locations are to be interfaced, then
o The least significant p address lines out of the available n lines can be directly connected from
the microprocessor to the memory chip
o The remaining (n—p) higher order address lines may be used for address decoding (as inputs
to the chip selection logic).
 The memory address depends upon the hardware circuit used for decoding the chip
select (CS).
o The output of the decoding circuit is connected with the CS pin of the memory chip.
General procedure of Static Memory Interfacing 80
1. Arrange the available memory chips so as to obtain 16-bit data bus width.
o The upper 8-bit bank is called ‘odd address memory bank’ and the lower 8-bit bank is
called ‘even address memory bank’
2. Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD# and WR# inputs to the
corresponding processor control signals. Connect the 16-bit data bus of the
memory bank with that of the microprocessor 8086
3. The remaining address lines of the microprocessor, BHE# and A0 are used for
decoding the required chip select signals for the odd and even memory banks.
o The CS of memory is derived from the O/P of the decoding circuit
81
Example Problems
1. Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with
82
8086. Select suitable maps
 After reset, the IP and CS are initialised to form address FFFFOH.
• Hence, this address must lie in the EPROM.
 The address of RAM may be selected any where in the 1MB address space
• Select the RAM address such that the address map of the system is continuous
83
84
 Total 8K bytes of EPROM need 13 address lines A0—A2 (since 213 = 8K).
 Address lines A13 —A19 are used for decoding to generate the chip
select.
 The BHE# signal goes low when a transfer is at odd address or higher
byte of data is to be accessed.

 The memory system in this example contains in total four 4K x 8 memory chips.
85
o The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data bus width.
 If A0 is 0, i.e. the address is even and is in RAM

o The lower RAM chip is selected indicating 8-bit transfer at an even address.
 If A0 is 1,
o The address is odd and is in RAM
 BHE# goes low

o Upper RAM chip is selected, further indicating that the 8-bit transfer is at an odd address.
 If the selected addresses are in ROM, the respective ROM chips are selected.
 If at a time A0 and BHE both are 0, both the RAM or ROM chips are selected, i.e. the data
transfer is of 16 bits.
Memory Chip Selection 86
2. Design an interface between 8086 CPU and two chips of 16K x 8
87
EPROM and two chips of 32K x 8 RAM. Select the starting address
of EPROM suitably. The RAM address must start at 00000H.
 The last address in the map of 8086 is FFFFFH.
 After resetting, the processor starts from FFFFOH.

o Hence this address must lie in the address range of EPROM.
 The RAM address Starts at 00000H
-Following figures shows the interfacing diagram, and complete map of the system.
Address Map 88
 16K x 8 EPROM – 2 no.s

o Must Include FFFF0H
 32K x 8 RAM – 2 no.s

o Must Start at 00000H
Interfacing 89
Chip Selection Logic 90
3. It is required to interface two chips of 32K x 8 ROM and four chips
91
of 32K x 8 RAM with 8086, according to the following map.
ROM 1 and 2 F0000H - FFFFFH,
RAM 1 and 2 D0000H - DFFFFH
RAM 3 and 4 E0000H - EFFFFH
Memory map
Interfacing 92
Interfacing 93
4. Design a memory system around 8088, that has total 16K x 8
94
EPROM and 32K x 8 RAM. The EPROM chips are available in modules
of 8K x 8 and the RAM chips are available in modules of 8K x 8.
 Since it is for 8088, there will not be odd and even banking.
 Lets check the address mapping with the following details, as it will be compatible
with 8086
o EPROM 1- F0000H - F1FFFH
o EPROM 2- Decide suitably for a practical system- (to include FFFF0H)
o RAM 1 - Contains Interrupt vector table
o RAM 2 - 30000H - 31FFFH
o RAM 3 - 40000H - 41FFFH
o RAM 4 - SOOOOH - 51FFFH
Address mapping 95
5. Interface a 4K x 8 EPROM, one chip of 8K x 8 RAM, two 96
chips of 8K x 4 RAM with 8088.
97

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MODULE 3

CST 307 : Microprocessors &

Stack and interrupts

o Programming using stack Controller – 8259

 As the resources of a microprocessor and its memory is limited, in

 When the control of a main program is transferred to subroutine,

CST 307 : Microprocessors &

Stack and interrupts

o Programming using stack Controller – 8259

 The stack is required in case of CALL instructions.

 The stack is essentially Last-In-First-Out (LIFO) data segment.

 After a subroutine is called using the CALL instruction,

• Then the subroutine is executed.

o New data will be pushed to this location

 For a selected value of SS, the maximum value of SP = FFFF H

 The Execution of Bracketed PUSH AX Instruction Results in Stack Overflow

CST 307 : Microprocessors &

Stack and interrupts

o Programming using stack Controller – 8259

 The memory bank of 8086/88 is organised according to segments.

o SP: Stack Pointer contains the offset for the stack-top.

CST 307 : Microprocessors &

Stack and interrupts

o Programming using stack Controller – 8259

 Interrupt is some event that breaks the sequence of operation.

 If an ‘Interrupt occurs while CPU is executing a program

o Breaks the normal sequence of execution of instructions

o Diverts its execution to some other program called Interrupt Service

 Multiple interrupt processing capability.

 In 8086, there are two interrupt pins

o INTR: Interrupt input Pin

 INTR is of 256 types.

 Interrupt Service Routines (ISRs) are the programs to be executed by

 There are two types of interrupts.

• If the IF is not set, the interrupt requests are ignored.

o The contents of IP and CS are next pushed to the stack.

o The execution of the ISR starts.

o At the end of ISR the last instruction should be IRET.

 Every external and internal interrupt is assigned with a Type (N)

o Specified in the instruction INT N (in case of internal interrupts)

o In case of external interrupts, the type is passed to processor by programmable interrupt

 8086 supports a total of 256 (00 to FF) types of the interrupts,

 The interrupt vector table contains the IP and CS of all the

interrupt types stored sequentially from address 0000:0000 to

o The execution automatically starts from the new CS:IP.

 Type 0: Divide by Zero Interrupt

 Type 1: Single Step Interrupt (INT1)

 Type 2: NMI (Non Mask-able Interrupt) (INT2)

 Type 3: One Byte Interrupt/Breakpoint Interrupt (INT3)

 Type 4: Interrupt on Overflow (INTO)

 Type 0 is automatic and cannot be disabled i.e. non mask-able.

 The microprocessor executes this interrupt after every instruction if the TF

 It puts microprocessor in single stepping mode

o Very useful during debugging.

 Its ISR generally displays contents of all registers.

 Highest priority hardware interrupt and is non mask-able.

o Must be active for two clock cycles to generate recognition.

 This interrupt is primarily used as a breakpoint interrupt for software debug.

 Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.

 The OF flag is set if the signed result of an arithmetic operation on two

 Its ISR address is stored at location 4 x 4 = 00010H in the IVT

 The NMI is activated on a positive transition (low to high voltage).

 Lower priority as compared to NMI.