Verilog III

Accelerating Systems with
Programmable Logic Components

Lecture 05 Verilog III
1DT109 ASPLOC
2022 VT1-VT2
Yuan Yao, yuan.yao@it.uu.se
2022-09-17 1
Agenda
• Conditional statement
• If-else statement
• The “: ?” conditional operator
• Case statement
• Finite state machine (FSM)
• A mini project
• We will do it together
2022-09-17 2
Conditional statement
• If-else statement
• The “: ?” conditional operator
• Case statement
2022-09-17 3
If-else statement
2022-09-17 4
If-else statement
• The if-else statement is used to determine whether
the statements within the if/else block should be
executed.
2022-09-17 5
If-else statement
executed.
• If the expression evaluates to true,
2022-09-17 6
If-else statement
executed.
any non-zero value,
2022-09-17 7
If-else statement
executed.
any non-zero value,
all statements within that if block will be executed.
2022-09-17 8
If-else statement
executed.
any non-zero value,
• If the expression evaluates to false,
2022-09-17 9
If-else statement
executed.
any non-zero value,
0 or ‘X’ or ‘Z’,
2022-09-17 10
If-else statement
• The if-else statement is used to determine whether the
statements within the if/else block should be executed.
any non-zero value,
0 or ‘X’ or ‘Z’,
the statements within that if block will not be executed.
2022-09-17 11
If-else statement
any non-zero value,
0 or ‘X’ or ‘Z’,
• If there is an else statement and the expression is false then
the statements within the else block will be executed (the
“default” case).
2022-09-17 12
If-else statement
Syntax is very
any non-zero value,similar to C if statement.
But behaviors
all statements within that ifare very
block will different.
be executed.
0 or ‘X’ or ‘Z’,
• If there is an else statement and the expression is false then
the statements within the else block will be executed (the
“default” case).
2022-09-17 13
If-else statement
2022-09-17 14
If-else statement
module demo_1(
input D, clk, n_rst,
output Q);
reg reg_Q;
assign Q = reg_Q;
always @ (posedge clk) begin
if(!n_rst)
reg_Q <= 1'b0;
else
reg_Q <= D;
end
endmodule
2022-09-17 15
If-else statement
module demo_1(
input D, clk, n_rst,
output Q);
reg reg_Q;
assign Q = reg_Q;
always @ (posedge clk) begin
if(!n_rst)
reg_Q <= 1'b0;
else
reg_Q <= D;
end
endmodule
2022-09-17 16
If-else statement
module demo_1( module demo_2(
input D, clk, n_rst, input D, clk, n_rst,
output Q); output Q);
reg reg_Q; reg reg_Q;
assign Q = reg_Q; assign Q = reg_Q;
always @ (posedge clk) begin always @ (posedge clk,

negedge n_rst) begin
if(!n_rst) if(!n_rst)
reg_Q <= 1'b0; reg_Q <= 1'b0;
else else
reg_Q <= D; reg_Q <= D;
end end
endmodule endmodule
2022-09-17 17
If-else statement
input D, clk, n_rst, input D, clk, n_rst,
always @ (posedge clk) begin always @ (posedge clk,

negedge n_rst) begin
if(!n_rst) if(!n_rst)
reg_Q <= 1'b0; reg_Q <= 1'b0;
else else
end end
endmodule endmodule
2022-09-17 18
If-else statement
module demo_1( module demo_2( module demo_3(
input D, clk, n_rst, input D, clk, n_rst, input D, clk, rst,
output Q); output Q); output Q);
reg reg_Q; reg reg_Q; reg reg_Q;
assign Q = reg_Q; assign Q = reg_Q; assign Q = reg_Q;
always @ (posedge clk) begin always @ (posedge clk, always @ (posedge clk,
negedge n_rst) begin posedge rst) begin
if(!n_rst) if(!n_rst) if(rst)
reg_Q <= 1'b0; reg_Q <= 1'b0; reg_Q <= 1'b0;
else else else
reg_Q <= D; reg_Q <= D; reg_Q <= D;
end end end
endmodule endmodule endmodule

2022-09-17 19
If-else statement
module demo_1( module demo_2( module demo_3(
input D, clk, n_rst, input D, clk, n_rst, input D, clk, rst,
output Q); output Q); output Q);
reg reg_Q; reg reg_Q; reg reg_Q;
assign Q = reg_Q; assign Q = reg_Q; assign Q = reg_Q;
always @ (posedge clk) begin always @ (posedge clk, always @ (posedge clk,
negedge n_rst) begin posedge rst) begin
if(!n_rst) if(!n_rst) if(rst)
reg_Q <= 1'b0; reg_Q <= 1'b0; reg_Q <= 1'b0;
else else else
reg_Q <= D; reg_Q <= D; reg_Q <= D;
end end end
endmodule endmodule endmodule

2022-09-17 20
If-else statement
input D, en, input D, en,
always @ (D, en) begin always @ (D, en) begin
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
end end
endmodule endmodule
2022-09-17 21
If-else statement
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
• If enabled, the output
end follows the input. end
• Otherwise, the output
endmodule is reset to 0. endmodule
2022-09-17 22
If-else statement
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
2022-09-17 23
If-else statement
reg reg_Q; reg reg_Q; • If enabled, the output

follows the input.
assign Q = reg_Q; assign Q = reg_Q; • Otherwise, the output
holds the old value.
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
2022-09-17 24
If-else statement

follows the input.
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
2022-09-17 25
If-else statement

follows the input.
if(!en) if(en)
reg_Q <= 1'b0; reg_Q <= D;
else
reg_Q <= D;
2022-09-17 26
If-else statement
Rules of thumb
assign Q No.7:
follows the input.
assign Q = reg_Q; = reg_Q; • Otherwise, the output
Always enclose an if with an beginelse to

always @ (D, en) begin always @ (D, en)
if(!en) avoid
reg_Q <= 1'b0;
auto-generated
if(en)
reg_Q <= D;
latch.
else
reg_Q <= D;
2022-09-17 27
Let’s play some tricks
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
always @ (A, B, C, D, sel) begin

if (sel == 2'b00)
reg_Q <= A;
else if (sel == 2'b01)
reg_Q <= B;
reg_Q <= C;
else
reg_Q <= D;
end
endmodule
2022-09-17 28
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;

if (sel == 2'b00)
reg_Q <= A;
reg_Q <= B;
reg_Q <= C;
else
reg_Q <= D;
end
endmodule
2022-09-17 29
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
… // demo_7
always @ (A, B, C, D, sel) begin always @ (A, B, C, D, sel) begin
if (sel == 2'b00) if (sel == 2'b00)
reg_Q <= A; reg_Q <= A;
else if (sel == 2'b01) else if (sel == 2'b01)
reg_Q <= B; reg_Q <= B;
reg_Q <= C; reg_Q <= C;
else else if (sel == 2’b11)
end end
endmodule
2022-09-17 endmodule 30
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
… // demo_7
if (sel == 2'b00) if (sel == 2'b00)
reg_Q <= B; reg_Q <= B; Equivalent
else if (sel == 2'b10) else if (sel == 2'b10) as before?
end end
endmodule
2022-09-17 endmodule 31
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
… // demo_7
if (sel == 2'b00) if (sel == 2'b00)
reg_Q <= B; reg_Q <= B; Equivalent
else if (sel == 2'b10) else if (sel == 2'b10) as before?
end end
endmodule
2022-09-17 endmodule 32
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
… // demo_7
if (sel == 2'b00) if (sel == 2'b00)
else if (sel == 2'b01) else if (sel == 2'b01) Always enclose an if
reg_Q <= B; reg_Q <= B; Equivalent with an else to
else if (sel == 2'b10) else if (sel == 2'b10) as before? avoid auto-generated
reg_Q <= C; reg_Q <= C; latch.
end end
endmodule
2022-09-17 endmodule 33
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;
… // demo_7
if (sel == 2'b00) if (sel == 2'b00)
else if (sel == 2'b01) else if (sel == 2'b01) Always enclose an if
reg_Q <= B; reg_Q <= B; Equivalent with an else to
else if (sel == 2'b10) else if (sel == 2'b10) as before? avoid auto-generated
reg_Q <= C; reg_Q <= C; latch.
end end
endmodule
2022-09-17 endmodule 34
Nested if-else statement
What if we want to do:
1. Q = A when sel == 00
2. Q = B when sel == 01
3. Q = C when all other cases
2022-09-17 35
1. Q = A when sel == 00
2. Q = B when sel == 01
always @ (A, B, C, sel) begin

if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end 2022-09-17 36
1. Q = A when sel == 00
2. Q = B when sel == 01
Way 1 (demo_8)
if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end 2022-09-17 37
1. Q = A when sel == 00
2. Q = B when sel == 01
Way 1 (demo_8) Way 2 (demo_9)

if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end 2022-09-17 38
1. Q = A when sel == 00
2. Q = B when sel == 01

always @ (A, B, C, sel) begin always @ (A, B, C, sel) begin
if (sel == 1'b00) if (sel[1] == 1'b0)
reg_Q <= A; if (sel[0] == 1'b0)
else if (sel == 1'b01) reg_Q <= A;
reg_Q <= B; else
else reg_Q <= B;
reg_Q <= C; else
reg_Q <= C;
end 2022-09-17 end 39
1. Q = A when sel == 00
2. Q = B when sel == 01

if (sel == 1'b00) if (sel[1] == 1'b0)
reg_Q <= A; if (sel[0] == 1'b0)
reg_Q <= B; else
else reg_Q <= B;
reg_Q <= C; else
reg_Q <= C;
end 2022-09-17 end 40
1. Q = A when sel == 00
2. Q = B when sel == 01
Way 1 (demo_8) Way 2 (demo_9) Bad style (demo_10)

if (sel == 1'b00) if (sel[1] == 1'b0)
reg_Q <= A; if (sel[0] == 1'b0)
reg_Q <= B; else
else reg_Q <= B;
reg_Q <= C; else
reg_Q <= C;
end 2022-09-17 end 41
1. Q = A when sel == 00
2. Q = B when sel == 01

always @ (A, B, C, sel) begin always @ (A, B, C, sel) begin always @ (A, B, C, sel) begin
if (sel == 1'b00) if (sel[1] == 1'b0) if (sel == 1'b00)
reg_Q <= A; if (sel[0] == 1'b0) reg_Q <= A;
else if (sel == 1'b01) reg_Q <= A; else if (sel == 1'b01)
reg_Q <= B; else reg_Q <= B;
else reg_Q <= B; else if (sel == 1’b10 || sel == 1’b11 )
reg_Q <= C; else reg_Q <= C;
reg_Q <= C;
end 2022-09-17 end end 42
1. Q = A when sel == 00
2. Q = B when sel == 01

if (sel == 1'b00) if (sel[1] == 1'b0) if (sel == 1'b00)
reg_Q <= A; if (sel[0] == 1'b0) reg_Q <= A;
else if (sel == 1'b01) reg_Q <= A; else if (sel == 1'b01)
reg_Q <= B; else reg_Q <= B;
else reg_Q <= B; else if (sel == 1’b10 || sel == 1’b11 )
reg_Q <= C; else reg_Q <= C;
reg_Q <= C;
end 2022-09-17 end end 43
The depth of an if-else (3-8 decoder)
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
else if (in == 3'b001)
reg_out = 8'h0_2;
reg_out = 8'h0_4;
reg_out = 8'h0_8;
reg_out = 8'h1_0;
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 44
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_2;
reg_out = 8'h0_4;
reg_out = 8'h0_8;
reg_out = 8'h1_0;
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 45
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_2; • If-else statement implicitly implies a
else if (in == 3'b010) priority-based decoding process.
reg_out = 8'h0_4;
reg_out = 8'h0_8;
reg_out = 8'h1_0;
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 46
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
else if (in == 3'b011) • The first if statement is checked first.
reg_out = 8'h0_8;
reg_out = 8'h1_0;
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 47
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
reg_out = 8'h0_8; • Short data path.
reg_out = 8'h1_0;
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 48
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
reg_out = 8'h1_0; • Run fast.
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 49
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
else if (in == 3'b101) • The last if statement is checked last.
reg_out = 8'h2_0;
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 50
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
reg_out = 8'h2_0;
else if (in == 3'b110) • Long data path.
reg_out = 8'h4_0;
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 51
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
reg_out = 8'h2_0;
reg_out = 8'h4_0; • Run slow.
else
reg_out = 8'h8_0;
end // demo_11
2022-09-17 52
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4;
reg_out = 8'h2_0;
else
reg_out = 8'h8_0;
• Performance of the circuit depends
end // demo_11 on input.
2022-09-17 53
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
reg_out = 8'h0_4; Rules of thumb
priority-based No.8:
decoding process.
• The first if statement is checked first.
reg_out = 8'h0_8; Don’t• Short
writedata deep
path. if-else.
reg_out = 8'h2_0;
else
reg_out = 8'h8_0;
2022-09-17 54
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
decoding process.
writedata deep
path. if-else.
reg_out = 8'h1_0; Note the ROM.
• Run fast.
reg_out = 8'h2_0;
else
reg_out = 8'h8_0;
2022-09-17 55
always @ (in) begin
if (in == 3'b000)
reg_out = 8'h0_1;
decoding process.
writedata deep
path. if-else.
reg_out = 8'h1_0; Note the ROM.
• Run fast.
reg_out = 8'h2_0;
How
• Long to
dataimprove?
path.
else
reg_out = 8'h8_0;
2022-09-17 56
Improve deep if-else
2022-09-17 57
• Insight: balance the
HW structure.
2022-09-17 58
HW structure.
• 3’b000 → 8’h01
2022-09-17 59
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
2022-09-17 60
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
2022-09-17 61
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
2022-09-17 62
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
2022-09-17 63
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
2022-09-17 64
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
• 3’b110 → 8’h40
2022-09-17 65
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 66
HW structure.
• 3’b000 → 8’h01
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 67
HW structure.
• 3’b000 → 8’h01
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 68
HW structure.
• 3’b000 → 8’h01
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 69
HW structure.
• 3’b000 → 8’h01
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 70
HW structure.
• 3’b000 → 8’h01
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 71
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 72
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 73
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
in[1]=1
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 74
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
in[1]=1
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 75
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
in[1]=1
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[1]=0
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 76
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
• 3’b010 → 8’h04
in[1]=1
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[1]=0
in[2]=1
• 3’b101 → 8’h20
• 3’b110 → 8’h40
• 3’b111 → 8’h80
2022-09-17 77
HW structure.
• 3’b000 → 8’h01
in[1]=0
in[2]=0
• 3’b001 → 8’h02
in[1]=1
• 3’b010 → 8’h04
• 3’b011 → 8’h08
• 3’b100 → 8’h10
in[1]=0
in[2]=1
• 3’b101 → 8’h20
in[1]=1• 3’b110 → 8’h40
2022-09-17
• 3’b111 → 8’h80 78
always @ (in) begin
if (in[2] == 1'b0)
if(in[1] == 1'b0)
Improve deep if-else if(in[0] == 1'b0)
reg_out = 8'h0_1;
else
reg_out = 8'h0_2;
• Insight: balance the else // in[1] == 1’b1
if(in[0] == 1'b0)
HW structure. reg_out = 8'h0_4;
• 3’b000 → 8’h01 else

reg_out = 8'h0_8;
in[1]=0
in[2]=0
• 3’b001 → 8’h02 else
if(in[1] == 1'b0)
in[1]=1
• 3’b010 → 8’h04 if(in[0] == 1'b0)
reg_out = 8'h1_0;
• 3’b011 → 8’h08 else
reg_out = 8'h2_0;
• 3’b100 → 8’h10 else // in[1] == 1’b1
in[1]=0 if(in[0] == 1'b0)
in[2]=1
• 3’b101 → 8’h20 reg_out = 8'h4_0;
in[1]=1• 3’b110 → 8’h40

else
reg_out = 8'h8_0;
2022-09-17
• 3’b111 → 8’h80 end //demo_12 79
always @ (in) begin
if (in[2] == 1'b0)
if(in[1] == 1'b0)
reg_out = 8'h0_1;
else
reg_out = 8'h0_2;
if(in[0] == 1'b0)
• 3’b000 → 8’h01 else

reg_out = 8'h0_8;
in[1]=0
in[2]=0
• 3’b001 → 8’h02 else
if(in[1] == 1'b0)
in[1]=1
• 3’b010 → 8’h04 if(in[0] == 1'b0)
reg_out = 8'h1_0;
• 3’b011 → 8’h08 else
reg_out = 8'h2_0;
• 3’b100 → 8’h10 else // in[1] == 1’b1
in[1]=0 if(in[0] == 1'b0)
in[2]=1
• 3’b101 → 8’h20 reg_out = 8'h4_0;
in[1]=1• 3’b110 → 8’h40

else
reg_out = 8'h8_0;
2022-09-17
• 3’b111 → 8’h80 end //demo_12 80
always @ (in) begin
if (in[2] == 1'b0)
if(in[1] == 1'b0)
reg_out = 8'h0_1;
else
reg_out = 8'h0_2;
if(in[0] == 1'b0)
• 3’b000Balanced
→ 8’h01 data-path, no ROM.
else
reg_out = 8'h0_8;
in[1]=0
in[2]=0 Hard to tune. Not always possible to balance.
• 3’b001 → 8’h02 else
if(in[1] == 1'b0)
in[1]=1
• 3’b010 → 8’h04 if(in[0] == 1'b0)
reg_out = 8'h1_0;
• 3’b011 → 8’h08 else
reg_out = 8'h2_0;
• 3’b100 → 8’h10 else // in[1] == 1’b1
in[1]=0 if(in[0] == 1'b0)
in[2]=1
• 3’b101 → 8’h20 reg_out = 8'h4_0;
in[1]=1• 3’b110 → 8’h40

else
reg_out = 8'h8_0;
2022-09-17
• 3’b111 → 8’h80 end //demo_12 81
always @ (in) begin
if (in[2] == 1'b0)
if(in[1] == 1'b0)
reg_out = 8'h0_1;
else
reg_out = 8'h0_2;
if(in[0] == 1'b0)
• 3’b000Balanced
→ 8’h01 data-path, no ROM.
else
reg_out = 8'h0_8;
in[1]=0
in[2]=0 Hard to tune. Not always possible to balance.
• 3’b001 → 8’h02 else
if(in[1] == 1'b0)
• 3’b010 → 8’h04
in[1]=1
if(in[0] == 1'b0)
Use case statement. reg_out = 8'h1_0;
• 3’b011 → 8’h08 else
reg_out = 8'h2_0;
• 3’b100 → 8’h10 else // in[1] == 1’b1
in[1]=0 if(in[0] == 1'b0)
in[2]=1
• 3’b101 → 8’h20 reg_out = 8'h4_0;
in[1]=1• 3’b110 → 8’h40

else
reg_out = 8'h8_0;
2022-09-17
• 3’b111 → 8’h80 end //demo_12 82
The “: ?” conditional operator
• Also called as inline if.
• Syntax
condition ? value_if_true : value_if_false
2022-09-17 83
• Syntax
… // demo_4
always @ (D, en) begin
if(!en)
reg_Q <= 1'b0;
else
reg_Q <= D;
end
2022-09-17 84
• Syntax
… // demo_4
if(!en)
reg_Q <= 1'b0;
else
reg_Q <= D;
end
2022-09-17 85
demo_4
• Syntax
… // demo_4
if(!en)
reg_Q <= 1'b0;
else
reg_Q <= D;
end
2022-09-17 86
demo_4
• Syntax
… // demo_4 … // demo_9
always @ (D, en) begin always @ (A, B, C, sel) begin

if (sel == 1'b00)
if(!en) reg_Q <= A;
reg_Q <= 1'b0; else if (sel == 1'b01)
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 87
demo_4
• Syntax
… // demo_4 … // demo_9

if (sel == 1'b00)
if(!en) reg_Q <= A;
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 88
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9

if (sel == 1'b00)
if(!en) reg_Q <= A;
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 89
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13
always @ (D, en) begin always @ (A, B, C, sel) begin assign Q = en ? D : 1’b0;
if (sel == 1'b00)
if(!en) reg_Q <= A; endmodule
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 90
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13
always @ (D, en) begin always @ (A, B, C, sel) begin assign Q = en ? D : 1’b0;
if (sel == 1'b00)
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 91
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13
always @ (D, en) begin demo_11

always @ (A, B, C, sel) begin assign Q = en ? D : 1’b0;
if (sel == 1'b00)
else reg_Q <= B;
reg_Q <= D; else
reg_Q <= C;
end end
2022-09-17 92
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13

if (sel == 1'b00)
else reg_Q <= B; … // demo_14
reg_Q <= D; else
reg_Q <= C; assign Q = sel[1] ? C : (sel[0] ? B : A);
end end endmodule

2022-09-17 93
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13

if (sel == 1'b00)
reg_Q <= D; else
end end endmodule

2022-09-17 94
demo_4 demo_9
• Syntax
… // demo_4 … // demo_9 … // demo_13 demo_12

if (sel == 1'b00)
reg_Q <= D; else
end end endmodule

2022-09-17 95
Case statement
• The case statement checks if the given expression matches
one among the case branches.
• If none of the case matches the given expression, statements within
the default branch are evaluated.
2022-09-17 96
Case statement
case (expression)
case_branch_1 : A
case_branch_2,
case_branch_3 : B
case_branch_4 :
begin
C1, C2
end
default: D
2022-09-17 endcase 97
Case statement
If expression matches case (expression)

case_branch_1 then A case_branch_1 : A
is evaluated case_branch_2,
case_branch_3 : B
case_branch_4 :
begin
C1, C2
end
default: D
2022-09-17 endcase 98
Case statement
If expression matches case (expression)

case_branch_1 then A case_branch_1 : A
is evaluated case_branch_2,
case_branch_3 : B
case_branch_4 :
begin
If expression matches
C1, C2
case_branch_2 or
end
case_branch_3 then B
default: D
is evaluated
2022-09-17 endcase 99
Case statement
case_branch_4 then
If expression matches case (expression) C1 and C2 in the
case_branch_1 then A case_branch_1 : A begin-end block are
is evaluated case_branch_2, evaluated sequentially
case_branch_3 : B
case_branch_4 :
begin
C1, C2
case_branch_2 or
end
default: D
is evaluated
2022-09-17 endcase 100
Case statement
case_branch_4 then
If expression matches case (expression) C1 and C2 in the
case_branch_1 then A case_branch_1 : A begin-end block are
is evaluated case_branch_2, evaluated sequentially
case_branch_3 : B
case_branch_4 :
begin If none of the above
C1, C2 matches, D in the
case_branch_2 or
end default branch is
default: D evaluated.
is evaluated
2022-09-17 endcase 101
Case statement
module demo_6 (
input [1:0] sel,
input A, B, C, D,
output Q);
reg reg_Q;
assign Q = reg_Q;

if (sel == 2'b00)
reg_Q <= A;
reg_Q <= B;
reg_Q <= C;
else
reg_Q <= D;
end
endmodule
2022-09-17 102
Case statement module demo_15 (
input [1:0] sel,
module demo_6 ( input A, B, C, D,
input [1:0] sel, output Q);
input A, B, C, D,
output Q); reg reg_Q;
assign Q = reg_Q;
reg reg_Q;
assign Q = reg_Q; always @ (A, B, C, D, sel) begin
case (sel)
always @ (A, B, C, D, sel) begin 2'b00:
if (sel == 2'b00) reg_Q = A;
reg_Q <= A; 2'b01:
else if (sel == 2'b01) reg_Q = B;
reg_Q <= B; 2'b10:
else if (sel == 2'b10) reg_Q = C;
reg_Q <= C; default:
else reg_Q = D;
reg_Q <= D; endcase
end end
endmodule
2022-09-17 endmodule 103
input [1:0] sel,
module demo_15 (
input [1:0] sel,
module demo_6 ( input A, B, C, D, input A, B, C, D,
input [1:0] sel, output Q); output Q);
input A, B, C, D,
output Q); reg reg_Q; reg reg_Q;
reg reg_Q;
assign Q = reg_Q; always @ (A, B, C, D, sel) begin always @ (A, B, C, D, sel) begin
case (sel) case (sel)
always @ (A, B, C, D, sel) begin 2'b00: 2'b00:
if (sel == 2'b00) reg_Q = A; reg_Q = A;
reg_Q <= A; 2'b01: 2'b01:
else if (sel == 2'b01) reg_Q = B; reg_Q = B;
reg_Q <= B; 2'b10: 2'b10:
else if (sel == 2'b10) reg_Q = C; reg_Q = C;
reg_Q <= C; default: 2’b11:
else reg_Q = D; reg_Q = D;
reg_Q <= D; endcase endcase
end end end
endmodule
2022-09-17 endmodule endmodule 104
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg reg_Q;
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
else if (sel == 2'b10) reg_Q = C; Equivalent reg_Q = C;
end end end
endmodule
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg reg_Q;
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
end end end
endmodule
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg reg_Q;
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
end end end
endmodule
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg reg_Q; Using if-else
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
end end end
endmodule
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
end end end
endmodule
input [1:0] sel,
module demo_15 (
input [1:0] sel,
input A, B, C, D,
reg_Q <= A; 2'b01: 2'b01:
reg_Q <= B; 2'b10: 2'b10:
else Using case reg_Q = D; reg_Q = D;
end end end
endmodule
The depth of a case (3-8 decoder)
always @ (in) begin

case (in)
3'b000: reg_out = 8'h01;
3'b001: reg_out = 8'h02;
3'b010: reg_out = 8'h04;
3'b011: reg_out = 8'h08;
3'b100: reg_out = 8'h10;
3'b101: reg_out = 8'h20;
3'b110: reg_out = 8'h40;
default: reg_out = 8'h80;
endcase
end
2022-09-17 111
always @ (in) begin

case (in)
3'b000: reg_out = 8'h01;
3'b001: reg_out = 8'h02;
3'b010: reg_out = 8'h04;
3'b011: reg_out = 8'h08;
3'b100: reg_out = 8'h10;
3'b101: reg_out = 8'h20;
3'b110: reg_out = 8'h40;
endcase
end
2022-09-17 112
always @ (in) begin

case (in)
3'b000: reg_out = 8'h01;
3'b001: reg_out = 8'h02;
3'b010: reg_out = 8'h04;
3'b011: reg_out = 8'h08;
3'b100: reg_out = 8'h10;
3'b101: reg_out = 8'h20;
3'b110: reg_out = 8'h40;
endcase
end
2022-09-17 113
The don’t-care “?” in case statement
2022-09-17 114

if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end
2022-09-17 115
demo_8
if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end
2022-09-17 116
demo_8
if (sel == 1'b00)
reg_Q <= A;
reg_Q <= B;
else
reg_Q <= C;
end
2022-09-17 117
demo_8
if (sel == 1'b00) case(sel)
reg_Q <= A; 2'b00:
else if (sel == 1'b01) reg_Q = A;
reg_Q <= B; 2'b01:
else reg_Q = B;
reg_Q = C;
end endcase
end
2022-09-17 118
demo_8 demo_16
reg_Q <= A; 2'b00:
reg_Q <= B; 2'b01:
else reg_Q = B;
reg_Q = C;
end endcase
end
2022-09-17 119
demo_8 demo_16
reg_Q <= A; 2'b00:
reg_Q <= B; 2'b01:
else reg_Q = B;
reg_Q = C;
end endcase
end
2022-09-17 120
demo_8 demo_16
if (sel == 1'b00) case(sel) casex(sel) // or casez(sel)
reg_Q <= A; 2'b00: 2'b00:
else if (sel == 1'b01) reg_Q = A; reg_Q = A;
reg_Q <= B; 2'b01: 2'b01:
else reg_Q = B; reg_Q = B;
reg_Q <= C; default: 2’b1?: // for both ’10’ and ’11’
reg_Q = C; reg_Q = C;
end endcase endcase
end end
2022-09-17 121
demo_8 demo_16 demo_16

reg_Q <= A; 2'b00: 2'b00:
reg_Q <= B; 2'b01: 2'b01:
end endcase endcase
end end
2022-09-17 122
demo_8 demo_16 demo_16

reg_Q <= A; 2'b00: 2'b00:
reg_Q <= B; 2'b01: 2'b01:
end endcase endcase
end end
2022-09-17 123
Case, casez, casex
2022-09-17 124
Case, casez, casex
• In Verilog, casez and casex are special case statement.
2022-09-17 125
Case, casez, casex
• In casez
‘Z’ and ‘?’ are treated as don’t-care
in both case expression and case branch
2022-09-17 126
Case, casez, casex
• In casez
• In casex
‘Z’, ‘X’ and ‘?’ are treated as don’t-care
2022-09-17 127
Case, casez, casex
• In casez
• In casex
• In case
‘1’, ‘0’, ‘X’, ‘Z’ are treated as four different values
Don’t use don’t-care in case, use them in casez/casex
2022-09-17 128
Case, casez, casex
• In casez
• In casex
• In case
‘1’, ‘0’, ‘X’, ‘Z’ are treated as four different values
Don’t use don’t-care in case, use them in casez/casex
• In casez and casex, if multiple case branches matches
the expression, the first match dominates.
2022-09-17 129
Examples: case, casex, casez
2022-09-17 130
reg sel = 1'bZ;
initial begin
case(sel)
1'b0:
$display("A");
1'b1:
$display("B");
1'bZ:
$display("C");
1'bX:
$display("D");
default:
$display("default");
endcase
end //demo_17
C
2022-09-17 131
reg sel = 1'bZ;
initial begin
case(sel)
1'b0:
$display("A");
1'b1:
$display("B");
1'bZ:
$display("C");
1'bX:
$display("D");
default:
endcase
end //demo_17
C
2022-09-17 132
reg sel = 1'bZ; reg sel = 1'bX;
initial begin initial begin

case(sel) casez(sel)
1'b0: 1'b0:
$display("A"); $display("A");
1'b1: 1'b1:
$display("B"); $display("B");
1'bZ: 1’bZ:
$display("C"); $display("C");
1'bX: 1’b?:
$display("D"); $display("D");
default: 1'bX:
$display("default"); $display("E");
endcase default:
end //demo_17 $display("default");
endcase
end //demo_18
C C
2022-09-17 133
reg sel = 1'bZ; reg sel = 1'bX;
initial begin initial begin

case(sel) casez(sel)
1'b0: 1'b0:
$display("A"); $display("A");
1'b1: 1'b1:
$display("B"); $display("B");
1'bZ: 1’bZ:
$display("C"); $display("C");
1'bX: 1’b?:
$display("D"); $display("D");
default: 1'bX:
$display("default"); $display("E");
endcase default:
end //demo_17 $display("default");
endcase
end //demo_18
C C
2022-09-17 134
reg sel = 1'bZ; reg sel = 1'bX; reg sel = 1'bX;
initial begin initial begin initial begin

case(sel) casez(sel) casez(sel)
1'b0: 1'b0: 1'b0:
$display("A"); $display("A"); $display("A");
1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX:
$display("C"); $display("C"); $display("C");
1'bX: 1’b?: 1'bZ:
$display("D"); $display("D"); $display("D");
default: 1'bX: 1'b?:
$display("default"); $display("E"); $display("E");
endcase default: default:
end //demo_17 $display("default"); $display("default");
endcase endcase
end //demo_18 end //demo_19
C C C
2022-09-17 135
reg sel = 1'bZ; reg sel = 1'bX; reg sel = 1'bX;
initial begin initial begin initial begin

case(sel) casez(sel) casez(sel)
1'b0: 1'b0: 1'b0:
$display("A"); $display("A"); $display("A");
1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX:
$display("C"); $display("C"); $display("C");
1'bX: 1’b?: 1'bZ:
$display("D"); $display("D"); $display("D");
default: 1'bX: 1'b?:
$display("default"); $display("E"); $display("E");
endcase default: default:
end //demo_17 $display("default"); $display("default");
endcase endcase
end //demo_18 end //demo_19
C C C
2022-09-17 136
reg sel = 1'bZ; reg sel = 1'bX; reg sel = 1'bX; reg sel = 1'bZ;
initial begin initial begin initial begin initial begin

case(sel) casez(sel) casez(sel) casez(sel)
1'b0: 1'b0: 1'b0: 1'b0:
$display("A"); $display("A"); $display("A"); $display("A");
1'b1: 1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX: 1'bX:
$display("C"); $display("C"); $display("C"); $display("C");
1'bX: 1’b?: 1'bZ: 1'bZ:
$display("D"); $display("D"); $display("D"); $display("D");
default: 1'bX: 1'b?: 1'b?:
$display("default"); $display("E"); $display("E"); $display("E");
endcase default: default: default:
end //demo_17 $display("default"); $display("default"); $display("default");
endcase endcase endcase
end //demo_18 end //demo_19 end //demo_20
C C C A
2022-09-17 137
reg sel = 1'bZ; reg sel = 1'bX; reg sel = 1'bX; reg sel = 1'bZ;
initial begin initial begin initial begin initial begin

case(sel) casez(sel) casez(sel) casez(sel)
1'b0: 1'b0: 1'b0: 1'b0:
$display("A"); $display("A"); $display("A"); $display("A");
1'b1: 1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX: 1'bX:
$display("C"); $display("C"); $display("C"); $display("C");
1'bX: 1’b?: 1'bZ: 1'bZ:
$display("D"); $display("D"); $display("D"); $display("D");
default: 1'bX: 1'b?: 1'b?:
$display("default"); $display("E"); $display("E"); $display("E");
endcase default: default: default:
end //demo_17 $display("default"); $display("default"); $display("default");
endcase endcase endcase
end //demo_18 end //demo_19 end //demo_20
C C C A
2022-09-17 138
reg sel = 1'bZ; reg sel = 1'bX; reg sel = 1'bX; reg sel = 1'bZ; reg sel = 1'bX;
initial begin initial begin initial begin initial begin initial begin
case(sel) casez(sel) casez(sel) casez(sel) casex(sel)
1'b0: 1'b0: 1'b0: 1'b0: 1'b0:
$display("A"); $display("A"); $display("A"); $display("A"); $display("A");
1'b1: 1'b1: 1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX: 1'bX: 1'bX:
$display("C"); $display("C"); $display("C"); $display("C"); $display("C");
1'bX: 1’b?: 1'bZ: 1'bZ: 1'bZ:
$display("D"); $display("D"); $display("D"); $display("D"); $display("D");
default: 1'bX: 1'b?: 1'b?: 1'b?:
$display("default"); $display("E"); $display("E"); $display("E"); $display("E");
endcase default: default: default: default:
end //demo_17 $display("default"); $display("default"); $display("default"); $display("default");
endcase endcase endcase endcase
end //demo_18 end //demo_19 end //demo_20 end //demo_21
C C C A A
2022-09-17 139
1'b0: 1'b0: 1'b0: 1'b0: 1'b0:
1'b1: 1'b1: 1'b1: 1'b1: 1'b1:
$display("B"); $display("B"); $display("B"); $display("B"); $display("B");
1'bZ: 1’bZ: 1'bX: 1'bX: 1'bX:
1'bX: 1’b?: 1'bZ: 1'bZ: 1'bZ:
default: 1'bX: 1'b?: 1'b?: 1'b?:
C C C A A
2022-09-17 140
1'b0: 1'b0: 1'b0: 1'b0: 1'b0:
1'b1: 1'b1: 1'b1: 1'b1: 1'b1:
$display("B");
1'bZ: All don’t-cares are non-synthesizable.
$display("B");
1’bZ:
$display("B");
1'bX:
$display("B");
1'bX:
$display("B");
1'bX:
1'bX: 1’b?: 1'bZ: 1'bZ: 1'bZ:
default: 1'bX: 1'b?: 1'b?: 1'b?:
C C C A A
2022-09-17 141
2022-09-17 142
reg sel = 1'bX;
always @ (sel) begin

casex(sel)
1'b0:
$display("A");
1'b1:
$display("B");
1'bX:
$display("C");
1'bZ:
$display("D");
1'b?:
$display("E");
default:
endcase
end //demo_22
always doesn’t trigger

2022-09-17 143
reg sel = 1'bX;

casex(sel)
1'b0:
$display("A");
1'b1:
$display("B");
1'bX:
$display("C");
1'bZ:
$display("D");
1'b?:
$display("E");
default:
endcase
end //demo_22

2022-09-17 144
reg sel = 1'bX;

casex(sel)
1'b0:
$display("A");
1'b1:
$display("B");
Default value is
1'bX:
$display("C"); indeed ‘X’.
1'bZ:
$display("D");
1'b?:
$display("E");
default:
endcase
end //demo_22

2022-09-17 145
Finite state machines
2022-09-17 146
• A digital system can generally be divided into control
unit and datapath.
2022-09-17 147
unit and datapath.
• For example, in a processor circuit:
2022-09-17 148
unit and datapath.
• For example, in a processor circuit:
2022-09-17 149
2022-09-17 150
• FSM is a method to model control logic.
2022-09-17 151
• An FSM consists of combinational, sequential and output logic.
2022-09-17 152
1. The combinational logic is used to decide the next state of the FSM.
2022-09-17 153
Next state
Logic
2022-09-17 154
Next state
Logic
2022-09-17 155
Next state
Logic
2022-09-17 156
Next state
Logic
input
2022-09-17 157
2. The sequential logic is used to store the current state of the FSM.
Next state
Logic
input
2022-09-17 158
Next state Current state

Logic Logic
input
2022-09-17 159

Logic Logic
D Q
D_FF
input
clk
2022-09-17 160

Logic Logic
D Q
D_FF
input
clk
2022-09-17 161
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 162
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 163
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 164
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 165
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 166
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 167
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 168
clk
3. The output logic is used to generate output based on the current state of the FSM.

Logic Logic
D Q
D_FF
input
clk
2022-09-17 169
clk
Next state Current state Output Logic

Logic Logic
D Q
D_FF
input
clk
2022-09-17 170
clk

Logic Logic
D Q
D_FF
input
clk
2022-09-17 171
clk

Logic Logic
D Q D Q
D_FF D_FF
input
clk clk
2022-09-17 172
clk

Logic Logic
D Q D Q
D_FF D_FF
input
clk clk
2022-09-17 173
clk

Logic Logic
D Q D Q
D_FF D_FF
input
clk clk
2022-09-17 174
clk

Logic Logic
D Q D Q
D_FF D_FF
input
clk clk
2022-09-17 175
clk

Logic Logic
D Q D Q
D_FF D_FF
input
clk clk
2022-09-17 176
clk

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 177
clk

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 178
clk

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 179
clk
• W
ithout taking the input Type Moore

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 180
clk
• W
ithout taking the input Type Moore

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 181
clk
• W
• With input (green line) Type Mealy

Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
2022-09-17 182
clk
How to design an FSM
2022-09-17 183
1. Specification analysis
2022-09-17 184
2. Create state diagrams
2022-09-17 185
• Choose type Moore or Mealy
2022-09-17 186
• Minimize state diagram using Karnaugh map (out of scope here)
2022-09-17 187
3. Assign codes for states
2022-09-17 188
• One-hot? Binary? Gray code?
2022-09-17 189
4. Design seq-logic for storing the next state
2022-09-17 190
5. Design the output logic
2022-09-17 191
• May use both combi- and seq-logic for output generation
2022-09-17 192
6. Design combi-logic for calculating the next state
2022-09-17 193
6. Design combi-logic for calculating the next state
• Core of the FSM
2022-09-17 194
FSM Mini project – Traffic light control
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Traffic
light 2 with
Specification car sensor
Oscar wants a system containing two

traffic lights, governing a junction of
two (one-way) streets.
1. In the default case, traffic light 1
is green, traffic light 2 is red. Traffic
light 1
2. When a car is detected at traffic
light 2, the system switches traffic
light 1 to red, light 2 to green,
waits some amount of time for
the car to pass.
3. Then the system switches back
to the default situation.
2022-09-17 196
Specification analysis
2
2022-09-17 197
• First thing first, how traffic light works? 2
2022-09-17 198
• Traffic lights change their colors in the same
order every time.
2022-09-17 199
order every time.
1. Red light on: This tells drivers to stop.
1
2022-09-17 200
order every time.
2.Green light on: This means the driver can start driving
or keep driving. 1
2022-09-17 201
order every time.
or keep driving. 1
3. Yellow light on: This tells drivers to stop when it
is safe to, because the light is about to turn red.
2022-09-17 202
order every time.
or keep driving. 1
2022-09-17 203
order every time.
or keep driving. 1
• In our case:
2022-09-17 204
order every time.
or keep driving. 1
• In our case:
• Car comes
2022-09-17 205
order every time.
or keep driving. 1
• In our case:
• Car comes
• Light 1: Green Yellow Red
2022-09-17 206
order every time.
2.Green light on: This means the driver can start
1
driving or keep driving.
3. Yellow light on: This tells drivers to stop
when it is safe to, because the light is about
to turn red.
• In our case:
• Car comes
2022-09-17
• Light 2: Red (wait) → Green 207
order every time.
1
to turn red.
• In our case:
• Car comes
2022-09-17
order every time.
1
to turn red.
• In our case:
• Car comes T
2022-09-17
order every time.
1
to turn red.
• In our case:
• Car leaves
• Car comes T
2022-09-17
order every time.
1
to turn red.
• In our case:
• Car leaves
• Car comes T
• Light 1: Red (wait) → Green
2022-09-17
order every time.
1
to turn red.
• In our case:
• Car leaves
• Car comes T
• Light 1: Red (wait) → Green
• Light 1: Green Yellow Red • Light 2: Green → Yellow → Red
2022-09-17
Create state diagrams
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S1
L1: Green
L2: Red
2022-09-17 214
Sensor input
car_sensor
S1
L1: Green
L2: Red
2022-09-17 215
Sensor input
car_sensor
S1
L1: Green
L2: Red
2022-09-17 216
Sensor input S2
car_sensor L1: Yellow
L2: Red
S1
L1: Green
L2: Red
2022-09-17 217
Sensor input S2 5s
L2: Red
S1
L1: Green
L2: Red
2022-09-17 218
Sensor input S2 5s
L2: Red
S1
L1: Green
L2: Red
2022-09-17 219
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
2022-09-17 220
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
2022-09-17 221
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
30s
2022-09-17 222
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
S4
L1: Red
L2: Yellow 30s
2022-09-17 223
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
S4
L1: Red
L2: Yellow 30s
2022-09-17 224
Sensor input S2 5s
L2: Red
S1 S3
L1: Green L1: Red
L2: Red L2: Green
S4
L1: Red
5s L2: Yellow 30s
2022-09-17 225
Sensor input S2 5s
L2: Red
Let’s code
S1
the FSM together inS3Vivado
L1: Green L1: Red
L2: Red L2: Green
S4
L1: Red
5s L2: Yellow 30s
2022-09-17 226
Assign codes for states
2022-09-17 227
`timescale 1ms / 1ms
module traffic(
input car_sensor,
input clk,
input n_rst,
output [2:0] light_1, // 3: Red, 2: Yellow, 1: Green
output [2:0] light_2 // 3: Red, 2: Yellow, 1: Green
);
2022-09-17 228

Freq for a traffic light.
module traffic( This affect later how we
input car_sensor, design our counter to
input clk, count time.
input n_rst,
);
2022-09-17 229
//------------ Codes for states ------------
localparam
S_1 = 4'b0001,
S_2 = 4'b0010,
S_3 = 4'b0100,
S_4 = 4'b1000;
reg [2:0] reg_light_1;
assign light_1 = reg_light_1;
input n_rst,
reg [3:0] cur_state;
);
reg [3:0] next_state;
integer counter;
reg counter_enable;
2022-09-17 230
//------------ Codes for states ------------
localparam We use
S_1 = 4'b0001, one-hot code.
S_2 = 4'b0010, You can choose other
S_3 = 4'b0100, coding style, too.
S_4 = 4'b1000;
input n_rst,
);
integer counter;
reg counter_enable;
2022-09-17 231
//------------ Codes for states ------------
localparam We use
S_4 = 4'b1000;
`timescale 1ms / 1ms Internal driving
Freq for a traffic light. signals.
input n_rst,
);
integer counter;
reg counter_enable;
2022-09-17 232
//------------ Codes for states ------------
localparam We use
S_4 = 4'b1000;
`timescale 1ms / 1ms Internal driving
Freq for a traffic light. signals.
input n_rst, The counter is used
output [2:0] light_1, // 3: Red, 2: Yellow, 1: Green to count time between
output [2:0] light_2 // 3: Red, 2: Yellow, 1: Green light changes.
); The counter is only
enabled when we are
integer counter; in S_2, S_3, and S_4
reg counter_enable;
2022-09-17 233
Design seq-logic for storing the next state
//------------ Seq logic -----------------------------------

always @ (posedge clk, negedge n_rst) begin
if (!n_rst) begin
cur_state <= S_1;
end else begin
cur_state <= next_state;
end
end
2022-09-17 234
Nothing but a
asynchronous reset
D_FF.
//------------ Seq logic -----------------------------------
if (!n_rst) begin
cur_state <= S_1;
end else begin
cur_state <= next_state;
end
end
2022-09-17 235
Nothing but a
asynchronous reset
D_FF.
//------------ Seq logic -----------------------------------
if (!n_rst) begin
cur_state <= S_1;
end else begin
cur_state <= next_state; Reset to S_1.
end
end
2022-09-17 236
Nothing but a
asynchronous reset
D_FF.
//------------ Seq logic -----------------------------------
if (!n_rst) begin
cur_state <= S_1;
end else begin
cur_state <= next_state; Reset to S_1.
end
end
Store next state on

each clock edge.
2022-09-17 237
Design the output logic
//------------ Output logic --------------------------------

if (!n_rst) begin
reg_light_1 <= 3'b111;
reg_light_2 <= 3'b111;
end else begin
case(cur_state)
S_1: {reg_light_1, reg_light_2} <= {3'b001, 3'b100};
endcase
end
end
2022-09-17 238
Design the output logic
//------------ Output logic -------------------------------- When reset, both Light_1 and Light_2 turn all
always @ (posedge clk, negedge n_rst) begin lights on to test if they work properly.
if (!n_rst) begin
reg_light_1 <= 3'b111; Note! At this moment, the cur_state is also
reg_light_2 <= 3'b111; reset to S_1, but that can only pass to the
end else begin output logic 1 cycle later.
case(cur_state)
endcase
end
end
2022-09-17 239
Design the output logic Next state Current state Output Logic
Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
clk
if (!n_rst) begin
case(cur_state)
endcase
end
end
2022-09-17 240
Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
clk
if (!n_rst) begin
case(cur_state)
S_4: {reg_light_1, reg_light_2} <= {3'b100, 3'b010}; S_1: Light 1 green, Light 2 red
endcase S_2: Light 1 yellow, Light 2 red (car comes!)
end S_3: Light 1 red, Light 2 green
end S_4: Light 1 red, Light 2 yellow
2022-09-17 241
Logic Logic
D Q D Q output
D_FF D_FF
input
clk clk
clk
if (!n_rst) begin
case(cur_state)
S_4: {reg_light_1, reg_light_2} <= {3'b100, 3'b010}; S_1: Light 1 green, Light 2 red
endcase S_2: Light 1 yellow, Light 2 red (car comes!)
end S_3: Light 1 red, Light 2 green
end S_4: Light 1 red, Light 2 yellow
2022-09-17 242
Design combi-logic for calculating the
next state
2022-09-17 243
next state
• We need a counter to counter the
time between
2022-09-17 244
next state
• We need a counter to counter the time
between
• S_2 and S_3
(duration of the yellow light Light 1)
Car comes at Light 2
2022-09-17 245
next state
between
• S_2 and S_3
• S_3 and S_4
(duration of the green light Light 2)
Car goes through
2022-09-17 246
next state
between
• S_2 and S_3
• S_3 and S_4
Car goes through
• S_4 and S_1
Car leaves, back to zero
2022-09-17 247
next state
between
• S_2 and S_3
• S_3 and S_4
Car goes through
• S_4 and S_1
• The counter is turned on when we
change from S_1 to S_2.
2022-09-17 248
next state
time between
• S_2 and S_3
• S_3 and S_4
Car goes through
• S_4 and S_1
• The counter is turned on when we
change from S_1 to S_2.
• The counter is turned off and reset
to 0 when we change from S_4 to
S_1.
2022-09-17 249
next state
//------------ Counter logic -------------------------------
time between always @ (posedge clk, negedge n_rst) begin
• S_2 and S_3 if (!n_rst) begin
Car comes at Light 2 counter <= 0;
• S_3 and S_4 end else begin
(duration of the green light Light 2) if (counter_enable) begin
Car goes through counter <= counter + 1;
(duration of the yellow light Light 2) if (counter != 0)
Car leaves, back to zero counter <= 0;
• The counter is turned on when we end
change from S_1 to S_2. end
end
• The counter is turned off and reset
to 0 when we change from S_4 to
S_1.
2022-09-17 250
next state
//------------ Counter logic -------------------------------
time between always @ (posedge clk, negedge n_rst) begin
• S_2 and S_3 if (!n_rst) begin
Car comes at Light 2 counter <= 0;
(duration of the green light Light 2) if (counter_enable) begin
Car goes through counter <= counter + 1;
(duration of the yellow light Light 2) if (counter != 0)
Car leaves, back to zero counter <= 0;
• The counter is turned on when we end
change from S_1 to S_2. end 1. S_2 sets counter_enable to
end true
• The counter is turned off and reset 2. counter_enable remains true
to 0 when we change from S_4 to in S_3 and S_4
S_1. 3. S_1 sets counter_enable to
2022-09-17 false 251
next state
2022-09-17 252
next state
//------------ Combinational function
always @ (cur_state, car_sensor, counter) begin
case( cur_state)
S_1: begin
if (car_sensor) begin
next_state = S_2;
counter_enable = 1'b1;
end else begin
next_state = cur_state;
counter_enable = 1’b0;
end
end
...
endcase
end
2022-09-17 253
next state
//------------ Combinational function
always @ (cur_state, car_sensor, counter) begin
case( cur_state)
S_1: begin
next_state = S_2;
end else begin
end
end 1. If car comes, next_state is S_2 and
... we set the counter on.
endcase 2. Other wise we hold at S_1.
end 3. The second counter_enable = 1’b0
is used to turn off the counter when
2022-09-17 we change from S_4 to S_1. 254
next state S_2: begin
//------------ Combinational function if (counter == 5_000)
always @ (cur_state, car_sensor, counter) begin next_state = S_3;
else
case( cur_state) next_state = cur_state;
S_1: begin end
next_state = S_2;
end else begin
end
else
S_1: begin end
if (car_sensor) begin S_3: begin
next_state = S_2; if (counter == 35_000)
counter_enable = 1'b1; next_state = S_4;
end else begin else
next_state = cur_state; next_state = cur_state;
counter_enable = 1’b0; end
end
else
S_1: begin end
end else begin else
end
end 1. If car comes, next_state is S_2 and S_4: begin
... we set the counter on. if (counter == 40_000)
endcase 2. Other wise we hold at S_1. next_state = S_1;
end 3. The second counter_enable = 1’b0 else
is used to turn off the counter when next_state = cur_state;
2022-09-17 we change from S_4 to S_1. end 257
1. Wait the counter to
count 5000 cycles
(1 ms per cycle)
else
2. Then change
next_state to S_3
S_1: begin end
end else begin else
end
count 5000 cycles
(1 ms per cycle)
else
2. Then change
next_state to S_3
S_1: begin end
if (car_sensor) begin S_3: begin 1. Wait the counter to
next_state = S_2; if (counter == 35_000) count 30_000
counter_enable = 1'b1; next_state = S_4; cycles more (1 ms
end else begin else per cycle)
next_state = cur_state; next_state = cur_state; 2. Then change
counter_enable = 1’b0; end next_state to S_4
end
count 5000 cycles
(1 ms per cycle)
else
2. Then change
next_state to S_3
S_1: begin end
if (car_sensor) begin S_3: begin 1. Wait the counter to
next_state = S_2; if (counter == 35_000) count 30_000
counter_enable = 1'b1; next_state = S_4; cycles more (1 ms
end else begin else per cycle)
next_state = cur_state; next_state = cur_state; 2. Then change
counter_enable = 1’b0; end next_state to S_4
end
end 1. If car comes, next_state is S_2 and S_4: begin 1. Wait the counter to
... we set the counter on. if (counter == 40_000) count 5_000 cycles
endcase 2. Other wise we hold at S_1. next_state = S_1; more (1 ms per
end 3. The second counter_enable = 1’b0 else cycle)
is used to turn off the counter when next_state = cur_state; 2. Then change
2022-09-17 we change from S_4 to S_1. end next_state
260to S_1
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
#1 n_rst = 1;
#100 car_sensor = 1;
#1000000 car_sensor = 1;
end
always #0.5 clk = ~clk;
2022-09-17 261
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
#1 n_rst = 1; Drive the reset signal.
#1000000 car_sensor = 1;
end
2022-09-17 262
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
#1000000 car_sensor = 1;
end
2022-09-17 263
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
Simulate car arrivals.
#1000000 car_sensor = 1; Sensor signal lasts for 200 ms (0.2s).
end
2022-09-17 264
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
end
2022-09-17 265
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
end
always #0.5 clk = ~clk; Drive the clock signal.

Clock cycle is 1 ms.
2022-09-17 266
Testbench
initial begin
clk = 0;
n_rst = 1;
car_sensor = 0;
#1 n_rst = 0;
end
always #0.5 clk = ~clk; Drive the clock signal.

Clock cycle is 1 ms.
2022-09-17 267
Waveform – FSM reset
2022-09-17 268
2022-09-17 269
n_rst negedge arrives
1. light_1, light_2 turn all the lights on (3’b111) to
check if they can be lit up properly.
2. cur_state is reset to S_1
• next_state is set to S_1 in the combi-logic
3. counter is reset to 0
• counter_enable is set to 0 in the combi-logic
2022-09-17 270
3. counter is reset to 0
• counter_enable is set to 0 in the combi-logic
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3. counter is reset to 0 n_rst
• counter_enable is set to 0 in the combi-logic leaves
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3. counter is reset to 0 n_rst
• counter_enable is set to 0 in the combi-logic leaves
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The first posedge clk since n_rst
leaves. The FSM begins to work.
n_rst negedge arrives 1. Counter logic is disabled.
1. light_1, light_2 turn all the lights on (3’b111) to 2. cur_state, car_sensor, counter
check if they can be lit up properly. all remain silent, FSM combi-logic
2. cur_state is reset to S_1 remains silent. next_state holds.
• next_state is set to S_1 in the combi-logic 3. cur_state holds.
3. counter is reset to 0 n_rst 4. Output updated to the ones for
• counter_enable is set to 0 in the combi-logic leaves S_1. Light 1 green, light 2 red.
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Waveform – Car comes, state change S_1 to S_2
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car_sensor arrives, combi-logic triggers.

next_state = S_2, counter_enable = 1’b1.
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Clock posedge arrives. FSM state changes.
cur_state = next_state (S_2). Counter
starts to count.

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Clock posedge arrives. FSM state changes.
cur_state = next_state (S_2). Counter
starts to count.

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Clock posedge arrives. FSM state changes. Output updated 1 cycle later. Light 1 is
cur_state = next_state (S_2). Counter yellow. Light 2 is red.
starts to count. Max 2 ms lagging between car arrival event
and traffic light changes.

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Waveform – State change S_2 to S_3
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Counter counts 5,000 cycles (5 s).

next_state changes from S_2 to
S_3.
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S_3.
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FSM changes cur_state to S_3 in
the following cycle.

S_3.
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S_3.
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Counter counts 5,000 cycles (5 s). Output changes 1 cycle later. Light 1
next_state changes from S_2 to is red, Light 2 is green.
S_3.
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Counter counts 30,000 cycles more

(30 s). next_state changes from S_3
to S_4.
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to S_4.
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to S_4.
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to S_4.
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Output changes 1 cycle later. Light 1
Counter counts 30,000 cycles more is red, Light 2 is yellow.
(30 s). next_state changes from S_3 Don’t miss it, hurry up!
to S_4.
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Counter counts 5,000 cycles more (5 s).

next_state changes from S_4 to S_1.
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counter_enable set to 1’b0.

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counter_enable set to 1’b0.

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counter_enable set to 1’b0. Output changes 1 cycle later. Light 1
is Green, Light 2 is Red.
Counter reset.
Counter counts 5,000 cycles more (5 s). Back to square one.
2022-09-17 302
Counter reset.
Why not reset the

counter directly at
the combi-logic?
2022-09-17 303
Counter reset.
Rules of thumb No.9:
Each reg should only be driven by one always block.
Why not reset the

counter directly at
the combi-logic?
2022-09-17 304
Questions?
2022-09-17 305

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Accelerating Systems with

Programmable Logic Components

Yuan Yao, yuan.yao@it.uu.se

always @ (posedge clk) begin

always @ (posedge clk) begin

reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q;

always @ (posedge clk) begin always @ (posedge clk,

reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q;

always @ (posedge clk) begin always @ (posedge clk,

reg reg_Q; reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q; assign Q = reg_Q;

endmodule endmodule endmodule

reg reg_Q; reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q; assign Q = reg_Q;

endmodule endmodule endmodule

reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q;

always @ (D, en) begin always @ (D, en) begin

reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q;

always @ (D, en) begin always @ (D, en) begin

reg reg_Q; reg reg_Q;

assign Q = reg_Q; assign Q = reg_Q;

always @ (D, en) begin always @ (D, en) begin

reg reg_Q; reg reg_Q; • If enabled, the output

reg reg_Q; reg reg_Q; • If enabled, the output

reg reg_Q; reg reg_Q; • If enabled, the output

reg reg_Q; reg reg_Q; • If enabled, the output

Always enclose an if with an beginelse to

always @ (A, B, C, D, sel) begin

always @ (A, B, C, D, sel) begin

always @ (A, B, C, sel) begin

Way 1 (demo_8) Way 2 (demo_9)

Way 1 (demo_8) Way 2 (demo_9)

Way 1 (demo_8) Way 2 (demo_9)

Way 1 (demo_8) Way 2 (demo_9) Bad style (demo_10)

Way 1 (demo_8) Way 2 (demo_9) Bad style (demo_10)

Way 1 (demo_8) Way 2 (demo_9) Bad style (demo_10)

• 3’b000 → 8’h01 else

in[1]=1• 3’b110 → 8’h40

• 3’b000 → 8’h01 else

in[1]=1• 3’b110 → 8’h40

in[1]=1• 3’b110 → 8’h40

in[1]=1• 3’b110 → 8’h40

always @ (D, en) begin

always @ (D, en) begin

always @ (D, en) begin

always @ (D, en) begin always @ (A, B, C, sel) begin

always @ (D, en) begin always @ (A, B, C, sel) begin

always @ (D, en) begin always @ (A, B, C, sel) begin

always @ (D, en) begin demo_11

always @ (D, en) begin demo_11

end end endmodule

always @ (D, en) begin demo_11

end end endmodule

always @ (D, en) begin demo_11

end end endmodule

If expression matches case (expression)

If expression matches case (expression)

always @ (A, B, C, D, sel) begin

always @ (in) begin