12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

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AURIX™ TC3xx startup file analysis

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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

Author: Zhang Chi, Infineon AURIX™ Technical Expert

Startup file flow chart

TC3xx series MCU will start from the _START() function of the Ifx_Ssw_Tc0.c file after reset,
and will start to run from CPU0 when starting, until the _StartUpSoftware_Phase6()
function will start other cores in sequence according to user configuration.

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_START()

The address of _START() is determined by RESET in the link file. Taking TASKING as an
example, in the Link file:

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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

#define RESET 0xA0000000

This address must also be consistent with the definition of the application start address in
BMHD.

_START() code analysis

void _START(void)

Ifx_Ssw_jumpToFunction(__StartUpSoftware); // 直接跳转到__StartUpSoftware()

_StartUpSoftware()

_StartUpSoftware() is mainly used to set the A1 register, set the PSW register, and
determine whether it is Application Reset, so as to perform different jumps.

In TriCore™, A0, A1, A8, and A9 are global address registers. The area pointed to by A1
here is used to store small RODATA. The so-called small data area can be directly
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The default value of PSW is set to 0x980, namely Supervise mode, Global Address Register content
Write Permission Enable, Call Depth Count Enable, User Stack. Zhihu has high-quality questions,
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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

_StartUpSoftware() code analysis:

static void __StartUpSoftware(void)

Ifx_Ssw_setAddressReg(a1, __SDATA2(0)); // A1指向small data区域

Ifx_Ssw_MTCR(CPU_PSW, IFX_CFG_SSW_PSW_DEFAULT); // 设置CPU0的PSW寄存器

if (Ifx_Ssw_isApplicationReset() != 1)

Ifx_Ssw_jumpToFunction(__StartUpSoftware_Phase2);

}
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Ifx_Ssw_jumpToFunction(__StartUpSoftware_Phase3ApplicationResetPath);
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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge
_StartUpSoftware_Phase2()
In this API, the initial configuration of EVRC, LBIST test, and MONBIST test will be
performed according to the user's configuration.
IFX_CFG_SSW_CALLOUT_PMS_INIT()
IFX_CFG_SSW_CALLOUT_LBIST()
IFX_CFG_SSW_CALLOUT_MONBIST()
_StartUpSoftware_Phase2() code analysis
static void __StartUpSoftware_Phase2(void)
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Whether to execute or not depends on the
configuration of
IFX_CFG_SSW_ENABLE_PMS_INIT in
Ifx_Cfg_Ssw.h. This function is used to
execute the startup process of EVRC. The
default EVRC GATE driver output frequency
is 1.8MHz, which can be changed to 800kHz
output through this API. The function called
by this API is in IfxPmsEvr.h, so to perform
this test, you need to add this LLD file to the
project
Whether to execute depends on the
configuration of
IFX_CFG_SSW_ENABLE_LBIST in
Ifx_Cfg_Ssw.h. This function is used to
perform LBIST test, and LBIST is used to test
the internal logic circuit of the chip. LBIST
can also be executed in BootROM. The
function called by this API is in IfxScuLbist.h,
so to perform this test, you need to add this
LLD file to the project
Whether to execute depends on the
configuration of
IFX_CFG_SSW_ENABLE_MONBIST in
Ifx_Cfg_Ssw.h. This function is used to
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perform a self-test of the secondary voltage
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monitor circuit. The function called by this content
API is in Ifx_Ssw_Infra.c, so to perform this
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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge
/* Power and EVRC configurations */
IFX_CFG_SSW_CALLOUT_PMS_INIT();
/* LBIST Tests and evaluation */
IFX_CFG_SSW_CALLOUT_LBIST();
/* MONBIST Tests and evaluation */
IFX_CFG_SSW_CALLOUT_MONBIST();
Ifx_Ssw_jumpToFunction(__StartUpSoftware_Phase3PowerOnResetPath);
IFX_CFG_SSW_CALLOUT_PMS_INIT()
IFX_CFG_SSW_CALLOUT_LBIST()
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// 执行EVC初始化流程
// 执行LBIST测试
// 执行MONBIST测试
Whether to execute or not depends on the
configuration of
IFX_CFG_SSW_ENABLE_PMS_INIT in
Ifx_Cfg_Ssw.h. This function is used to
execute the startup process of EVRC. The
default EVRC GATE driver output frequency
is 1.8MHz, which can be changed to 800kHz
output through this API. The function called
by this API is in IfxPmsEvr.h, so to perform
this test, you need to add this LLD file to the
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configuration of Zhihu has high-quality questions,
IFX_CFG_SSW_ENABLE_LBIST in professional answers, in-depth articles
Ifx_Cfg_Ssw.h. This function is used to and exciting videos from more than 50
million creators.
perform LBIST test, and LBIST is used to test
the internal logic circuit of the chip. LBIST
can also be executed in BootROM. The
function called by this API is in IfxScuLbist.h,
6/17
12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

so to perform this test, you need to add this

LLD file to the project

Whether to execute depends on the

IFX_CFG_SSW_CALLOUT_MONBIST()
configuration of
IFX_CFG_SSW_ENABLE_MONBIST in
Ifx_Cfg_Ssw.h. This function is used to
perform a self-test of the secondary voltage
monitor circuit. The function called by this
API is in Ifx_Ssw_Infra.c, so to perform this
test, you need to add this LLD file to the
project

_StartUpSoftware_Phase3PowerOnResetPath()

In this API, the context will be initialized. The so-called context is the SP pointer and CSA.

In TriCore™, SP is the A10 register, where the top address of the stack will be assigned to
A10.

CSA is the area where the context is stored. In TriCore™, whenever a sub-function is called
or an interrupt is entered, some general-purpose registers will be automatically stored in
the CSA area (Push), and then these registers will be stored when the sub-function returns
or the interrupt returns. Resume (Pop).

_StartUpSoftware_Phase3ApplicationResetPath code analysis:

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_StartUpSoftware_Phase4

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In this API, it will first feed the CPU0 watchdog and safety watchdog (note: CPU0
watchdog and safety watchdog are enabled after reset), and then complete the clock
initialization and MBIST test according to user configuration.

static void __StartUpSoftware_Phase4(void)

/* This is for ADAS chip, where clock is provided by MMIC chip. This has to be

* implemented according the board.

*/

IFX_CFG_SSW_CALLOUT_MMIC_CHECK();

/* Update safety and cpu watchdog reload value*/

unsignedshort cpuWdtPassword = Ifx_Ssw_getCpuWatchdogPasswordInline(&MODULE_SCU.

unsignedshort safetyWdtPassword = Ifx_Ssw_getSafetyWatchdogPasswordInline();

/* servicing watchdog timers */

Ifx_Ssw_serviceCpuWatchdog(&MODULE_SCU.WDTCPU[0], cpuWdtPassword);

Ifx_Ssw_serviceSafetyWatchdog(safetyWdtPassword);

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/* Initialize the clock system */
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IFX_CFG_SSW_CALLOUT_PLL_INIT();
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/* MBIST Tests and evaluation */

IFX_CFG_SSW_CALLOUT_MBIST();

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Ifx_Ssw_jumpToFunction(__StartUpSoftware_Phase5);

Whether to execute depends on the

configuration of
IFX_CFG_SSW_ENABLE_PLL_INIT in
Ifx_Cfg_Ssw.h, this function is used to
IFX_CFG_SSW_CALLOUT_PLL_INIT()
initialize the PLL configuration. The function
called by this API is in IfxScuCcu.c, so to
initialize the PLL, you need to add this LLD
file to the project

Whether to execute depends on the

IFX_CFG_SSW_CALLOUT_MBIST()
configuration of
IFX_CFG_SSW_ENABLE_MBIST in
Ifx_Cfg_Ssw.h. This function is used to
perform the MBIST test, which is used for
hardware self-testing of the RAM area. The
function called by this API is in IfxMtu.c, so
to perform this test, you need to add this
LLD file to the project

_StartUpSoftware_Phase5

In this API, there is only one API configured by SMU, but this API is just an empty
function, so nothing is actually done here.

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IFX_CFG_SSW_ENABLE_TRICORE1 1: Start Core1, 0: Do not start Core1

IFX_CFG_SSW_ENABLE_TRICORE2 1: Start Core2, 0: Do not start Core2

IFX_CFG_SSW_ENABLE_TRICORE3 1: Start Core3, 0: Do not start Core3

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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

The BHALT bit of the SYSCON register is used to set whether the Core is started, the PC is
used to set the program pointer, and these two registers are set in Ifx_Ssw_startCore() to
start other cores.

_StartUpSoftware_Phase6() code analysis:

static void __StartUpSoftware_Phase6(void)

/* Start remaining cores as a daisy-chain */

#if (IFX_CFG_SSW_ENABLE_TRICORE1 != 0)

Ifx_Ssw_startCore(&MODULE_CPU1, (unsigned int)&__Core1_start); // 启动core 1

#endif/* #if (IFX_CFG_CPU_CSTART_ENABLE_TRICORE1 != 0)*/

#if (IFX_CFG_SSW_ENABLE_TRICORE1 == 0)

#if (IFX_CFG_SSW_ENABLE_TRICORE2 != 0)

Ifx_Ssw_startCore(&MODULE_CPU2, (unsigned int)&__Core2_start); // 启动core 2

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#if (IFX_CFG_SSW_ENABLE_TRICORE2 == 0)
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#if (IFX_CFG_SSW_ENABLE_TRICORE3 != 0)
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Ifx_Ssw_startCore(&MODULE_CPU3, (unsigned int)&__Core3_start); // 启动core 3

#endif

#endif/* #if (IFX_CFG_SSW_ENABLE_TRICORE2 == 0) */

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#endif/* #if (IFX_CFG_SSW_ENABLE_TRICORE1 == 0) */

Ifx_Ssw_jumpToFunction(__Core0_start);

_Ifx_Ssw_startCore() code analysis:

void Ifx_Ssw_startCore(Ifx_CPU *cpu, unsigned int programCounter)

/* Set the PC */

cpu->PC.B.PC = (unsigned int)programCounter >> 1U; // 设置PC

/* release boot halt mode if required */

Ifx_CPU_SYSCON syscon;

syscon = cpu->SYSCON;

if (syscon.B.BHALT)

syscon.B.BHALT = 0U; // 启动内核

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Taking TC38x as an example, if all 4 cores are started, CORE1 will be started in
_StartUpSoftware_Phase6(). At this time, _Core0_Start() and __Core1_Start() are running at
the same time. At the end of _Core1_Start(), Core2 will be started, and then jump to

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_Core2_Start(). At the end of _Core2_Start(), Core3 will be started, and then jump to
_Core3_Start().

_Corex_start

Take _Core0_Start() as an example. In _Core0_Start(), PCACHE and DCACHE will be enabled

according to the configuration, A0, A8, A9 addresses will be set, Trap and interrupt vector
table start addresses will be configured, interrupt stack pointers will be configured, and
global variables will be initialized. .

CACHE configuration:

Whether to enable CACHE, by configuring the following two macros:

IFX_CFG_SSW_ENABLE_TRICORE0_PCACHE 1: enable PCACHE, 0: disable PCACHE

IFX_CFG_SSW_ENABLE_TRICORE0_DCACHE 1: enable DCACHE, 0: disable DCACHE

Enable PCACHE by configuring the PCBYP bit of PCON0:

Enable DCACHE by configuring PCBYP of DCON0:

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Trap and interrupt vector configuration:

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The BTV register is used to set the first address of the Trap vector table. In the project, the
first address of the Trap vector table is set in the link file. The following statement will
assign the address of the Trap vector table in the link file to BTV.

Ifx_Ssw_MTCR(CPU_BTV, (unsigned int)__TRAPTAB(0));

The BIV register is used to set the first address of the interrupt vector table. In the project,
the first address of the interrupt vector table is set in the link file. The following statement
will assign the address of the interrupt vector table of the link file to BIV. Note that in
TriCore™, by default, the interrupt vector is 32-byte aligned, and the position of the
interrupt vector is not fixed, but determined by the interrupt priority.

Ifx_Ssw_MTCR(CPU_BIV, (unsigned int)__INTTAB(0));

Configure ISTACK:

In TriCore™, the stack is divided into USTACK and ISTACK. Their use is determined by the
PSW.IS bit. The default configuration PSW.IS=0 means that when the function call in the
thread, the USTACK (A11) part will be used as the CPU Stack, and ISTACK (ISP) will be
used as the CPU stack in the interrupt function. USTACK and ISTACK size and position are
configured in the Link file. The following statement sets the ISP:

/* Interrupt stack pointer is configured */

Ifx_Ssw_MTCR(CPU_ISP, (unsigned int)__ISTACK(0));

For CPU0, the USTACK stack top pointer has been assigned to A10 in
_StartUpSoftware_Phase3ApplicationResetPath(). For other CPUs, assign the top pointer of
USTACK to A10 of the respective CPUs in their respective _Corex_Start().

Initialize global variables:

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The following function is used to initialize global variables (this function is implemented content
by the compiler), and the global variables are divided into two parts: Data and BSS.
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global variable.

BSS: The BSS segment is used to store global variables without initialization values. In this
function, global variables without initialization values ​will be cleared.

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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

/* Initialization of C runtime variables */

Ifx_Ssw_C_Init();

For other _Corex_Start(), the process is basically the same as _Core0_Start(), and the
operation of assigning the USTACK stack top pointer to A10 and PSW initialization
operation are added.

The _Corex_Start() of each CPU will finally jump to the respective corex_main() to run.

AURIX™ has added a new partner - the software I have "RT-Thread Auto"

Recently, Ruiside Technology, a leading domestic core software manufacturer in China,

announced that RT-Thread commercially supports Infineon Technologies' automotive-
grade 32-bit AURIX™ TriCore™ multi-core microcontrollers, which can help users
seamlessly use TriCore™ processors. RT-Thread makes full use of the powerful
performance of AURIX™ multi-core to provide users with an easy-to-use operating
system development environment and capabilities such as OTA, CAN/CAN FD/LIN;
combined with the upcoming ISO26262 ASIL-D functional safety certification, RT-Thread
Auto for MCU provides an optional high-security, cost-effective commercial OS solution
for many application scenarios in the automotive field.

RT-Thread is a technology platform integrating real-time operating system (RTOS) kernel,

middleware components and developer community. At the same time, it is also a
complete and rich component, highly scalable, easy development, ultra-low power
consumption, and high security. IoT operating system. The software has all the key
components required for an industrial operating system platform, such as GUI, TCP/IP
v4/v6 dual-stack network protocol stack, secure transmission, low-power components,
USB, POSIX, C++, etc. After more than ten years of accumulation and development, RT-
Thread has formed one of the largest embedded open source communities in China, with
a cumulative installed capacity of more than 1 billion units. It has become a domestically
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developed, mature and stable open source RTOS with a large installed capacity.
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With the development of vehicle electrification, intelligence, and networking, the
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and more complex. At this time, more consideration needs to be given to the integration
of functional modules, and thus higher requirements are placed on the performance of
the MCU. AURIX™ multi-core microcontroller is a series of 32-bit multi-core
microcontrollers launched by Infineon that meet the various requirements of powertrain
and safety applications in the automotive industry, because of its powerful functions, high

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safety, high reliability, and rich network interfaces It is widely used in automotive
applications such as smart driving gateways, engine management systems, transmission
systems, chassis and braking systems, and airbags.

For AURIX™ multi-core microcontrollers, RT Thread can support up to 6 cores, and also
supports the lock-step core features:

• 6 TriCore™ cores running at 300 MHz (with 4 additional checker cores providing 4000
DMIPS)
• Floating-point and fixed-point support for all cores
• 16 MB Flash/ECC protected
• Up to 6.9 MB SRAM/ECC protected
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• Supports ISO 26262 ASIL-D
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• RT-Thread version that supports multi-core features, while continuing the easy-to-use
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TASKING tool chain (and ADS integrated development environment) million creators.

Zhang Lihong, Senior Marketing Manager of the Automotive Electronics Division of

Infineon Technologies Greater China, said: "It is a great pleasure for Ruiside Technology to
join the Infineon Automotive Electronics ecosystem. Infineon AURIX™ series
microcontrollers, with their powerful real-time performance, The excellent design of

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12/31/22, 7:20 AM Demystification | AURIX™ TC3xx startup file analysis-Knowledge

information security has been widely welcomed by customers. Infineon has also been
committed to building a strong ecosystem to help our customers complete the design
more conveniently and quickly. Ruiside Technology's operating system RT-Thread has a
great impact on AURIX ™ series single-chip microcomputer support and
commercialization, is a major breakthrough of domestic RTOS in the field of automotive
electronics."

Xiong Puxiang, CEO of Ruiside Technology: "As a leading core software supplier in China,
Ruiside Technology's commercial support for Infineon's multi-core represents that the
domestic operating system has entered a new field, RT-Thread It can meet the multi-core
high-reliability requirements of the automotive grade."

About Ruiside Technology

Ruiside Technology enjoys a high reputation in the domestic operating system field. It is
the actual owner and development direction controller of RT-Thread, and is responsible
for the core technology development, community operation and marketing of RT-Thread
operating system. The company has a series of independent intellectual property rights
technologies, including high-reliability RTOS, log-type high-reliability file system, low
power consumption technology, Persimmon GUI graphics library, intelligent audio, etc.

About Infineon

Infineon Technologies AG is the world's leading semiconductor technology company, we

make people's life more convenient, safe and environmentally friendly. Infineon's
microelectronics products and solutions will lead you to a bright future. In the 2020 fiscal
year (ending September 30), the company's sales amounted to 8.5 billion euros and it has
approximately 46,700 employees worldwide. In April 2020, Infineon officially completed
the acquisition of Cypress Semiconductor Corporation, successfully becoming one of the
top ten semiconductor manufacturers in the world.

To learn more about Infineon's AURIX™ TC3xx , please visit Infineon's official website:
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