AIR UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

LAB# 02

Lab Title: Implementation of half adder, full adder and ALU.

Student Name: Abdur-Rehman Reg. No: 210312

Objective: The main objective of this lab is to well-aware about the Xilinx software, step to
run Xilinx software and to verify the truth tables of adders and ALU operations.

Submitted to: Mam Ayesha Sadiq

LAB ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory

Attributes
(5) (4) (3) (2) (1)
Ability to Conduct
Experiment
Ability to assimilate the
results
Effective use of lab
equipment and follows
the lab safety rules

Total Marks: Obtained Marks:

LAB REPORT ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory
Attributes
(5) (4) (3) (2) (1)

Data presentation

Experimental results

Conclusion

Total Marks: Obtained Marks:

Date: Signature:
1: Implement a Half Adder using Xilinx. Also mention its truth table, mathematical
modeling (includes equations etc.) and block diagram.

`CODE:
timescale 1ns / 1ps
module HALFADDER(A,B,C_out,Carry);
input A,B;
output C_out,Carry;
xor(C_out, A,B);
and(Carry, A,B);
endmodule

Truth table:

HALF ADDER

INPUT: OUTPUT:

A B C_out Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Block diagram:

Figure 1 Half adder

 Figure 2 Half Adder circuit

2: Implement a Full Adder using Xilinx. Also mention its truth table, mathematical.
modeling (includes equations etc.) and block diagram.

CODE:
module FULLADDEER(input A,
input B,
input Cin,
output Sum,
output Cout
);

assign {Cout, Sum} = A + B + Cin;

endmodule

Truth table:

Truth table
Input Output
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Block Diagram:

Figure 3Full Adder

Figure 4 Full adder circuit

Wave form:

3: Implement a Half adder using either NAND gate or NOR gate. Verify waveform of
above gates by writing test module.

Code:

`timescale 1ns / 1ps

module half_adderf(input A, input B, output Sum, output Carry);

assign Sum = ~(~A & ~B) & ~(A & B);
assign Carry = A & B;

endmodule

Test bench

`timescale 1ns / 1ps

module Half_adder_tb;
// Inputs
reg A;
reg B;
// Outputs
wire Sum;
wire Carry;

// Instantiate the Unit Under Test (UUT)

half_adderf uut (
.A(A),
.B(B),
.Sum(Sum),
.Carry(Carry)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0;
B = 1;
#100;
A = 1;
B = 0;
#100;
A = 1;
B = 1;

// Add stimulus here

end

endmodule

Wave form:

Block Diagram:

Figure 5 Half Adder

 Figure 6 Full Adder NAND circuit

Task 2:
Part a: Implement an ALU that will perform 8 operations.

Code:

module ALU(ALU_out,A,B,ALU_sel);
input[7:0]A,B;
input[2:0]ALU_sel;
output reg[9:0]ALU_out;
always@(*)
begin
case(ALU_sel)
3'b000:ALU_out=A+B;
3'b001:ALU_out=A-B;
3'b010:ALU_out=A*B;
3'b011:ALU_out=A/B;
3'b100:ALU_out=A>>B;
3'b101:ALU_out=A<<B;
3'b110:ALU_out=A&B;
3'b111:ALU_out=A|B;
default:
ALU_out=A+B;
endcase
end

endmodule
Part b: Implement a 4x1 Multiplexer.

Code:

module MUX(
input [3:0] D,
input [1:0] S,
output Y
);

assign Y = (S == 2'b00) ? D[0] :

(S == 2'b01) ? D[1] :
(S == 2'b10) ? D[2] :
(S == 2'b11) ? D[3] :
1'b0;
endmodule

Circuit Diagram:

Figure 7 4*1 Multiplexer

Wave form:
Conclusion:

In conclusion, the implementation of half adder, full adder, and ALU on Verilog provides a solid
foundation for designing and implementing digital circuits.

A half adder is a basic building block of digital circuits that is used to add two binary digits and
produce a sum and carry output. Its implementation on Verilog is straightforward and requires only a
few lines of code.

A full adder is a more complex circuit that is used to add three binary digits and produce a sum and
carry output. Its implementation on Verilog can be done using either basic logic gates or more
advanced operations, such as using a carry lookahead adder.

An ALU, or arithmetic logic unit, is a circuit that performs various arithmetic and logic operations on
binary data. Its implementation on Verilog can be done using a combination of half adders, full
adders, and other logic gates, such as AND, OR, XOR, and NOT gates.

Overall, Verilog provides a flexible and efficient way to design and implement digital circuits, and the
implementation of half adder, full adder, and ALU on Verilog provides a strong foundation for further
study and exploration in the field of digital circuits and computer architecture.