physical aware synthesis :dc_shell-topo Tools: Synopsys:Design compiler Cadence:Genus

Synthesis: The process of converting RTL code into optimized gate level netlist
physical aware synthesis : In order to minimize the congestion and better timing and better
utilization
Inputs:
RTLcode
lib
upf
sdc
techlef
floorplan def
I)analyze: read the RTL description and check for syntax error //input:RTL code
II)elaborate: design compiler convertes the rtl description into technology independent GTECH
cells (GENERIC GATES) which contains basic gates and flops // input: RTL code+lib
at elaborate stage we don’t have timing and functionality informatoin and we don’t know at what
technology we are going to manufacture our chip
ISSUES:
1.linking issues:
RTL code has to be linking with corresponding technology independent GTECH library
If RTL code is not linking with corresponding technology independent library then we will have
linking issues : like unresolved reference error
2.pins mismatch error: If pins are missing in library file then we have to intimate lib team then they
have to update the library file
3.Bus width increases more than the specified value
Example : P1-RTLtage has -bus width [31.0]
p2-RTL tag has-bus width [20:0]
then by default design compiler converted remaining has to be connected to vss
Example: For suppose if we have available bus width [20:0] but we require bus width[31:0] at that
time we have to update the library file
read verilog =analyze+elaborate+pre optimize
III)specify constraints //read sdc
1.Timing constraints: create clock, create generated clock,set clock latency,set clock transition,set
max delay,set min delay
2.I/O constraints : set input delay,set output delay
3.DRV’S: set max transition, set max capacitance, set max fanout
4.Environmental conditions: Wire load model, pvt conditions, drive strength,operating conditions
we are considering zero wire load model in synthesis because in synthesis actual clock routing is
not done
IV)clock gating : Insert clock gating between elaborate stage and compile stage //Inorder to save
the dynamic power.
This information we will see in compile log file. Command:compile_ultra -gated_clock
V)compile stage: //inputs :techlef, floorplan def //command :read floorplan def, read techlef
1.Mapping: The process of converting technology independent gates into technology dependent
gates. Here technology is assigned to GTECH gates
2.Optimization:
I.Timing
2.Power
3.Area
1.Timing optimization: In synthesis design compiler automatically upsize/downsize to meet the
timing if it work ok otherwise go for manually creating path groups
path groups: The paths which are slack violating consider them as a group and give a weightage
those paths so that tool will focus more on those slack violating paths in order to meet the timing
command:dc_shell-topo>group_path -start points IN3 -end point FF2 -weightage 2.5
if it works ok otherwise go for critical path re synthesis
command:compile_timing_effort high
2.Area optimization:
For area optimization design compiler automatically done below this

Architecutral optimiation:
 Resource sharing
 operate reordering
 Sharing common subexpressions
Manually done: Boundary optimization command:set boundary_opto
3.Power optimization:Insert clock gating between elaborate stage and compile stage inorder to
save the dynamic power // command:compile_ultra -gated_clock
VI) DFT logic insertion //COMMAND:insert_dft
First compile netlist is given to dft team they will insert scan flops,scan chain length, scan
input/output and they will give scan information in ddc format
VII) outputs :
.v (gate level netlist)
.sdc(synopsys design constraints)
.scan def
VII) report file generation
Report area
Report power
Report qor
Report timing