Comprehensive Physical Design Guide

Advanced Digital Design

Introduction to CMOS & Layout
Introduction to CMOS & Layout
Introduction to CMOS & Layout
RTL Synthesis & Pre-Layout STA
Introduction to DFT
IC Manufacturing
IC Manufacturing
 Manufacturing Defect
Defect:
Physical manufacturing error which can
cause chip to malfunction.
Short circuited source/drain of transistor
caused by metal spike through.
Power or ground short
Open interconnect on the die caused by
dust particles
 Design, Verification and Test

Design synthesis:
Given a function, develop a procedure to manufacture a device using known materials and
processes.
Verification:
Predictive analysis to ensure that the synthesized design, when manufactured, will perform the
given function.
Functional and Structural
Test:
A manufacturing step that ensures that the physical device, manufactured from the synthesized
design, has no manufacturing defect.
 IC Testing
Test:
Verifies correctness of manufactured hardware.
Two-part process: –
Test generation: software process executed once during design
Test application: electrical tests applied to hardware

Test application performed on every manufactured device.

Responsible for quality of devices
IC Testing Scheme
Test Point Insertion
Test Point Insertion
Test Point Insertion
Convert a Memory Element to a
Scan Cell
Convert a Memory Element to a
Scan Cell
 Why Scan Design?

Makes internal circuit access much more direct to allow for controllability and
observability
Converts a sequential test generation problem into a combinational test generation
problem
Enables automatic test pattern generation (ATPG)
Enables use of low-pincount, low cost testers (ATE)
 How do we test a 25bit AND gate:

•
Functional testing:
●
Test all input patterns and cross check
corresponding output pattern with
intended pattern.
 How do we test a 25bit AND gate:
Functional testing:
• Need to apply 2^25 patterns
• Time taken to test all patterns with 1MHz
tester is 62 years.
 Defect, Fault and Fault Model

Real defects too numerous and often not analyzable

A defect manifests itself as a fault
A fault is modeled by a fault model

A fault model,
– identifies targets for testing
– makes analysis possible
 Different types of fault models:

Stuck-at-fault (single)
Stuck open fault
Delay fault
Bridging fault
Memory fault
Functional fault
Analog fault etc.,
 Levels of Fault Models
● Physical Defects
● Silicon Defects
● Photolithographic Defects
● Mask Contamination
● Process Variation
● Defective Oxides
● Electrical Effects
● Shorts (Bridging Faults)
● Opens
● Transistor Stuck-On/Open
● Resistive Shorts/Opens
● Change in Threshold Voltages
● Logical Effects
● Logical Stuck-at 0/1
● Slower Transition (Delay Faults)
● AND-bridging, OR-bridging
 Stuck At Fault
Stuck at 0 model (SA0):
Stuck at 0 model (SA0): represent a signal
that is permanently low regardless of
other control signals.
Stuck at 1 model (SA1):
Stuck at 1 model (SA1): represent a signal
that is permanently high regardless of
other control signals.
 Detecting stuck at faults:
Controlling target node to the opposite of stuck at value
Making the nodes fault effect observable by controlling the value at all other nodes
affecting the output response.
 SA faults on AND gate:

To check SA1 on A pin, I/P pattern need to check is A: 0 B: 1

To check SA0 on B Pin, I/P pattern we need to use is A: 1 B: 1

Patterns that need for various SA faults are:
SA Fault Sensitization and
Propagation
SA Fault Sensitization and
Propagation
SA Fault Sensitization and
Propagation
SA Fault Sensitization and
Propagation
 Bridging Faults

The fault model of bridging faults considers short circuits between two wires of a circuit

Occurs when two or more signal lines in a circuit are accidentally connected together
Due to imperfection during layout fabrication.
If an element is short to power (VDD) or ground (VSS), it is equivalent to the stuck-at
fault model
 Bridging Faults
Bridging faults in a transistor-level circuit may occur between the terminals of a
transistor or between two or more signal lines.
These can be further classified into two types: 
wired-AND bridging 
wired-OR bridging.

A=1, B=0
 Bridging Faults

Bridging faults at the gate level ca be

classified into two types: 
◦ Input Bridging 
◦
corresponds to the shorting of a certain
number of primary input lines
◦

◦ Feedback Bridging.
◦
Occurs if there is a short between an
output and an input line.
◦
May cause a circuit to oscillate, or it may
convert it into a sequential circuit.
Bridging Faults
 Stuck Open Fault

A single transistor is permanently stuck in an

open state
It's detection requires two vectors while
modelling

Stuck open fault of a pmos can be modelled

as a s-a-1 fault at the corresponding input
signal
Stuck open fault of an nmos can be modelled
as a s-a-0 fault at the corresponding input
signal
Stuck Open Fault
 Transistor Stuck On

Here, N transistor is always on

May cause ambiguous logic level

Depends on the relative impedances of
the pull-up and pull-down networks
When Input Is Low in the example,
● both P and N transistors are conducting,

● causing increased quiescent current,

called IDDQ fault
 Transistor Stuck On
Depending on the sizing of the transistors involved
● the path behaves like a voltage divider,

● and in spite of the fault the output may obtain the correct logic value

The fault cannot be detected by observing primary outputs but only by a current
measurement
In extreme case the faulty path may result in a very high current flow, such that the chip
immediately will be destroyed
 Transistor Stuck Open

Transistor stuck-open
May cause the output to be floating
The faulty cell has sequential behavior
Stuck-open might require two vector tests
 Transistor Stuck Open

Here, Transistor T3 never conducts,

corresponding to a stuck-at-0 at T3
As a consequence,
● using input a = 1 and b = 1

● output y of the NAND gate is not connected

to VDD neither to VSS

y is an isolated node and for a certain time the
node will maintain the last valid signal value.
the behavior of the faulty NAND gate becomes
sequential
it behaves like a dynamic memory cell
 Pseudo-Stuck-At Fault Model for
IDDQ testing
Similar to single stuck-at fault model,
except that every cell output is considered observable by IDDQ testing
The fault site at a gate input requires sensitization and propagation to an output of the
same gate
(but not to an output of the circuit) in order to be given credit for IDDQ fault detection
 Pseudo-Stuck-At Fault Model for
IDDQ testing
The exhaustive pseudo-stuck-at patterns
for IDDQ testing cover all leakage faults in
fully complementary combinational CMOS
circuits
 Scan Insertion:
Step1: swap regular flip-flops/registers to scan equivalents.
Step2: form single or multiple scan chains
●
Each scan chain has
●
Primary input as input
●
Primary output as output
Step3: Scan chain reordering
Scan Testing:

Step1: testing chain integrity

●
Set scan mode
●
Bit pattern input as scan-in
●
Scan out (bit pattern) == scan in ( bit pattern), (after N clock delay)
●
N is no of flops in scan chain
Scan Testing:
Step2: Shift Cycle:
◦ FF are in scan chain mode and SE is asserted
◦ O/P of scan FF = Pseudo Primary input (controllable points)

◦ Required bit patterns for combinatorial I/P’s are programmed by passing through scan
chain.
Scan Testing:
Step3: Capture Cycle:
◦ FF are in functional mode and SE is de asserted
◦ Outputs of combinational logic are captured in FFs
Scan Testing:
Step4: Shift cycle:
◦ FF are in scan mode and SE is asserted.
◦ I/P of scan FF = Pseudo Primary O/P (observable output)
◦ Logic at D inputs are captured, passed through scan chains to primary outputs.
Delay Faults

Higher proportion of the defects are timing related

Defect spectrum now includes more problems such as
● High impedance shorts,
● In-line resistance, and
● Crosstalk between signals
A delay fault causes excessive delay along a path such that the total propagation delay
falls outside the specified limit

Not always detected with stuck-at tests

 1.The pattern's launch event may
propagate a 0-to-1 (rising edge)
transition along a specific path
2.While holding all other conditions
constant
3.Then the capture event pulses a
functional clock to latch in the path's
response to the transition
4.If the “high” value was not detected
at the capture point in time, the
path fails the test

Considered to have a “slow-to-rise”

defect
◦ Path A-P-Q-R-D is tested for rising
transition at pin A.
◦ Small delay defects distributed along the
path will be tested if the cumulative delay
exceeds specification.
launch-off-shift

◦ The last shift of the scan chain load

also serves as the transition launch
event

◦ The critical timing is the time from

that last shift (or launch) clock to the
capture clock
launch-off-shift

◦ The scan enable signal (SE) must be able to turn off very quickly after the last shift
clock and let logic settle before the capture clock occurs.
◦ For that reason, the scan enable signal usually needs to be routed as a clock signal
to accomplish this.
◦ Depending on the design frequency required for the test, the scan chains
themselves might also be required to shift at system frequencies.
◦ This can be a limitation because most scan chain shifting is done at lower
frequencies. If the chains are shifted and tested at-speed, this could result in an
unnecessary yield loss.
◦ The main advantage of this launch-off-shift approach is that it only requires the
ATPG tool to create combinational patterns, which are quicker and easier to
generate.
broadside
◦ The entire scan data shifting can be
done at slow speeds in test mode,
and then two at-speed clocks are
pulsed for launch and capture in
functional mode.
◦ Once the values are captured, the
data can be shifted out slowly in test
mode
◦ The main advantages of this
approach are that it does not require
scan chains to shift at-speed or the
SE signal to perform as a high-speed
clock.
◦ The main disadvantage is that the
ATPG problem is now a sequential
one, which can increase the test
pattern generation time and might
result in a higher pattern count
Introduction to Physical Design Flow
Methodology Overview
IC Compiler II High Level Design Flow
– Set up the libraries and prepare
the design data
– Perform design planning and
power planning
– Perform placement and
optimization
– Perform clock tree synthesis and
optimization
– Perform routing and postroute
optimization
– Perform chip finishing and design
for manufacturing tasks
– Save the design
 Power Intent Concepts
Unified Power Format (UPF) specify the power intent for multivoltage designs
– Establishes a set of commands to specify the low-power design intent
– Specify supply network, switches, isolation, retention, and other power
management aspects
UPF provides a way to specify power requirements, without explicitly stating their
implementations
Specify
– how to create a power supply network,
– the behavior of supply nets with respect to each other, and
– how the logic functionality is extended to support dynamic power switching to
design elements
UPF
Design Planning