019722, 159 AM How to calculate the “Drive Adjustment” value in the timing report How to calculate th “Drive Adjustment” value in the timing report Problem Whats ‘Drive Adjustment” in he timing report and how does Tempus /Innovus calculate this value? Solution ‘To model the driving capability ofthe extemal driver, the timing analyzer computes an offset tothe arrival ime ofan input and changes the slew time used to compute the delay for the next cel, ‘To understand the drive adjustment, refer tothe folowing diagram ofa block withthe “int input por, which is connected to an an external river: ‘To model the driving capability of an extemal diver connected to an input por, the se*_driving_cel1 command is used as shown in the following constraints defined for ths block: create_clock ~period 10 [get_ports ctkL set_input_delay 5 -clock cikI [get_ports inl] set_driving_cell -1ib cell SUFX2 From pin A -pin ¥ (gat_ports int] ‘To model the delay by loading eect. following two delay values are required: 4. Delay of BUFX2 with zero output load: This delay will be the intrinsic call dlay. The intrinsic delay is calculated internally by the tool. 2. Delay of BUFX2 with load: The load (total cap) inthis case is 0.00089160 (wite cap + input pin cap of ANDIB), “These two delay are shown in the folowing diagram: ‘The orive adjustment delay atthe “int” input por of the block i the diference between the call delay withthe load and the cell delay with zero load, which is @ - ©. “The ofive adjustment is the “load-dependent delay” ofthe driving cel. Load-dependent delay = total delay of cell - intrinsic delay (zero-load) ‘The input delay and drive adjustment are shown inthe following diagram: hitpsueuppor.cadence.com/apex/ArcleAtlachmen'Portal?id=a1 Os0000007MSpgEAG&pageName=ArteleContent 12019722, 1159 AM How to calculate the “Drive Adjustment” value in the timing report #1 ¢-Transition Time atthe port eee xem ry BBE pajcmont-@)-@ clock input a ‘The input delay ofS ns isthe delay from the external clock pinto the delay trp point atthe rise signal at the output pin ofthe driving cel with zero load, ‘You can refer tothe fllowing figure to easily understand the relationship between the timing report and these diagrams: Path 1s WE Sotap Chosk vith Pan KSI/OE Enopint: BSI/D (4) checked vith leading edge of ‘cll’ Tegingoint= inl (5) triggeved by leading alge of 'ellt” Path Groupes jell} Analysie Vion: setup fume Other EM Artval Tine o.com ‘raneton Tia ae port + Sotuy 180 = Phase Shieh s0.cona 2 4 CRE Aajuetnent on ee a tune acrstnnt= @) - @) + eit ie yan oe tai amd 1. rise delay with the load =0.1019 ns mae sie ee 2. rise delay w/ zero load=0.0085 ns Clock Fiee age: 9.0000 Drive Adjustment = 0.1019 — 0.0985 1 ips Blo a0 =0 004ns 1 ive sie tet eigoint Acie} tae HSH ining Beh Vsstace toe GU) Neh fossa |e | Tie | Tine | sal 1 line Fink int 99.6643 | ham 4 Faw int 18 ONDA 0.cUUP | 0.0m | SHURE | 99.6642 1 Fain FS 5 PT AMMO | vise AND HY | O.OM5 1 0.c0m8 1 0.1487 | 5.2481 | 98.6090 1 rn) 1 SoRRHQRL | 13 | 6.0415 | 0.c008 | 6.0mm | 5.1481 1 99.8090 1 ‘Return to the top of the page cleContent 22 hitpseupport.cadence.com/apexiAricleAtlachmen'Portal?id=a1 Od0000007MSpgEAGBpageNam