Digital Electronics, Chapter 5

1. If the waveforms in Figure 7–70 are applied to an active-HIGH S-R latch, draw the resulting Q
output waveform in relation to the inputs. Assume that Q starts LOW.

2. For a gated S-R latch, determine the Q and Q outputs for the inputs in Figure 7–73. Show them
in proper relation to the enable input. Assume that Q starts LOW.

3. Determine the output of a gated D latch for the inputs in Figure 7–74.

4. Two edge-triggered J-K flip-flops are shown in Figure 7–77. If the inputs are as shown, draw
the Q output of each flip-flop relative to the clock, and explain the difference between the two.
The flip-flops are initially RESET.

5. For a positive edge-triggered D flip-flop with the input as shown in Figure 7–81, determine the
Q output relative to the clock. Assume that Q starts LOW.
Digital Electronics, Chapter 5

6. Determine the Q waveform relative to the clock if the signals shown in Figure 7–83 are applied
to the inputs of the J-K flip-flop. Assume that Q is initially LOW.

7. For a negative edge-triggered J-K flip-flop with the inputs in Figure 7–84, develop the Q output
waveform relative to the clock. Assume that Q is initially LOW.

8. The following serial data are applied to the flip-flop through the AND gates as indicated in
Figure 7–85. Determine the resulting serial data that appear on the Q output. There is one clock
pulse for each bit time. Assume that Q is initially 0 and that PRE and CLR are HIGH. Rightmost
bits are applied first.
J1: 1 0 1 0 0 1 1; J2: 0 1 1 1 0 1 0; J3: 1 1 1 1 0 0 0; K1: 0 0 0 1 1 1 0; K2: 1 1 0 1 1 0 0;
K3: 1 0 1 0 1 0 1
9. For the circuit in Figure 7–85, complete the timing diagram in Figure 7–86 by showing the Q
output (which is initially LOW). Assume PRE and CLR remain HIGH.
Digital Electronics, Chapter 5

10. For the circuit in Figure 7–89, determine the maximum frequency of the clock signal for
reliable operation if the set-up time for each flip-flop is 3 ns and the propagation delays (tPLH
and tPHL) from clock to output are 6 ns for each flip-flop.

11. A D flip-flop is connected as shown in Figure 7–90. Determine the Q output in relation to the
clock. What specific function does this device perform?

Figure 7–90
12. For the serial in/serial out shift register, determine the data-output waveform for the data-input
and clock waveforms in Figure 8–50. Assume that the register is initially cleared.
Digital Electronics, Chapter 5

13. Solve Problem 12 for the waveforms in Figure 8–51.

14. Develop the Q0 through Q7 outputs for a 74HC164 shift register with the input waveforms
shown in Figure 8–53

15. The shift register in Figure 8–54(a) has SHIFT/LOAD and CLK inputs as shown in part (b).
The serial data input (SER) is a 0. The parallel data inputs are D0 = 1, D1 = 0, D2 = 1, and
D3 = 0 as shown. Develop the data-output waveform in relation to the inputs.

16. The waveforms in Figure 8–55 are applied to a 74HC165 shift register. The parallel inputs are
all 0. Determine the Q7 waveform.
Digital Electronics, Chapter 5

17. Determine all the Q output waveforms for a 74HC195 4-bit shift register when the inputs are as
shown in Figure 8–56.

18. Determine the Q outputs of a 74HC194 with the inputs shown in Figure 8–59. Inputs D0, D1,
D2, and D3 are all HIGH.

19. For the ring counter in Figure 8–60, show the waveforms for each flip-flop output with respect
Digital Electronics, Chapter 5
to the clock. Assume that FF0 is initially SET and that the rest are RESET. Show at least ten
clock pulses.

20. The waveform pattern in Figure 8–61 is required. Devise a ring counter, and indicate how it can
be preset to produce this waveform on its Q9 output. At CLK16 the pattern begins to repeat.